<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2020.02.21.15:02:43"
 outputDirectory="K:/Work/SP100/PROG/FPGA/gflish2/ip/gflish/gflish_jtag_uart_0/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Arria 10"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="10AS048H4F34E3SG"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="3"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="avalon_jtag_slave" kind="avalon" start="0">
   <property name="addressAlignment" value="NATIVE" />
   <property name="addressGroup" value="0" />
   <property name="addressSpan" value="2" />
   <property name="addressUnits" value="WORDS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="bridgedAddressOffset" value="0" />
   <property name="bridgesToMaster" value="" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="explicitAddressSpan" value="0" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isFlash" value="false" />
   <property name="isMemoryDevice" value="false" />
   <property name="isNonVolatileStorage" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="minimumUninterruptedRunLength" value="1" />
   <property name="prSafe" value="false" />
   <property name="printableDevice" value="true" />
   <property name="readLatency" value="0" />
   <property name="readWaitStates" value="1" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="transparentBridge" value="false" />
   <property name="waitrequestAllowance" value="0" />
   <property name="wellBehavedWaitrequest" value="false" />
   <property name="writeLatency" value="0" />
   <property name="writeWaitStates" value="0" />
   <property name="writeWaitTime" value="0" />
   <port name="av_chipselect" direction="input" role="chipselect" width="1" />
   <port name="av_address" direction="input" role="address" width="1" />
   <port name="av_read_n" direction="input" role="read_n" width="1" />
   <port name="av_readdata" direction="output" role="readdata" width="32" />
   <port name="av_write_n" direction="input" role="write_n" width="1" />
   <port name="av_writedata" direction="input" role="writedata" width="32" />
   <port name="av_waitrequest" direction="output" role="waitrequest" width="1" />
  </interface>
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="irq" kind="interrupt" start="0">
   <property
       name="associatedAddressablePoint"
       value="gflish_jtag_uart_0.avalon_jtag_slave" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bridgedReceiverOffset" value="0" />
   <property name="bridgesToReceiver" value="" />
   <property name="irqScheme" value="NONE" />
   <port name="av_irq" direction="output" role="irq" width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="clk" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="rst_n" direction="input" role="reset_n" width="1" />
  </interface>
 </perimeter>
 <entity kind="gflish_jtag_uart_0" version="1.0" name="gflish_jtag_uart_0">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE" value="10AS048H4F34E3SG" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
  <generatedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_jtag_uart_0\synth\gflish_jtag_uart_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_jtag_uart_0\synth\gflish_jtag_uart_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="K:/Work/SP100/PROG/FPGA/gflish2/ip/gflish/gflish_jtag_uart_0.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="gflish_jtag_uart_0">"Generating: gflish_jtag_uart_0"</message>
   <message level="Info" culprit="gflish_jtag_uart_0">"Generating: gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi"</message>
   <message level="Info" culprit="jtag_uart_0">Starting RTL generation for module 'gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi'</message>
   <message level="Info" culprit="jtag_uart_0">  Generation command is [exec E:/intelfpga_pro/18.0/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga_pro/18.0/quartus/bin64/perl/lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/europa -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/perl_lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin -I E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0012_jtag_uart_0_gen/ --quartus_dir=E:/intelfpga_pro/18.0/quartus --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0012_jtag_uart_0_gen//gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="jtag_uart_0">Done RTL generation for module 'gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi'</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_jtag_uart"
   version="18.0"
   name="gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi">
  <parameter name="readBufferDepth" value="64" />
  <parameter name="clkFreq" value="100000000" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="enableInteractiveInput" value="false" />
  <parameter name="avalonSpec" value="2.0" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="simInteractiveOptions" value="NO_INTERACTIVE_WINDOWS" />
  <parameter name="enableInteractiveOutput" value="false" />
  <parameter name="writeIRQThreshold" value="8" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="legacySignalAllow" value="false" />
  <generatedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_jtag_uart_0\altera_avalon_jtag_uart_180\synth\gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_jtag_uart_0\altera_avalon_jtag_uart_180\synth\gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="gflish_jtag_uart_0" as="jtag_uart_0" />
  <messages>
   <message level="Info" culprit="gflish_jtag_uart_0">"Generating: gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi"</message>
   <message level="Info" culprit="jtag_uart_0">Starting RTL generation for module 'gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi'</message>
   <message level="Info" culprit="jtag_uart_0">  Generation command is [exec E:/intelfpga_pro/18.0/quartus/bin64/perl/bin/perl.exe -I E:/intelfpga_pro/18.0/quartus/bin64/perl/lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/europa -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/perl_lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin -I E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/common -I E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- E:/intelfpga_pro/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0012_jtag_uart_0_gen/ --quartus_dir=E:/intelfpga_pro/18.0/quartus --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0012_jtag_uart_0_gen//gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="jtag_uart_0">Done RTL generation for module 'gflish_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi'</message>
  </messages>
 </entity>
</deploy>
