--scfifo DEVICE_FAMILY="Arria 10" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" RAM_BLOCK_TYPE="AUTO" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO"
--VERSION_BEGIN 18.0 cbx_altdpram 2018:04:11:18:04:13:SJ cbx_altera_counter 2018:04:11:18:04:13:SJ cbx_altera_syncram 2018:04:11:18:04:13:SJ cbx_altera_syncram_nd_impl 2018:04:11:18:04:13:SJ cbx_altsyncram 2018:04:11:18:04:13:SJ cbx_cycloneii 2018:04:11:18:04:13:SJ cbx_fifo_common 2018:04:11:18:04:13:SJ cbx_lpm_add_sub 2018:04:11:18:04:13:SJ cbx_lpm_compare 2018:04:11:18:04:13:SJ cbx_lpm_counter 2018:04:11:18:04:13:SJ cbx_lpm_decode 2018:04:11:18:04:13:SJ cbx_lpm_mux 2018:04:11:18:04:13:SJ cbx_mgl 2018:04:11:18:05:44:SJ cbx_nadder 2018:04:11:18:04:13:SJ cbx_scfifo 2018:04:11:18:04:13:SJ cbx_stratix 2018:04:11:18:04:13:SJ cbx_stratixii 2018:04:11:18:04:13:SJ cbx_stratixiii 2018:04:11:18:04:13:SJ cbx_stratixv 2018:04:11:18:04:13:SJ cbx_util_mgl 2018:04:11:18:04:13:SJ  VERSION_END


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FUNCTION a_dpfifo_5u41 (aclr, clock, data[7..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[7..0], usedw[5..0]);

--synthesis_resources = lut 18 M20K 1 reg 20 
SUBDESIGN scfifo_3p61
( 
	aclr	:	input;
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rdreq	:	input;
	usedw[5..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_5u41;
	sclr	: NODE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	empty = dpfifo.empty;
	full = dpfifo.full;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
END;
--VALID FILE
