// gflish_intel_generic_serial_flash_interface_top_0.v

// Generated using ACDS version 18.0 219

`timescale 1 ps / 1 ps
module gflish_intel_generic_serial_flash_interface_top_0 (
		input  wire [5:0]  avl_csr_address,       // avl_csr.address
		input  wire        avl_csr_read,          //        .read
		output wire [31:0] avl_csr_readdata,      //        .readdata
		input  wire        avl_csr_write,         //        .write
		input  wire [31:0] avl_csr_writedata,     //        .writedata
		output wire        avl_csr_waitrequest,   //        .waitrequest
		output wire        avl_csr_readdatavalid, //        .readdatavalid
		input  wire        avl_mem_write,         // avl_mem.write
		input  wire [6:0]  avl_mem_burstcount,    //        .burstcount
		output wire        avl_mem_waitrequest,   //        .waitrequest
		input  wire        avl_mem_read,          //        .read
		input  wire [22:0] avl_mem_address,       //        .address
		input  wire [31:0] avl_mem_writedata,     //        .writedata
		output wire [31:0] avl_mem_readdata,      //        .readdata
		output wire        avl_mem_readdatavalid, //        .readdatavalid
		input  wire [3:0]  avl_mem_byteenable,    //        .byteenable
		input  wire        clk_clk,               //     clk.clk
		input  wire        reset_reset            //   reset.reset
	);

	gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_top_180_h2f7kua #(
		.DEVICE_FAMILY ("Arria 10"),
		.CHIP_SELS     (1)
	) intel_generic_serial_flash_interface_top_0 (
		.avl_csr_address       (avl_csr_address),       //   input,   width = 6, avl_csr.address
		.avl_csr_read          (avl_csr_read),          //   input,   width = 1,        .read
		.avl_csr_readdata      (avl_csr_readdata),      //  output,  width = 32,        .readdata
		.avl_csr_write         (avl_csr_write),         //   input,   width = 1,        .write
		.avl_csr_writedata     (avl_csr_writedata),     //   input,  width = 32,        .writedata
		.avl_csr_waitrequest   (avl_csr_waitrequest),   //  output,   width = 1,        .waitrequest
		.avl_csr_readdatavalid (avl_csr_readdatavalid), //  output,   width = 1,        .readdatavalid
		.avl_mem_write         (avl_mem_write),         //   input,   width = 1, avl_mem.write
		.avl_mem_burstcount    (avl_mem_burstcount),    //   input,   width = 7,        .burstcount
		.avl_mem_waitrequest   (avl_mem_waitrequest),   //  output,   width = 1,        .waitrequest
		.avl_mem_read          (avl_mem_read),          //   input,   width = 1,        .read
		.avl_mem_address       (avl_mem_address),       //   input,  width = 23,        .address
		.avl_mem_writedata     (avl_mem_writedata),     //   input,  width = 32,        .writedata
		.avl_mem_readdata      (avl_mem_readdata),      //  output,  width = 32,        .readdata
		.avl_mem_readdatavalid (avl_mem_readdatavalid), //  output,   width = 1,        .readdatavalid
		.avl_mem_byteenable    (avl_mem_byteenable),    //   input,   width = 4,        .byteenable
		.clk_clk               (clk_clk),               //   input,   width = 1,     clk.clk
		.reset_reset           (reset_reset)            //   input,   width = 1,   reset.reset
	);

endmodule
