<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2020.02.21.15:03:00"
 outputDirectory="K:/Work/SP100/PROG/FPGA/gflish2/ip/gflish/gflish_nios2_gen2_0/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Arria 10"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="10AS048H4F34E3SG"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="3"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DATA_MASTER_ADDRESS_MAP"
     type="AddressMap"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DATA_MASTER_ADDRESS_WIDTH"
     type="AddressWidthType"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_INSTRUCTION_MASTER_ADDRESS_MAP"
     type="AddressMap"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_INSTRUCTION_MASTER_ADDRESS_WIDTH"
     type="AddressWidthType"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_IRQ_INTERRUPTS_USED"
     type="BigInteger"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk" direction="input" role="clk" width="1" />
  </interface>
  <interface
     name="custom_instruction_master"
     kind="nios_custom_instruction"
     start="1">
   <property name="CIName" value="" />
   <property name="addressWidth" value="8" />
   <property name="clockCycle" value="0" />
   <property name="enabled" value="false" />
   <property name="maxAddressWidth" value="8" />
   <property name="opcodeExtension" value="0" />
   <property name="sharedCombinationalAndMulticycle" value="false" />
   <port name="dummy_ci_port" direction="output" role="readra" width="1" />
  </interface>
  <interface name="data_master" kind="avalon" start="1">
   <property name="adaptsTo" value="" />
   <property name="addressGroup" value="1" />
   <property name="addressUnits" value="SYMBOLS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="burstOnBurstBoundariesOnly" value="true" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="dBSBigEndian" value="false" />
   <property name="doStreamReads" value="false" />
   <property name="doStreamWrites" value="false" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isAsynchronous" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isReadable" value="false" />
   <property name="isWriteable" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maxAddressWidth" value="32" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="prSafe" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="waitrequestAllowance" value="0" />
   <property name="writeWaitTime" value="0" />
   <port name="d_address" direction="output" role="address" width="26" />
   <port name="d_byteenable" direction="output" role="byteenable" width="4" />
   <port name="d_read" direction="output" role="read" width="1" />
   <port name="d_readdata" direction="input" role="readdata" width="32" />
   <port name="d_waitrequest" direction="input" role="waitrequest" width="1" />
   <port name="d_write" direction="output" role="write" width="1" />
   <port name="d_writedata" direction="output" role="writedata" width="32" />
   <port
       name="d_readdatavalid"
       direction="input"
       role="readdatavalid"
       width="1" />
   <port
       name="debug_mem_slave_debugaccess_to_roms"
       direction="output"
       role="debugaccess"
       width="1" />
  </interface>
  <interface name="debug_mem_slave" kind="avalon" start="0">
   <property name="addressAlignment" value="DYNAMIC" />
   <property name="addressGroup" value="0" />
   <property name="addressSpan" value="2048" />
   <property name="addressUnits" value="WORDS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="bridgedAddressOffset" value="0" />
   <property name="bridgesToMaster" value="" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="explicitAddressSpan" value="0" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isFlash" value="false" />
   <property name="isMemoryDevice" value="true" />
   <property name="isNonVolatileStorage" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="minimumUninterruptedRunLength" value="1" />
   <property name="prSafe" value="false" />
   <property name="printableDevice" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitStates" value="1" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="true" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="transparentBridge" value="false" />
   <property name="waitrequestAllowance" value="0" />
   <property name="wellBehavedWaitrequest" value="false" />
   <property name="writeLatency" value="0" />
   <property name="writeWaitStates" value="0" />
   <property name="writeWaitTime" value="0" />
   <port
       name="debug_mem_slave_address"
       direction="input"
       role="address"
       width="9" />
   <port
       name="debug_mem_slave_byteenable"
       direction="input"
       role="byteenable"
       width="4" />
   <port
       name="debug_mem_slave_debugaccess"
       direction="input"
       role="debugaccess"
       width="1" />
   <port name="debug_mem_slave_read" direction="input" role="read" width="1" />
   <port
       name="debug_mem_slave_readdata"
       direction="output"
       role="readdata"
       width="32" />
   <port
       name="debug_mem_slave_waitrequest"
       direction="output"
       role="waitrequest"
       width="1" />
   <port name="debug_mem_slave_write" direction="input" role="write" width="1" />
   <port
       name="debug_mem_slave_writedata"
       direction="input"
       role="writedata"
       width="32" />
  </interface>
  <interface name="debug_reset_request" kind="reset" start="1">
   <property name="associatedClock" value="clk" />
   <property name="associatedDirectReset" value="" />
   <property name="associatedResetSinks" value="none" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="debug_reset_request" direction="output" role="reset" width="1" />
  </interface>
  <interface name="instruction_master" kind="avalon" start="1">
   <property name="adaptsTo" value="" />
   <property name="addressGroup" value="1" />
   <property name="addressUnits" value="SYMBOLS" />
   <property name="alwaysBurstMaxBurst" value="true" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="dBSBigEndian" value="false" />
   <property name="doStreamReads" value="false" />
   <property name="doStreamWrites" value="false" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isAsynchronous" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isReadable" value="false" />
   <property name="isWriteable" value="false" />
   <property name="linewrapBursts" value="true" />
   <property name="maxAddressWidth" value="32" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="prSafe" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="waitrequestAllowance" value="0" />
   <property name="writeWaitTime" value="0" />
   <port name="i_address" direction="output" role="address" width="26" />
   <port name="i_read" direction="output" role="read" width="1" />
   <port name="i_readdata" direction="input" role="readdata" width="32" />
   <port name="i_waitrequest" direction="input" role="waitrequest" width="1" />
   <port
       name="i_readdatavalid"
       direction="input"
       role="readdatavalid"
       width="1" />
  </interface>
  <interface name="irq" kind="interrupt" start="1">
   <property
       name="associatedAddressablePoint"
       value="gflish_nios2_gen2_0.data_master" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="irqMap" value="" />
   <property name="irqScheme" value="INDIVIDUAL_REQUESTS" />
   <port name="irq" direction="input" role="irq" width="32" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="clk" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="reset_n" direction="input" role="reset_n" width="1" />
   <port name="reset_req" direction="input" role="reset_req" width="1" />
  </interface>
 </perimeter>
 <entity kind="gflish_nios2_gen2_0" version="1.0" name="gflish_nios2_gen2_0">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_IRQ_INTERRUPTS_USED" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
  <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_MAP" value="" />
  <parameter name="AUTO_DATA_MASTER_ADDRESS_MAP" value="" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
  <parameter name="AUTO_DATA_MASTER_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_DEVICE" value="10AS048H4F34E3SG" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <generatedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\synth\gflish_nios2_gen2_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\synth\gflish_nios2_gen2_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="K:/Work/SP100/PROG/FPGA/gflish2/ip/gflish/gflish_nios2_gen2_0.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0"</message>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci"</message>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi"</message>
   <message level="Info" culprit="cpu">Starting RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
   <message level="Info" culprit="cpu">  Generation command is [exec E:/intelfpga_pro/18.0/quartus/bin64//eperlcmd.exe -I E:/intelfpga_pro/18.0/quartus/bin64//perl/lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/europa -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/perl_lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen/ --quartus_bindir=E:/intelfpga_pro/18.0/quartus/bin64/ --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen//gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_processor_configuration.pl  --do_build_sim=0    --pro_version=1  ]</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*) Starting Nios II generation</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*)   Checking for plaintext license.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Plaintext license not found.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Checking for encrypted license (non-evaluation).</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Encrypted license found.  SOF will not be time-limited.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Elaborating CPU configuration settings</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Creating all objects for CPU</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Testbench</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Instruction decoding</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction fields</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction decodes</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Signals for RTL simulation waveforms</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Instruction controls</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline frontend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline backend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:57 (*)   Generating RTL from CPU objects</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:59 (*)   Creating encrypted RTL</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:03:00 (*) Done Nios II generation</message>
   <message level="Info" culprit="cpu">Done RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
  </messages>
 </entity>
 <entity
   kind="altera_nios2_gen2"
   version="18.0"
   name="gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci">
  <parameter name="mpx_enabled" value="false" />
  <parameter name="ocimem_ramBlockType" value="Automatic" />
  <parameter name="dcache_victim_buf_impl" value="ram" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_ic_ecc_present" value="true" />
  <parameter name="dcache_size_derived" value="2048" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter
     name="deviceFeaturesSystemInfo"
     value="ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0" />
  <parameter name="bht_ramBlockType" value="Automatic" />
  <parameter name="mmu_TLBMissExcSlave" value="None" />
  <parameter name="impl" value="Fast" />
  <parameter name="setting_branchpredictiontype" value="Dynamic" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
  <parameter name="breakOffset" value="32" />
  <parameter name="setting_activateTrace" value="false" />
  <parameter name="debug_offchiptrace" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="setting_tmr_output_disable" value="false" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="AUTO_DEVICE" value="10AS048H4F34E3SG" />
  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="debug_onchiptrace" value="false" />
  <parameter name="setting_rf_ecc_present" value="true" />
  <parameter name="ocimem_ramInit" value="false" />
  <parameter name="internalIrqMaskSystemInfo" value="1" />
  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
  <parameter name="exceptionAbsoluteAddr" value="33685536" />
  <parameter name="icache_size" value="2048" />
  <parameter
     name="dataSlaveMapParam"
     value="&lt;address-map&gt;&lt;slave name=&apos;gfilsh.avl_mem&apos; start=&apos;0x0&apos; end=&apos;0x2000000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;main_memory.s1&apos; start=&apos;0x2020000&apos; end=&apos;0x2039000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;nios2.debug_mem_slave&apos; start=&apos;0x2040800&apos; end=&apos;0x2041000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;gfilsh.avl_csr&apos; start=&apos;0x2041100&apos; end=&apos;0x2041200&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x2041200&apos; end=&apos;0x2041208&apos; datawidth=&apos;32&apos; /&gt;&lt;/address-map&gt;" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="flash_instruction_master_paddr_size" value="0" />
  <parameter name="setting_ecc_present" value="false" />
  <parameter name="stratix_dspblock_shift_mul" value="false" />
  <parameter name="shift_rot_impl" value="1" />
  <parameter name="setting_ioregionBypassDCache" value="false" />
  <parameter name="register_file_por" value="false" />
  <parameter name="faAddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="exceptionSlave" value="main_memory.s1" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dataAddrWidth" value="26" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="instAddrWidth" value="26" />
  <parameter name="io_regionbase" value="0" />
  <parameter name="mul_32_impl" value="2" />
  <parameter name="translate_on" value=" &quot;synthesis translate_on&quot;  " />
  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="instruction_master_paddr_base" value="0" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="mul_64_impl" value="0" />
  <parameter name="clockFrequency" value="100000000" />
  <parameter name="resetOffset" value="0" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="mul_shift_choice" value="0" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
  <parameter name="setting_asic_third_party_synthesis" value="false" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="setting_exportdebuginfo" value="false" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="resetSlave" value="main_memory.s1" />
  <parameter name="dcache_bursts_derived" value="false" />
  <parameter name="multiplierType" value="mul_fast32" />
  <parameter name="debug_traceStorage" value="onchip_trace" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="fa_cache_linesize" value="0" />
  <parameter name="data_master_paddr_size" value="0" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="setting_disableocitrace" value="false" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
  <parameter name="debug_datatrigger" value="0" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="debug_enabled" value="true" />
  <parameter name="setting_export_large_RAMs" value="false" />
  <parameter name="setting_dc_ecc_present" value="true" />
  <parameter name="dividerType" value="no_div" />
  <parameter name="setting_exportvectors" value="false" />
  <parameter name="breakSlave_derived" value="nios2.debug_mem_slave" />
  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
  <parameter name="mmu_ramBlockType" value="Automatic" />
  <parameter name="cdx_enabled" value="false" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
  <parameter name="customInstSlavesSystemInfo" value="" />
  <parameter name="tracefilename" value="" />
  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
  <parameter name="setting_oci_version" value="1" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="data_master_high_performance_paddr_size" value="0" />
  <parameter name="setting_disable_tmr_inj" value="false" />
  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
  <parameter name="regfile_ramBlockType" value="Automatic" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="breakSlave" value="None" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="breakAbsoluteAddr" value="33818656" />
  <parameter name="setting_ecc_sim_test_ports" value="false" />
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="master_addr_map" value="false" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="resetAbsoluteAddr" value="33685504" />
  <parameter name="cpuArchRev" value="1" />
  <parameter name="setting_dtcm_ecc_present" value="true" />
  <parameter name="customInstSlavesSystemInfo_nios_c" value="" />
  <parameter name="customInstSlavesSystemInfo_nios_b" value="" />
  <parameter name="customInstSlavesSystemInfo_nios_a" value="" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="dcache_tagramBlockType" value="Automatic" />
  <parameter name="debug_insttrace" value="false" />
  <parameter name="setting_itcm_ecc_present" value="true" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
  <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="setting_usedesignware" value="false" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="instruction_master_paddr_size" value="0" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="cpuID" value="0" />
  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
  <parameter name="setting_asic_enabled" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_asic_add_scan_mode_input" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="faSlaveMapParam" value="" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="fa_cache_line" value="2" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
  <parameter name="setting_allow_break_inst" value="false" />
  <parameter name="io_regionsize" value="0" />
  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
  <parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="flash_instruction_master_paddr_base" value="0" />
  <parameter name="cpuReset" value="false" />
  <parameter name="setting_removeRAMinit" value="false" />
  <parameter name="icache_tagramBlockType" value="Automatic" />
  <parameter name="setting_mmu_ecc_present" value="true" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
  <parameter name="debug_datatrace" value="false" />
  <parameter name="debug_hwbreakpoint" value="0" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  <parameter name="dataMasterHighPerformanceMapParam" value="" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="setting_breakslaveoveride" value="false" />
  <parameter name="debug_traceType" value="none" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_oci_export_jtag_signals" value="false" />
  <parameter name="dcache_lineSize_derived" value="32" />
  <parameter name="deviceFamilyName" value="Arria 10" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="setting_support31bitdcachebypass" value="true" />
  <parameter
     name="instSlaveMapParam"
     value="&lt;address-map&gt;&lt;slave name=&apos;main_memory.s1&apos; start=&apos;0x2020000&apos; end=&apos;0x2039000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;nios2.debug_mem_slave&apos; start=&apos;0x2040800&apos; end=&apos;0x2041000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;gfilsh.avl_csr&apos; start=&apos;0x2041100&apos; end=&apos;0x2041200&apos; datawidth=&apos;32&apos; /&gt;&lt;/address-map&gt;" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="setting_exportHostDebugPort" value="false" />
  <parameter name="tmr_enabled" value="false" />
  <parameter name="data_master_paddr_base" value="0" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="data_master_high_performance_paddr_base" value="0" />
  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
  <parameter name="setting_fast_register_read" value="false" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="shifterType" value="fast_le_shift" />
  <generatedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="gflish_nios2_gen2_0" as="nios2_gen2_0" />
  <messages>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci"</message>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi"</message>
   <message level="Info" culprit="cpu">Starting RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
   <message level="Info" culprit="cpu">  Generation command is [exec E:/intelfpga_pro/18.0/quartus/bin64//eperlcmd.exe -I E:/intelfpga_pro/18.0/quartus/bin64//perl/lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/europa -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/perl_lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen/ --quartus_bindir=E:/intelfpga_pro/18.0/quartus/bin64/ --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen//gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_processor_configuration.pl  --do_build_sim=0    --pro_version=1  ]</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*) Starting Nios II generation</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*)   Checking for plaintext license.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Plaintext license not found.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Checking for encrypted license (non-evaluation).</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Encrypted license found.  SOF will not be time-limited.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Elaborating CPU configuration settings</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Creating all objects for CPU</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Testbench</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Instruction decoding</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction fields</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction decodes</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Signals for RTL simulation waveforms</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Instruction controls</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline frontend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline backend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:57 (*)   Generating RTL from CPU objects</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:59 (*)   Creating encrypted RTL</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:03:00 (*) Done Nios II generation</message>
   <message level="Info" culprit="cpu">Done RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
  </messages>
 </entity>
 <entity
   kind="altera_nios2_gen2_unit"
   version="18.0"
   name="gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi">
  <parameter name="icache_burstType" value="None" />
  <parameter name="setting_oci_version" value="1" />
  <parameter name="mpx_enabled" value="false" />
  <parameter name="ocimem_ramBlockType" value="Automatic" />
  <parameter name="dcache_victim_buf_impl" value="ram" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_ic_ecc_present" value="true" />
  <parameter name="dcache_size_derived" value="2048" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_top" value="0" />
  <parameter
     name="deviceFeaturesSystemInfo"
     value="ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0" />
  <parameter name="bht_ramBlockType" value="Automatic" />
  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
  <parameter name="mmu_TLBMissExcSlave" value="None" />
  <parameter name="impl" value="Fast" />
  <parameter name="regfile_ramBlockType" value="Automatic" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="tightly_coupled_data_master_0_paddr_top" value="0" />
  <parameter name="breakOffset" value="32" />
  <parameter name="breakSlave" value="None" />
  <parameter name="setting_branchPredictionType" value="Dynamic" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="flash_instruction_master_paddr_top" value="0" />
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="cpu_name" value="cpu" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="breakAbsoluteAddr" value="33818656" />
  <parameter name="setting_activateTrace" value="false" />
  <parameter name="debug_offchiptrace" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="setting_ecc_sim_test_ports" value="false" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="master_addr_map" value="false" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="debug_onchiptrace" value="false" />
  <parameter name="setting_rf_ecc_present" value="true" />
  <parameter name="resetAbsoluteAddr" value="33685504" />
  <parameter name="tightly_coupled_data_master_1_paddr_top" value="0" />
  <parameter name="ocimem_ramInit" value="false" />
  <parameter name="internalIrqMaskSystemInfo" value="1" />
  <parameter name="instruction_master_paddr_top" value="0" />
  <parameter name="cpuArchRev" value="1" />
  <parameter name="setting_dtcm_ecc_present" value="true" />
  <parameter name="exceptionAbsoluteAddr" value="33685536" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="dcache_tagramBlockType" value="Automatic" />
  <parameter name="debug_insttrace" value="false" />
  <parameter name="icache_size" value="2048" />
  <parameter name="setting_itcm_ecc_present" value="true" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
  <parameter
     name="dataSlaveMapParam"
     value="&lt;address-map&gt;&lt;slave name=&apos;gfilsh.avl_mem&apos; start=&apos;0x0&apos; end=&apos;0x2000000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;main_memory.s1&apos; start=&apos;0x2020000&apos; end=&apos;0x2039000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;nios2.debug_mem_slave&apos; start=&apos;0x2040800&apos; end=&apos;0x2041000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;gfilsh.avl_csr&apos; start=&apos;0x2041100&apos; end=&apos;0x2041200&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;jtag_uart.avalon_jtag_slave&apos; start=&apos;0x2041200&apos; end=&apos;0x2041208&apos; datawidth=&apos;32&apos; /&gt;&lt;/address-map&gt;" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="setting_ecc_present" value="false" />
  <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="stratix_dspblock_shift_mul" value="false" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="setting_usedesignware" value="false" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="instruction_master_high_performance_paddr_top" value="0" />
  <parameter name="setting_ioregionBypassDCache" value="false" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="register_file_por" value="false" />
  <parameter name="faAddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightly_coupled_data_master_3_paddr_top" value="0" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="cpuID" value="0" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="setting_asic_enabled" value="false" />
  <parameter name="exceptionSlave" value="main_memory.s1" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dataAddrWidth" value="26" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="instAddrWidth" value="26" />
  <parameter name="setting_asic_add_scan_mode_input" value="false" />
  <parameter name="tightly_coupled_instruction_master_1_paddr_top" value="0" />
  <parameter name="io_regionbase" value="0" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="data_master_paddr_top" value="0" />
  <parameter name="translate_on" value=" &quot;synthesis translate_on&quot;  " />
  <parameter name="faSlaveMapParam" value="" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="fa_cache_line" value="2" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="instruction_master_paddr_base" value="0" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="clockFrequency" value="100000000" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="resetOffset" value="0" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightly_coupled_instruction_master_0_paddr_top" value="0" />
  <parameter name="setting_allow_break_inst" value="false" />
  <parameter name="setting_asic_third_party_synthesis" value="false" />
  <parameter name="io_regionsize" value="0" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
  <parameter name="translate_off" value=" &quot;synthesis translate_off&quot; " />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="flash_instruction_master_paddr_base" value="0" />
  <parameter name="setting_exportdebuginfo" value="false" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="cpuReset" value="false" />
  <parameter name="resetSlave" value="main_memory.s1" />
  <parameter name="dcache_bursts_derived" value="false" />
  <parameter name="multiplierType" value="mul_fast32" />
  <parameter name="setting_removeRAMinit" value="false" />
  <parameter name="icache_tagramBlockType" value="Automatic" />
  <parameter name="debug_traceStorage" value="onchip_trace" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="fa_cache_linesize" value="0" />
  <parameter name="setting_mmu_ecc_present" value="true" />
  <parameter name="debug_datatrace" value="false" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="debug_hwbreakpoint" value="0" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  <parameter name="dataMasterHighPerformanceMapParam" value="" />
  <parameter name="tightly_coupled_data_master_2_paddr_top" value="0" />
  <parameter name="setting_disableocitrace" value="false" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_breakslaveoveride" value="false" />
  <parameter name="debug_traceType" value="none" />
  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
  <parameter name="tightly_coupled_instruction_master_2_paddr_top" value="0" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_oci_export_jtag_signals" value="false" />
  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
  <parameter name="data_master_high_performance_paddr_top" value="0" />
  <parameter name="dcache_lineSize_derived" value="32" />
  <parameter name="deviceFamilyName" value="Arria 10" />
  <parameter name="debug_datatrigger" value="0" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="debug_enabled" value="true" />
  <parameter name="setting_export_large_RAMs" value="false" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="setting_dc_ecc_present" value="true" />
  <parameter name="setting_support31bitdcachebypass" value="true" />
  <parameter
     name="instSlaveMapParam"
     value="&lt;address-map&gt;&lt;slave name=&apos;main_memory.s1&apos; start=&apos;0x2020000&apos; end=&apos;0x2039000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;nios2.debug_mem_slave&apos; start=&apos;0x2040800&apos; end=&apos;0x2041000&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;gfilsh.avl_csr&apos; start=&apos;0x2041100&apos; end=&apos;0x2041200&apos; datawidth=&apos;32&apos; /&gt;&lt;/address-map&gt;" />
  <parameter name="dividerType" value="no_div" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="setting_exportvectors" value="false" />
  <parameter name="tmr_enabled" value="false" />
  <parameter name="data_master_paddr_base" value="0" />
  <parameter name="breakSlave_derived" value="nios2.debug_mem_slave" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
  <parameter name="mmu_ramBlockType" value="Automatic" />
  <parameter name="data_master_high_performance_paddr_base" value="0" />
  <parameter name="cdx_enabled" value="false" />
  <parameter name="customInstSlavesSystemInfo" value="" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="tracefilename" value="" />
  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
  <parameter name="setting_fast_register_read" value="false" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="shifterType" value="fast_le_shift" />
  <generatedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.ocp"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_bht_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_dc_tag_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_sysclk.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_tck.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_wrapper.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_ic_tag_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_mult_cell.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_ociram_default_contents.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_rf_ram_a.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_rf_ram_b.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_test_bench.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.ocp"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_bht_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_dc_tag_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_sysclk.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_tck.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_wrapper.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_ic_tag_ram.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_mult_cell.v"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_ociram_default_contents.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_rf_ram_a.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_rf_ram_b.mif"
       attributes="" />
   <file
       path="K:\Work\SP100\PROG\FPGA\gflish2\ip\gflish\gflish_nios2_gen2_0\altera_nios2_gen2_unit_180\synth\gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_test_bench.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="E:/intelfpga_pro/18.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="gflish_nios2_gen2_0_altera_nios2_gen2_180_z4tmuci"
     as="cpu" />
  <messages>
   <message level="Info" culprit="gflish_nios2_gen2_0">"Generating: gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi"</message>
   <message level="Info" culprit="cpu">Starting RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
   <message level="Info" culprit="cpu">  Generation command is [exec E:/intelfpga_pro/18.0/quartus/bin64//eperlcmd.exe -I E:/intelfpga_pro/18.0/quartus/bin64//perl/lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/europa -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin/perl_lib -I E:/intelfpga_pro/18.0/quartus/sopc_builder/bin -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- E:/intelfpga_pro/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi --dir=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen/ --quartus_bindir=E:/intelfpga_pro/18.0/quartus/bin64/ --verilog --config=C:/Users/ADMINI~1/AppData/Local/Temp/alt8313_7876297934862453575.dir/0013_cpu_gen//gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_processor_configuration.pl  --do_build_sim=0    --pro_version=1  ]</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*) Starting Nios II generation</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:50 (*)   Checking for plaintext license.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Plaintext license not found.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:52 (*)   Checking for encrypted license (non-evaluation).</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Encrypted license found.  SOF will not be time-limited.</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Elaborating CPU configuration settings</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)   Creating all objects for CPU</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Testbench</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)     Instruction decoding</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction fields</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:54 (*)       Instruction decodes</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Signals for RTL simulation waveforms</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)       Instruction controls</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline frontend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:55 (*)     Pipeline backend</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:57 (*)   Generating RTL from CPU objects</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:02:59 (*)   Creating encrypted RTL</message>
   <message level="Info" culprit="cpu"># 2020.02.21 15:03:00 (*) Done Nios II generation</message>
   <message level="Info" culprit="cpu">Done RTL generation for module 'gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi'</message>
  </messages>
 </entity>
</deploy>
