// gflish.v

// Generated using ACDS version 18.0 219

`timescale 1 ps / 1 ps
module gflish (
		input  wire  clk_clk,     //   clk.clk
		input  wire  reset_reset  // reset.reset
	);

	wire         sys_clk_out_clk_clk;                                       // sys_clk:out_clk -> [gfilsh:clk_clk, irq_mapper:clk, jtag_uart:clk, main_memory:clk, mm_interconnect_0:sys_clk_out_clk_clk, nios2:clk, reset_in:clk, rst_controller_001:clk]
	wire  [31:0] nios2_data_master_readdata;                                // mm_interconnect_0:nios2_data_master_readdata -> nios2:d_readdata
	wire         nios2_data_master_waitrequest;                             // mm_interconnect_0:nios2_data_master_waitrequest -> nios2:d_waitrequest
	wire         nios2_data_master_debugaccess;                             // nios2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_data_master_debugaccess
	wire  [25:0] nios2_data_master_address;                                 // nios2:d_address -> mm_interconnect_0:nios2_data_master_address
	wire   [3:0] nios2_data_master_byteenable;                              // nios2:d_byteenable -> mm_interconnect_0:nios2_data_master_byteenable
	wire         nios2_data_master_read;                                    // nios2:d_read -> mm_interconnect_0:nios2_data_master_read
	wire         nios2_data_master_readdatavalid;                           // mm_interconnect_0:nios2_data_master_readdatavalid -> nios2:d_readdatavalid
	wire         nios2_data_master_write;                                   // nios2:d_write -> mm_interconnect_0:nios2_data_master_write
	wire  [31:0] nios2_data_master_writedata;                               // nios2:d_writedata -> mm_interconnect_0:nios2_data_master_writedata
	wire  [31:0] nios2_instruction_master_readdata;                         // mm_interconnect_0:nios2_instruction_master_readdata -> nios2:i_readdata
	wire         nios2_instruction_master_waitrequest;                      // mm_interconnect_0:nios2_instruction_master_waitrequest -> nios2:i_waitrequest
	wire  [25:0] nios2_instruction_master_address;                          // nios2:i_address -> mm_interconnect_0:nios2_instruction_master_address
	wire         nios2_instruction_master_read;                             // nios2:i_read -> mm_interconnect_0:nios2_instruction_master_read
	wire         nios2_instruction_master_readdatavalid;                    // mm_interconnect_0:nios2_instruction_master_readdatavalid -> nios2:i_readdatavalid
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;  // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;    // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address;     // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;        // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;       // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;   // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire  [31:0] mm_interconnect_0_gfilsh_avl_csr_readdata;                 // gfilsh:avl_csr_readdata -> mm_interconnect_0:gfilsh_avl_csr_readdata
	wire         mm_interconnect_0_gfilsh_avl_csr_waitrequest;              // gfilsh:avl_csr_waitrequest -> mm_interconnect_0:gfilsh_avl_csr_waitrequest
	wire   [5:0] mm_interconnect_0_gfilsh_avl_csr_address;                  // mm_interconnect_0:gfilsh_avl_csr_address -> gfilsh:avl_csr_address
	wire         mm_interconnect_0_gfilsh_avl_csr_read;                     // mm_interconnect_0:gfilsh_avl_csr_read -> gfilsh:avl_csr_read
	wire         mm_interconnect_0_gfilsh_avl_csr_readdatavalid;            // gfilsh:avl_csr_readdatavalid -> mm_interconnect_0:gfilsh_avl_csr_readdatavalid
	wire         mm_interconnect_0_gfilsh_avl_csr_write;                    // mm_interconnect_0:gfilsh_avl_csr_write -> gfilsh:avl_csr_write
	wire  [31:0] mm_interconnect_0_gfilsh_avl_csr_writedata;                // mm_interconnect_0:gfilsh_avl_csr_writedata -> gfilsh:avl_csr_writedata
	wire  [31:0] mm_interconnect_0_gfilsh_avl_mem_readdata;                 // gfilsh:avl_mem_readdata -> mm_interconnect_0:gfilsh_avl_mem_readdata
	wire         mm_interconnect_0_gfilsh_avl_mem_waitrequest;              // gfilsh:avl_mem_waitrequest -> mm_interconnect_0:gfilsh_avl_mem_waitrequest
	wire  [22:0] mm_interconnect_0_gfilsh_avl_mem_address;                  // mm_interconnect_0:gfilsh_avl_mem_address -> gfilsh:avl_mem_address
	wire         mm_interconnect_0_gfilsh_avl_mem_read;                     // mm_interconnect_0:gfilsh_avl_mem_read -> gfilsh:avl_mem_read
	wire   [3:0] mm_interconnect_0_gfilsh_avl_mem_byteenable;               // mm_interconnect_0:gfilsh_avl_mem_byteenable -> gfilsh:avl_mem_byteenable
	wire         mm_interconnect_0_gfilsh_avl_mem_readdatavalid;            // gfilsh:avl_mem_readdatavalid -> mm_interconnect_0:gfilsh_avl_mem_readdatavalid
	wire         mm_interconnect_0_gfilsh_avl_mem_write;                    // mm_interconnect_0:gfilsh_avl_mem_write -> gfilsh:avl_mem_write
	wire  [31:0] mm_interconnect_0_gfilsh_avl_mem_writedata;                // mm_interconnect_0:gfilsh_avl_mem_writedata -> gfilsh:avl_mem_writedata
	wire   [6:0] mm_interconnect_0_gfilsh_avl_mem_burstcount;               // mm_interconnect_0:gfilsh_avl_mem_burstcount -> gfilsh:avl_mem_burstcount
	wire  [31:0] mm_interconnect_0_nios2_debug_mem_slave_readdata;          // nios2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_debug_mem_slave_waitrequest;       // nios2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_debug_mem_slave_debugaccess;       // mm_interconnect_0:nios2_debug_mem_slave_debugaccess -> nios2:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_debug_mem_slave_address;           // mm_interconnect_0:nios2_debug_mem_slave_address -> nios2:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_debug_mem_slave_read;              // mm_interconnect_0:nios2_debug_mem_slave_read -> nios2:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_debug_mem_slave_byteenable;        // mm_interconnect_0:nios2_debug_mem_slave_byteenable -> nios2:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_debug_mem_slave_write;             // mm_interconnect_0:nios2_debug_mem_slave_write -> nios2:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_debug_mem_slave_writedata;         // mm_interconnect_0:nios2_debug_mem_slave_writedata -> nios2:debug_mem_slave_writedata
	wire         mm_interconnect_0_main_memory_s1_chipselect;               // mm_interconnect_0:main_memory_s1_chipselect -> main_memory:chipselect
	wire  [31:0] mm_interconnect_0_main_memory_s1_readdata;                 // main_memory:readdata -> mm_interconnect_0:main_memory_s1_readdata
	wire  [14:0] mm_interconnect_0_main_memory_s1_address;                  // mm_interconnect_0:main_memory_s1_address -> main_memory:address
	wire   [3:0] mm_interconnect_0_main_memory_s1_byteenable;               // mm_interconnect_0:main_memory_s1_byteenable -> main_memory:byteenable
	wire         mm_interconnect_0_main_memory_s1_write;                    // mm_interconnect_0:main_memory_s1_write -> main_memory:write
	wire  [31:0] mm_interconnect_0_main_memory_s1_writedata;                // mm_interconnect_0:main_memory_s1_writedata -> main_memory:writedata
	wire         mm_interconnect_0_main_memory_s1_clken;                    // mm_interconnect_0:main_memory_s1_clken -> main_memory:clken
	wire         irq_mapper_receiver0_irq;                                  // jtag_uart:av_irq -> irq_mapper:receiver0_irq
	wire  [31:0] nios2_irq_irq;                                             // irq_mapper:sender_irq -> nios2:irq
	wire         rst_controller_reset_out_reset;                            // rst_controller:reset_out -> gfilsh:reset_reset
	wire         nios2_debug_reset_request_reset;                           // nios2:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
	wire         reset_in_out_reset_reset;                                  // reset_in:out_reset -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
	wire         rst_controller_001_reset_out_reset;                        // rst_controller_001:reset_out -> [irq_mapper:reset, jtag_uart:rst_n, main_memory:reset, mm_interconnect_0:nios2_reset_reset_bridge_in_reset_reset, nios2:reset_n, rst_translator:in_reset]
	wire         rst_controller_001_reset_out_reset_req;                    // rst_controller_001:reset_req -> [main_memory:reset_req, nios2:reset_req, rst_translator:reset_req_in]

	gflish_intel_generic_serial_flash_interface_top_0 gfilsh (
		.avl_csr_address       (mm_interconnect_0_gfilsh_avl_csr_address),       //   input,   width = 6, avl_csr.address
		.avl_csr_read          (mm_interconnect_0_gfilsh_avl_csr_read),          //   input,   width = 1,        .read
		.avl_csr_readdata      (mm_interconnect_0_gfilsh_avl_csr_readdata),      //  output,  width = 32,        .readdata
		.avl_csr_write         (mm_interconnect_0_gfilsh_avl_csr_write),         //   input,   width = 1,        .write
		.avl_csr_writedata     (mm_interconnect_0_gfilsh_avl_csr_writedata),     //   input,  width = 32,        .writedata
		.avl_csr_waitrequest   (mm_interconnect_0_gfilsh_avl_csr_waitrequest),   //  output,   width = 1,        .waitrequest
		.avl_csr_readdatavalid (mm_interconnect_0_gfilsh_avl_csr_readdatavalid), //  output,   width = 1,        .readdatavalid
		.avl_mem_write         (mm_interconnect_0_gfilsh_avl_mem_write),         //   input,   width = 1, avl_mem.write
		.avl_mem_burstcount    (mm_interconnect_0_gfilsh_avl_mem_burstcount),    //   input,   width = 7,        .burstcount
		.avl_mem_waitrequest   (mm_interconnect_0_gfilsh_avl_mem_waitrequest),   //  output,   width = 1,        .waitrequest
		.avl_mem_read          (mm_interconnect_0_gfilsh_avl_mem_read),          //   input,   width = 1,        .read
		.avl_mem_address       (mm_interconnect_0_gfilsh_avl_mem_address),       //   input,  width = 23,        .address
		.avl_mem_writedata     (mm_interconnect_0_gfilsh_avl_mem_writedata),     //   input,  width = 32,        .writedata
		.avl_mem_readdata      (mm_interconnect_0_gfilsh_avl_mem_readdata),      //  output,  width = 32,        .readdata
		.avl_mem_readdatavalid (mm_interconnect_0_gfilsh_avl_mem_readdatavalid), //  output,   width = 1,        .readdatavalid
		.avl_mem_byteenable    (mm_interconnect_0_gfilsh_avl_mem_byteenable),    //   input,   width = 4,        .byteenable
		.clk_clk               (sys_clk_out_clk_clk),                            //   input,   width = 1,     clk.clk
		.reset_reset           (rst_controller_reset_out_reset)                  //   input,   width = 1,   reset.reset
	);

	gflish_jtag_uart_0 jtag_uart (
		.av_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  //   input,   width = 1, avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //   input,   width = 1,                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),       //   input,   width = 1,                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //  output,  width = 32,                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),      //   input,   width = 1,                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //   input,  width = 32,                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //  output,   width = 1,                  .waitrequest
		.clk            (sys_clk_out_clk_clk),                                       //   input,   width = 1,               clk.clk
		.av_irq         (irq_mapper_receiver0_irq),                                  //  output,   width = 1,               irq.irq
		.rst_n          (~rst_controller_001_reset_out_reset)                        //   input,   width = 1,             reset.reset_n
	);

	gflish_onchip_memory2_0 main_memory (
		.clk        (sys_clk_out_clk_clk),                         //   input,   width = 1,   clk1.clk
		.reset      (rst_controller_001_reset_out_reset),          //   input,   width = 1, reset1.reset
		.reset_req  (rst_controller_001_reset_out_reset_req),      //   input,   width = 1,       .reset_req
		.address    (mm_interconnect_0_main_memory_s1_address),    //   input,  width = 15,     s1.address
		.clken      (mm_interconnect_0_main_memory_s1_clken),      //   input,   width = 1,       .clken
		.chipselect (mm_interconnect_0_main_memory_s1_chipselect), //   input,   width = 1,       .chipselect
		.write      (mm_interconnect_0_main_memory_s1_write),      //   input,   width = 1,       .write
		.readdata   (mm_interconnect_0_main_memory_s1_readdata),   //  output,  width = 32,       .readdata
		.writedata  (mm_interconnect_0_main_memory_s1_writedata),  //   input,  width = 32,       .writedata
		.byteenable (mm_interconnect_0_main_memory_s1_byteenable)  //   input,   width = 4,       .byteenable
	);

	gflish_nios2_gen2_0 nios2 (
		.clk                                 (sys_clk_out_clk_clk),                                 //   input,   width = 1,                       clk.clk
		.dummy_ci_port                       (),                                                    //  output,   width = 1, custom_instruction_master.readra
		.d_address                           (nios2_data_master_address),                           //  output,  width = 26,               data_master.address
		.d_byteenable                        (nios2_data_master_byteenable),                        //  output,   width = 4,                          .byteenable
		.d_read                              (nios2_data_master_read),                              //  output,   width = 1,                          .read
		.d_readdata                          (nios2_data_master_readdata),                          //   input,  width = 32,                          .readdata
		.d_waitrequest                       (nios2_data_master_waitrequest),                       //   input,   width = 1,                          .waitrequest
		.d_write                             (nios2_data_master_write),                             //  output,   width = 1,                          .write
		.d_writedata                         (nios2_data_master_writedata),                         //  output,  width = 32,                          .writedata
		.d_readdatavalid                     (nios2_data_master_readdatavalid),                     //   input,   width = 1,                          .readdatavalid
		.debug_mem_slave_debugaccess_to_roms (nios2_data_master_debugaccess),                       //  output,   width = 1,                          .debugaccess
		.debug_mem_slave_address             (mm_interconnect_0_nios2_debug_mem_slave_address),     //   input,   width = 9,           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_debug_mem_slave_byteenable),  //   input,   width = 4,                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_debug_mem_slave_debugaccess), //   input,   width = 1,                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_debug_mem_slave_read),        //   input,   width = 1,                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_debug_mem_slave_readdata),    //  output,  width = 32,                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_debug_mem_slave_waitrequest), //  output,   width = 1,                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_debug_mem_slave_write),       //   input,   width = 1,                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_debug_mem_slave_writedata),   //   input,  width = 32,                          .writedata
		.debug_reset_request                 (nios2_debug_reset_request_reset),                     //  output,   width = 1,       debug_reset_request.reset
		.i_address                           (nios2_instruction_master_address),                    //  output,  width = 26,        instruction_master.address
		.i_read                              (nios2_instruction_master_read),                       //  output,   width = 1,                          .read
		.i_readdata                          (nios2_instruction_master_readdata),                   //   input,  width = 32,                          .readdata
		.i_waitrequest                       (nios2_instruction_master_waitrequest),                //   input,   width = 1,                          .waitrequest
		.i_readdatavalid                     (nios2_instruction_master_readdatavalid),              //   input,   width = 1,                          .readdatavalid
		.irq                                 (nios2_irq_irq),                                       //   input,  width = 32,                       irq.irq
		.reset_n                             (~rst_controller_001_reset_out_reset),                 //   input,   width = 1,                     reset.reset_n
		.reset_req                           (rst_controller_001_reset_out_reset_req)               //   input,   width = 1,                          .reset_req
	);

	gflish_reset_in reset_in (
		.clk       (sys_clk_out_clk_clk),      //   input,  width = 1,       clk.clk
		.in_reset  (reset_reset),              //   input,  width = 1,  in_reset.reset
		.out_reset (reset_in_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

	gflish_clock_in sys_clk (
		.in_clk  (clk_clk),             //   input,  width = 1,  in_clk.clk
		.out_clk (sys_clk_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	gflish_altera_mm_interconnect_180_sbymbyi mm_interconnect_0 (
		.gfilsh_avl_csr_address                  (mm_interconnect_0_gfilsh_avl_csr_address),                  //  output,   width = 6,                    gfilsh_avl_csr.address
		.gfilsh_avl_csr_write                    (mm_interconnect_0_gfilsh_avl_csr_write),                    //  output,   width = 1,                                  .write
		.gfilsh_avl_csr_read                     (mm_interconnect_0_gfilsh_avl_csr_read),                     //  output,   width = 1,                                  .read
		.gfilsh_avl_csr_readdata                 (mm_interconnect_0_gfilsh_avl_csr_readdata),                 //   input,  width = 32,                                  .readdata
		.gfilsh_avl_csr_writedata                (mm_interconnect_0_gfilsh_avl_csr_writedata),                //  output,  width = 32,                                  .writedata
		.gfilsh_avl_csr_readdatavalid            (mm_interconnect_0_gfilsh_avl_csr_readdatavalid),            //   input,   width = 1,                                  .readdatavalid
		.gfilsh_avl_csr_waitrequest              (mm_interconnect_0_gfilsh_avl_csr_waitrequest),              //   input,   width = 1,                                  .waitrequest
		.gfilsh_avl_mem_address                  (mm_interconnect_0_gfilsh_avl_mem_address),                  //  output,  width = 23,                    gfilsh_avl_mem.address
		.gfilsh_avl_mem_write                    (mm_interconnect_0_gfilsh_avl_mem_write),                    //  output,   width = 1,                                  .write
		.gfilsh_avl_mem_read                     (mm_interconnect_0_gfilsh_avl_mem_read),                     //  output,   width = 1,                                  .read
		.gfilsh_avl_mem_readdata                 (mm_interconnect_0_gfilsh_avl_mem_readdata),                 //   input,  width = 32,                                  .readdata
		.gfilsh_avl_mem_writedata                (mm_interconnect_0_gfilsh_avl_mem_writedata),                //  output,  width = 32,                                  .writedata
		.gfilsh_avl_mem_burstcount               (mm_interconnect_0_gfilsh_avl_mem_burstcount),               //  output,   width = 7,                                  .burstcount
		.gfilsh_avl_mem_byteenable               (mm_interconnect_0_gfilsh_avl_mem_byteenable),               //  output,   width = 4,                                  .byteenable
		.gfilsh_avl_mem_readdatavalid            (mm_interconnect_0_gfilsh_avl_mem_readdatavalid),            //   input,   width = 1,                                  .readdatavalid
		.gfilsh_avl_mem_waitrequest              (mm_interconnect_0_gfilsh_avl_mem_waitrequest),              //   input,   width = 1,                                  .waitrequest
		.jtag_uart_avalon_jtag_slave_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //  output,   width = 1,       jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write       (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),       //  output,   width = 1,                                  .write
		.jtag_uart_avalon_jtag_slave_read        (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),        //  output,   width = 1,                                  .read
		.jtag_uart_avalon_jtag_slave_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //   input,  width = 32,                                  .readdata
		.jtag_uart_avalon_jtag_slave_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //  output,  width = 32,                                  .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //   input,   width = 1,                                  .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  //  output,   width = 1,                                  .chipselect
		.main_memory_s1_address                  (mm_interconnect_0_main_memory_s1_address),                  //  output,  width = 15,                    main_memory_s1.address
		.main_memory_s1_write                    (mm_interconnect_0_main_memory_s1_write),                    //  output,   width = 1,                                  .write
		.main_memory_s1_readdata                 (mm_interconnect_0_main_memory_s1_readdata),                 //   input,  width = 32,                                  .readdata
		.main_memory_s1_writedata                (mm_interconnect_0_main_memory_s1_writedata),                //  output,  width = 32,                                  .writedata
		.main_memory_s1_byteenable               (mm_interconnect_0_main_memory_s1_byteenable),               //  output,   width = 4,                                  .byteenable
		.main_memory_s1_chipselect               (mm_interconnect_0_main_memory_s1_chipselect),               //  output,   width = 1,                                  .chipselect
		.main_memory_s1_clken                    (mm_interconnect_0_main_memory_s1_clken),                    //  output,   width = 1,                                  .clken
		.nios2_data_master_address               (nios2_data_master_address),                                 //   input,  width = 26,                 nios2_data_master.address
		.nios2_data_master_waitrequest           (nios2_data_master_waitrequest),                             //  output,   width = 1,                                  .waitrequest
		.nios2_data_master_byteenable            (nios2_data_master_byteenable),                              //   input,   width = 4,                                  .byteenable
		.nios2_data_master_read                  (nios2_data_master_read),                                    //   input,   width = 1,                                  .read
		.nios2_data_master_readdata              (nios2_data_master_readdata),                                //  output,  width = 32,                                  .readdata
		.nios2_data_master_readdatavalid         (nios2_data_master_readdatavalid),                           //  output,   width = 1,                                  .readdatavalid
		.nios2_data_master_write                 (nios2_data_master_write),                                   //   input,   width = 1,                                  .write
		.nios2_data_master_writedata             (nios2_data_master_writedata),                               //   input,  width = 32,                                  .writedata
		.nios2_data_master_debugaccess           (nios2_data_master_debugaccess),                             //   input,   width = 1,                                  .debugaccess
		.nios2_debug_mem_slave_address           (mm_interconnect_0_nios2_debug_mem_slave_address),           //  output,   width = 9,             nios2_debug_mem_slave.address
		.nios2_debug_mem_slave_write             (mm_interconnect_0_nios2_debug_mem_slave_write),             //  output,   width = 1,                                  .write
		.nios2_debug_mem_slave_read              (mm_interconnect_0_nios2_debug_mem_slave_read),              //  output,   width = 1,                                  .read
		.nios2_debug_mem_slave_readdata          (mm_interconnect_0_nios2_debug_mem_slave_readdata),          //   input,  width = 32,                                  .readdata
		.nios2_debug_mem_slave_writedata         (mm_interconnect_0_nios2_debug_mem_slave_writedata),         //  output,  width = 32,                                  .writedata
		.nios2_debug_mem_slave_byteenable        (mm_interconnect_0_nios2_debug_mem_slave_byteenable),        //  output,   width = 4,                                  .byteenable
		.nios2_debug_mem_slave_waitrequest       (mm_interconnect_0_nios2_debug_mem_slave_waitrequest),       //   input,   width = 1,                                  .waitrequest
		.nios2_debug_mem_slave_debugaccess       (mm_interconnect_0_nios2_debug_mem_slave_debugaccess),       //  output,   width = 1,                                  .debugaccess
		.nios2_instruction_master_address        (nios2_instruction_master_address),                          //   input,  width = 26,          nios2_instruction_master.address
		.nios2_instruction_master_waitrequest    (nios2_instruction_master_waitrequest),                      //  output,   width = 1,                                  .waitrequest
		.nios2_instruction_master_read           (nios2_instruction_master_read),                             //   input,   width = 1,                                  .read
		.nios2_instruction_master_readdata       (nios2_instruction_master_readdata),                         //  output,  width = 32,                                  .readdata
		.nios2_instruction_master_readdatavalid  (nios2_instruction_master_readdatavalid),                    //  output,   width = 1,                                  .readdatavalid
		.nios2_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                        //   input,   width = 1, nios2_reset_reset_bridge_in_reset.reset
		.sys_clk_out_clk_clk                     (sys_clk_out_clk_clk)                                        //   input,   width = 1,                   sys_clk_out_clk.clk
	);

	gflish_altera_irq_mapper_180_grgmmai irq_mapper (
		.clk           (sys_clk_out_clk_clk),                //   input,   width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,   width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),           //   input,   width = 1, receiver0.irq
		.sender_irq    (nios2_irq_irq)                       //  output,  width = 32,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (nios2_debug_reset_request_reset), //   input,  width = 1, reset_in0.reset
		.reset_in1      (reset_in_out_reset_reset),        //   input,  width = 1, reset_in1.reset
		.clk            (),                                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset),  //  output,  width = 1, reset_out.reset
		.reset_req      (),                                // (terminated),                       
		.reset_req_in0  (1'b0),                            // (terminated),                       
		.reset_req_in1  (1'b0),                            // (terminated),                       
		.reset_in2      (1'b0),                            // (terminated),                       
		.reset_req_in2  (1'b0),                            // (terminated),                       
		.reset_in3      (1'b0),                            // (terminated),                       
		.reset_req_in3  (1'b0),                            // (terminated),                       
		.reset_in4      (1'b0),                            // (terminated),                       
		.reset_req_in4  (1'b0),                            // (terminated),                       
		.reset_in5      (1'b0),                            // (terminated),                       
		.reset_req_in5  (1'b0),                            // (terminated),                       
		.reset_in6      (1'b0),                            // (terminated),                       
		.reset_req_in6  (1'b0),                            // (terminated),                       
		.reset_in7      (1'b0),                            // (terminated),                       
		.reset_req_in7  (1'b0),                            // (terminated),                       
		.reset_in8      (1'b0),                            // (terminated),                       
		.reset_req_in8  (1'b0),                            // (terminated),                       
		.reset_in9      (1'b0),                            // (terminated),                       
		.reset_req_in9  (1'b0),                            // (terminated),                       
		.reset_in10     (1'b0),                            // (terminated),                       
		.reset_req_in10 (1'b0),                            // (terminated),                       
		.reset_in11     (1'b0),                            // (terminated),                       
		.reset_req_in11 (1'b0),                            // (terminated),                       
		.reset_in12     (1'b0),                            // (terminated),                       
		.reset_req_in12 (1'b0),                            // (terminated),                       
		.reset_in13     (1'b0),                            // (terminated),                       
		.reset_req_in13 (1'b0),                            // (terminated),                       
		.reset_in14     (1'b0),                            // (terminated),                       
		.reset_req_in14 (1'b0),                            // (terminated),                       
		.reset_in15     (1'b0),                            // (terminated),                       
		.reset_req_in15 (1'b0)                             // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (nios2_debug_reset_request_reset),        //   input,  width = 1, reset_in0.reset
		.reset_in1      (reset_in_out_reset_reset),               //   input,  width = 1, reset_in1.reset
		.clk            (sys_clk_out_clk_clk),                    //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_001_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                                   // (terminated),                       
		.reset_req_in1  (1'b0),                                   // (terminated),                       
		.reset_in2      (1'b0),                                   // (terminated),                       
		.reset_req_in2  (1'b0),                                   // (terminated),                       
		.reset_in3      (1'b0),                                   // (terminated),                       
		.reset_req_in3  (1'b0),                                   // (terminated),                       
		.reset_in4      (1'b0),                                   // (terminated),                       
		.reset_req_in4  (1'b0),                                   // (terminated),                       
		.reset_in5      (1'b0),                                   // (terminated),                       
		.reset_req_in5  (1'b0),                                   // (terminated),                       
		.reset_in6      (1'b0),                                   // (terminated),                       
		.reset_req_in6  (1'b0),                                   // (terminated),                       
		.reset_in7      (1'b0),                                   // (terminated),                       
		.reset_req_in7  (1'b0),                                   // (terminated),                       
		.reset_in8      (1'b0),                                   // (terminated),                       
		.reset_req_in8  (1'b0),                                   // (terminated),                       
		.reset_in9      (1'b0),                                   // (terminated),                       
		.reset_req_in9  (1'b0),                                   // (terminated),                       
		.reset_in10     (1'b0),                                   // (terminated),                       
		.reset_req_in10 (1'b0),                                   // (terminated),                       
		.reset_in11     (1'b0),                                   // (terminated),                       
		.reset_req_in11 (1'b0),                                   // (terminated),                       
		.reset_in12     (1'b0),                                   // (terminated),                       
		.reset_req_in12 (1'b0),                                   // (terminated),                       
		.reset_in13     (1'b0),                                   // (terminated),                       
		.reset_req_in13 (1'b0),                                   // (terminated),                       
		.reset_in14     (1'b0),                                   // (terminated),                       
		.reset_req_in14 (1'b0),                                   // (terminated),                       
		.reset_in15     (1'b0),                                   // (terminated),                       
		.reset_req_in15 (1'b0)                                    // (terminated),                       
	);

endmodule
