
State Machine - gfilsh|intel_generic_serial_flash_interface_top_0|csr_controller|state
Name state.ST_WAIT_RSP state.ST_SEND_DATA_1 state.ST_SEND_DATA_0 state.ST_SEND_HEADER state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 
state.ST_WAIT_RSP 1 0 0 0 1 
state.ST_SEND_HEADER 0 0 0 1 1 
state.ST_SEND_DATA_0 0 0 1 0 1 
state.ST_SEND_DATA_1 0 1 0 0 1 

State Machine - gfilsh|intel_generic_serial_flash_interface_top_0|xip_controller|current_state
Name current_state.STATE_READ_DATA current_state.STATE_READ_NVCR_RSP current_state.STATE_READ_NVCR_CMD current_state.STATE_COMPLETE current_state.STATE_POLL_RSP current_state.STATE_POLL_CMD current_state.STATE_WR_DATA current_state.STATE_WR_CMD current_state.STATE_WRENABLE_RSP current_state.STATE_WRENABLE_CMD current_state.STATE_STATUS_RSP current_state.STATE_STATUS_CMD current_state.STATE_READ_CMD current_state.STATE_IDLE 
current_state.STATE_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
current_state.STATE_READ_CMD 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
current_state.STATE_STATUS_CMD 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
current_state.STATE_STATUS_RSP 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
current_state.STATE_WRENABLE_CMD 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
current_state.STATE_WRENABLE_RSP 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
current_state.STATE_WR_CMD 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
current_state.STATE_WR_DATA 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
current_state.STATE_POLL_CMD 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
current_state.STATE_POLL_RSP 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
current_state.STATE_COMPLETE 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_NVCR_CMD 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_NVCR_RSP 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_DATA 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - gfilsh|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state
Name state.ST_COMPLETE state.ST_SEND_DUMMY_RSP state.ST_WAIT_BUFFER state.ST_WAIT_RSP state.ST_SEND_DATA state.ST_SEND_ADDR state.ST_SEND_OPCODE state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 0 0 0 
state.ST_SEND_ADDR 0 0 0 0 0 1 0 1 
state.ST_WAIT_BUFFER 0 0 1 0 0 0 0 1 
state.ST_SEND_DATA 0 0 0 0 1 0 0 1 
state.ST_SEND_OPCODE 0 0 0 0 0 0 1 1 
state.ST_WAIT_RSP 0 0 0 1 0 0 0 1 
state.ST_SEND_DUMMY_RSP 0 1 0 0 0 0 0 1 
state.ST_COMPLETE 1 0 0 0 0 0 0 1 

State Machine - gfilsh|intel_generic_serial_flash_interface_top_0|qspi_inf_inst|state
Name state.ST_DEASSERT_CS_DLY state.ST_DEASSERT_CS state.ST_STOP_CLK state.ST_RECEIVE state.ST_DUMMY_CYCLES state.ST_SEND state.ST_ASSERT_CS state.ST_START_CLK state.ST_ASSERT_CS_DLY state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 0 0 0 0 0 
state.ST_DUMMY_CYCLES 0 0 0 0 1 0 0 0 0 1 
state.ST_START_CLK 0 0 0 0 0 0 0 1 0 1 
state.ST_ASSERT_CS_DLY 0 0 0 0 0 0 0 0 1 1 
state.ST_ASSERT_CS 0 0 0 0 0 0 1 0 0 1 
state.ST_SEND 0 0 0 0 0 1 0 0 0 1 
state.ST_RECEIVE 0 0 0 1 0 0 0 0 0 1 
state.ST_STOP_CLK 0 0 1 0 0 0 0 0 0 1 
state.ST_DEASSERT_CS 0 1 0 0 0 0 0 0 0 1 
state.ST_DEASSERT_CS_DLY 1 0 0 0 0 0 0 0 0 1 

State Machine - nios2|nios2_gen2_0|cpu|the_gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_nios2_oci|the_gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_wrapper|the_gflish_nios2_gen2_0_altera_nios2_gen2_unit_180_cjamevi_debug_slave_tck|DRsize
Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 
DRsize.000 0 0 0 0 0 0 
DRsize.001 0 0 0 0 1 1 
DRsize.010 0 0 0 1 0 1 
DRsize.011 0 0 1 0 0 1 
DRsize.100 0 1 0 0 0 1 
DRsize.101 1 0 0 0 0 1 

State Machine - Summary
