module gflish_nios2_gen2_0 (
		input  wire        clk,                                 //                       clk.clk
		output wire        dummy_ci_port,                       // custom_instruction_master.readra
		output wire [25:0] d_address,                           //               data_master.address
		output wire [3:0]  d_byteenable,                        //                          .byteenable
		output wire        d_read,                              //                          .read
		input  wire [31:0] d_readdata,                          //                          .readdata
		input  wire        d_waitrequest,                       //                          .waitrequest
		output wire        d_write,                             //                          .write
		output wire [31:0] d_writedata,                         //                          .writedata
		input  wire        d_readdatavalid,                     //                          .readdatavalid
		output wire        debug_mem_slave_debugaccess_to_roms, //                          .debugaccess
		input  wire [8:0]  debug_mem_slave_address,             //           debug_mem_slave.address
		input  wire [3:0]  debug_mem_slave_byteenable,          //                          .byteenable
		input  wire        debug_mem_slave_debugaccess,         //                          .debugaccess
		input  wire        debug_mem_slave_read,                //                          .read
		output wire [31:0] debug_mem_slave_readdata,            //                          .readdata
		output wire        debug_mem_slave_waitrequest,         //                          .waitrequest
		input  wire        debug_mem_slave_write,               //                          .write
		input  wire [31:0] debug_mem_slave_writedata,           //                          .writedata
		output wire        debug_reset_request,                 //       debug_reset_request.reset
		output wire [25:0] i_address,                           //        instruction_master.address
		output wire        i_read,                              //                          .read
		input  wire [31:0] i_readdata,                          //                          .readdata
		input  wire        i_waitrequest,                       //                          .waitrequest
		input  wire        i_readdatavalid,                     //                          .readdatavalid
		input  wire [31:0] irq,                                 //                       irq.irq
		input  wire        reset_n,                             //                     reset.reset_n
		input  wire        reset_req                            //                          .reset_req
	);
endmodule

