// gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_top_180_h2f7kua.v

// This file was auto-generated from intel_generic_serial_flash_interface_top_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.0 219

`timescale 1 ps / 1 ps
module gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_top_180_h2f7kua #(
		parameter DEVICE_FAMILY = "Arria 10",
		parameter CHIP_SELS     = 1
	) (
		input  wire [5:0]  avl_csr_address,       // avl_csr.address
		input  wire        avl_csr_read,          //        .read
		output wire [31:0] avl_csr_readdata,      //        .readdata
		input  wire        avl_csr_write,         //        .write
		input  wire [31:0] avl_csr_writedata,     //        .writedata
		output wire        avl_csr_waitrequest,   //        .waitrequest
		output wire        avl_csr_readdatavalid, //        .readdatavalid
		input  wire        avl_mem_write,         // avl_mem.write
		input  wire [6:0]  avl_mem_burstcount,    //        .burstcount
		output wire        avl_mem_waitrequest,   //        .waitrequest
		input  wire        avl_mem_read,          //        .read
		input  wire [22:0] avl_mem_address,       //        .address
		input  wire [31:0] avl_mem_writedata,     //        .writedata
		output wire [31:0] avl_mem_readdata,      //        .readdata
		output wire        avl_mem_readdatavalid, //        .readdatavalid
		input  wire [3:0]  avl_mem_byteenable,    //        .byteenable
		input  wire        clk_clk,               //     clk.clk
		input  wire        reset_reset            //   reset.reset
	);

	wire         csr_controller_cmd_pck_valid;                                // csr_controller:cmd_valid -> multiplexer:sink1_valid
	wire  [31:0] csr_controller_cmd_pck_data;                                 // csr_controller:cmd_data -> multiplexer:sink1_data
	wire         csr_controller_cmd_pck_ready;                                // multiplexer:sink1_ready -> csr_controller:cmd_ready
	wire   [1:0] csr_controller_cmd_pck_channel;                              // csr_controller:cmd_channel -> multiplexer:sink1_channel
	wire         csr_controller_cmd_pck_startofpacket;                        // csr_controller:cmd_sop -> multiplexer:sink1_startofpacket
	wire         csr_controller_cmd_pck_endofpacket;                          // csr_controller:cmd_eop -> multiplexer:sink1_endofpacket
	wire         xip_controller_cmd_pck_valid;                                // xip_controller:cmd_valid -> multiplexer:sink0_valid
	wire  [31:0] xip_controller_cmd_pck_data;                                 // xip_controller:cmd_data -> multiplexer:sink0_data
	wire         xip_controller_cmd_pck_ready;                                // multiplexer:sink0_ready -> xip_controller:cmd_ready
	wire   [1:0] xip_controller_cmd_pck_channel;                              // xip_controller:cmd_channel -> multiplexer:sink0_channel
	wire         xip_controller_cmd_pck_startofpacket;                        // xip_controller:cmd_sop -> multiplexer:sink0_startofpacket
	wire         xip_controller_cmd_pck_endofpacket;                          // xip_controller:cmd_eop -> multiplexer:sink0_endofpacket
	wire         merlin_demultiplexer_0_src1_valid;                           // merlin_demultiplexer_0:src1_valid -> csr_controller:rsp_valid
	wire  [31:0] merlin_demultiplexer_0_src1_data;                            // merlin_demultiplexer_0:src1_data -> csr_controller:rsp_data
	wire         merlin_demultiplexer_0_src1_ready;                           // csr_controller:rsp_ready -> merlin_demultiplexer_0:src1_ready
	wire   [1:0] merlin_demultiplexer_0_src1_channel;                         // merlin_demultiplexer_0:src1_channel -> csr_controller:rsp_channel
	wire         merlin_demultiplexer_0_src1_startofpacket;                   // merlin_demultiplexer_0:src1_startofpacket -> csr_controller:rsp_sop
	wire         merlin_demultiplexer_0_src1_endofpacket;                     // merlin_demultiplexer_0:src1_endofpacket -> csr_controller:rsp_eop
	wire         merlin_demultiplexer_0_src0_valid;                           // merlin_demultiplexer_0:src0_valid -> xip_controller:rsp_valid
	wire  [31:0] merlin_demultiplexer_0_src0_data;                            // merlin_demultiplexer_0:src0_data -> xip_controller:rsp_data
	wire         merlin_demultiplexer_0_src0_ready;                           // xip_controller:rsp_ready -> merlin_demultiplexer_0:src0_ready
	wire   [1:0] merlin_demultiplexer_0_src0_channel;                         // merlin_demultiplexer_0:src0_channel -> xip_controller:rsp_channel
	wire         merlin_demultiplexer_0_src0_startofpacket;                   // merlin_demultiplexer_0:src0_startofpacket -> xip_controller:rsp_sop
	wire         merlin_demultiplexer_0_src0_endofpacket;                     // merlin_demultiplexer_0:src0_endofpacket -> xip_controller:rsp_eop
	wire  [31:0] xip_addr_adaption_gen_qspi_mem_readdata;                     // xip_controller:mem_rddata -> xip_addr_adaption:gen_qspi_mem_rddata
	wire         xip_addr_adaption_gen_qspi_mem_waitrequest;                  // xip_controller:mem_waitrequest -> xip_addr_adaption:gen_qspi_mem_waitrequest
	wire  [31:0] xip_addr_adaption_gen_qspi_mem_address;                      // xip_addr_adaption:gen_qspi_mem_addr -> xip_controller:mem_addr
	wire         xip_addr_adaption_gen_qspi_mem_read;                         // xip_addr_adaption:gen_qspi_mem_read -> xip_controller:mem_rd
	wire   [3:0] xip_addr_adaption_gen_qspi_mem_byteenable;                   // xip_addr_adaption:gen_qspi_mem_byteenable -> xip_controller:mem_byteenable
	wire         xip_addr_adaption_gen_qspi_mem_readdatavalid;                // xip_controller:mem_rddatavalid -> xip_addr_adaption:gen_qspi_mem_rddata_valid
	wire         xip_addr_adaption_gen_qspi_mem_write;                        // xip_addr_adaption:gen_qspi_mem_write -> xip_controller:mem_wr
	wire  [31:0] xip_addr_adaption_gen_qspi_mem_writedata;                    // xip_addr_adaption:gen_qspi_mem_wrdata -> xip_controller:mem_wrdata
	wire   [6:0] xip_addr_adaption_gen_qspi_mem_burstcount;                   // xip_addr_adaption:gen_qspi_mem_burstcount -> xip_controller:mem_burstcount
	wire   [3:0] csr_controller_chip_select_chip_select;                      // csr_controller:chip_select -> xip_controller:chip_select
	wire   [3:0] serial_flash_inf_cmd_gen_inst_addr_num_lines_addr_num_lines; // serial_flash_inf_cmd_gen_inst:addr_num_lines -> qspi_inf_inst:addr_num_lines
	wire   [3:0] serial_flash_inf_cmd_gen_inst_data_num_lines_data_num_lines; // serial_flash_inf_cmd_gen_inst:data_num_lines -> qspi_inf_inst:data_num_lines
	wire   [3:0] serial_flash_inf_cmd_gen_inst_op_num_lines_op_num_lines;     // serial_flash_inf_cmd_gen_inst:op_num_lines -> qspi_inf_inst:op_num_lines
	wire  [31:0] csr_controller_addr_bytes_csr_addr_bytes_csr;                // csr_controller:addr_bytes_csr -> serial_flash_inf_cmd_gen_inst:addr_bytes_csr
	wire  [31:0] xip_controller_addr_bytes_xip_addr_bytes_xip;                // xip_controller:addr_bytes_xip -> serial_flash_inf_cmd_gen_inst:addr_bytes_xip
	wire   [1:0] csr_controller_op_type_op_type;                              // csr_controller:op_type -> serial_flash_inf_cmd_gen_inst:op_type
	wire   [1:0] csr_controller_wr_addr_type_wr_addr_type;                    // csr_controller:wr_addr_type -> serial_flash_inf_cmd_gen_inst:wr_addr_type
	wire   [1:0] csr_controller_wr_data_type_wr_data_type;                    // csr_controller:wr_data_type -> serial_flash_inf_cmd_gen_inst:wr_data_type
	wire   [1:0] csr_controller_rd_addr_type_rd_addr_type;                    // csr_controller:rd_addr_type -> serial_flash_inf_cmd_gen_inst:rd_addr_type
	wire   [1:0] csr_controller_rd_data_type_rd_data_type;                    // csr_controller:rd_data_type -> serial_flash_inf_cmd_gen_inst:rd_data_type
	wire   [7:0] csr_controller_wr_en_opcode_wr_en_opcode;                    // csr_controller:wr_en_opcode -> xip_controller:wr_en_opcode
	wire   [7:0] csr_controller_polling_opcode_polling_opcode;                // csr_controller:polling_opcode -> xip_controller:polling_opcode
	wire   [2:0] csr_controller_polling_bit_polling_bit;                      // csr_controller:polling_bit -> xip_controller:polling_bit
	wire   [7:0] csr_controller_wr_opcode_wr_opcode;                          // csr_controller:wr_opcode -> xip_controller:wr_opcode
	wire   [7:0] csr_controller_rd_opcode_rd_opcode;                          // csr_controller:rd_opcode -> xip_controller:rd_opcode
	wire   [4:0] csr_controller_rd_dummy_cycles_rd_dummy_cycles;              // csr_controller:rd_dummy_cycles -> xip_controller:rd_dummy_cycles
	wire         csr_controller_is_4bytes_addr_xip_is_4bytes_addr_xip;        // csr_controller:is_4bytes_addr_xip -> xip_controller:is_4bytes_addr_xip
	wire   [4:0] csr_controller_baud_rate_divisor_baud_rate_divisor;          // csr_controller:baud_rate_divisor -> qspi_inf_inst:baud_rate_divisor
	wire   [7:0] csr_controller_cs_delay_setting_cs_delay_setting;            // csr_controller:cs_delay_setting -> qspi_inf_inst:cs_delay_setting
	wire   [3:0] csr_controller_read_capture_delay_read_capture_delay;        // csr_controller:read_capture_delay -> qspi_inf_inst:read_capture_delay
	wire   [1:0] xip_controller_xip_trans_type_xip_trans_type;                // xip_controller:xip_trans_type -> serial_flash_inf_cmd_gen_inst:xip_trans_type
	wire         serial_flash_inf_cmd_gen_inst_out_rsp_pck_valid;             // serial_flash_inf_cmd_gen_inst:out_rsp_valid -> merlin_demultiplexer_0:sink_valid
	wire  [31:0] serial_flash_inf_cmd_gen_inst_out_rsp_pck_data;              // serial_flash_inf_cmd_gen_inst:out_rsp_data -> merlin_demultiplexer_0:sink_data
	wire         serial_flash_inf_cmd_gen_inst_out_rsp_pck_ready;             // merlin_demultiplexer_0:sink_ready -> serial_flash_inf_cmd_gen_inst:out_rsp_ready
	wire   [1:0] serial_flash_inf_cmd_gen_inst_out_rsp_pck_channel;           // serial_flash_inf_cmd_gen_inst:out_rsp_channel -> merlin_demultiplexer_0:sink_channel
	wire         serial_flash_inf_cmd_gen_inst_out_rsp_pck_startofpacket;     // serial_flash_inf_cmd_gen_inst:out_rsp_sop -> merlin_demultiplexer_0:sink_startofpacket
	wire         serial_flash_inf_cmd_gen_inst_out_rsp_pck_endofpacket;       // serial_flash_inf_cmd_gen_inst:out_rsp_eop -> merlin_demultiplexer_0:sink_endofpacket
	wire         qspi_inf_inst_out_rsp_pck_valid;                             // qspi_inf_inst:out_rsp_valid -> serial_flash_inf_cmd_gen_inst:in_rsp_valid
	wire   [7:0] qspi_inf_inst_out_rsp_pck_data;                              // qspi_inf_inst:out_rsp_data -> serial_flash_inf_cmd_gen_inst:in_rsp_data
	wire         qspi_inf_inst_out_rsp_pck_ready;                             // serial_flash_inf_cmd_gen_inst:in_rsp_ready -> qspi_inf_inst:out_rsp_ready
	wire   [4:0] serial_flash_inf_cmd_gen_inst_dummy_cycles_dummy_cycles;     // serial_flash_inf_cmd_gen_inst:dummy_cycles -> qspi_inf_inst:dummy_cycles
	wire   [3:0] serial_flash_inf_cmd_gen_inst_chip_select_chip_select;       // serial_flash_inf_cmd_gen_inst:chip_select -> qspi_inf_inst:chip_select
	wire         serial_flash_inf_cmd_gen_inst_require_rdata_require_rdata;   // serial_flash_inf_cmd_gen_inst:require_rdata -> qspi_inf_inst:require_rdata
	wire         csr_controller_qspi_interface_en_qspi_interface_en;          // csr_controller:qspi_interface_en -> qspi_inf_inst:qspi_interface_en
	wire         serial_flash_inf_cmd_gen_inst_out_cmd_pck_valid;             // serial_flash_inf_cmd_gen_inst:out_cmd_valid -> qspi_inf_inst:in_cmd_valid
	wire   [7:0] serial_flash_inf_cmd_gen_inst_out_cmd_pck_data;              // serial_flash_inf_cmd_gen_inst:out_cmd_data -> qspi_inf_inst:in_cmd_data
	wire         serial_flash_inf_cmd_gen_inst_out_cmd_pck_ready;             // qspi_inf_inst:in_cmd_ready -> serial_flash_inf_cmd_gen_inst:out_cmd_ready
	wire   [8:0] serial_flash_inf_cmd_gen_inst_out_cmd_pck_channel;           // serial_flash_inf_cmd_gen_inst:out_cmd_channel -> qspi_inf_inst:in_cmd_channel
	wire         serial_flash_inf_cmd_gen_inst_out_cmd_pck_startofpacket;     // serial_flash_inf_cmd_gen_inst:out_cmd_sop -> qspi_inf_inst:in_cmd_sop
	wire         serial_flash_inf_cmd_gen_inst_out_cmd_pck_endofpacket;       // serial_flash_inf_cmd_gen_inst:out_cmd_eop -> qspi_inf_inst:in_cmd_eop
	wire         multiplexer_src_valid;                                       // multiplexer:src_valid -> serial_flash_inf_cmd_gen_inst:in_cmd_valid
	wire  [31:0] multiplexer_src_data;                                        // multiplexer:src_data -> serial_flash_inf_cmd_gen_inst:in_cmd_data
	wire         multiplexer_src_ready;                                       // serial_flash_inf_cmd_gen_inst:in_cmd_ready -> multiplexer:src_ready
	wire   [1:0] multiplexer_src_channel;                                     // multiplexer:src_channel -> serial_flash_inf_cmd_gen_inst:in_cmd_channel
	wire         multiplexer_src_startofpacket;                               // multiplexer:src_startofpacket -> serial_flash_inf_cmd_gen_inst:in_cmd_sop
	wire         multiplexer_src_endofpacket;                                 // multiplexer:src_endofpacket -> serial_flash_inf_cmd_gen_inst:in_cmd_eop
	wire         rst_controller_reset_out_reset;                              // rst_controller:reset_out -> [csr_controller:reset, merlin_demultiplexer_0:reset, multiplexer:reset, qspi_inf_inst:reset, serial_flash_inf_cmd_gen_inst:reset, xip_addr_adaption:reset, xip_controller:reset]

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (DEVICE_FAMILY != "Arria 10")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					device_family_check ( .error(1'b1) );
		end
		if (CHIP_SELS != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					chip_sels_check ( .error(1'b1) );
		end
	endgenerate

	intel_generic_serial_flash_interface_csr #(
		.ADD_W               (6),
		.CHIP_SELECT_BYPASS  (0),
		.DEFAULT_VALUE_REG_0 (32'b00000000000000000000000000000001),
		.DEFAULT_VALUE_REG_1 (32'b00000000000000000000000000010000),
		.DEFAULT_VALUE_REG_2 (32'b00000000000000000000000000000000),
		.DEFAULT_VALUE_REG_3 (32'b00000000000000000000000000000000),
		.DEFAULT_VALUE_REG_4 (32'b00000000000000000000000000000000),
		.DEFAULT_VALUE_REG_5 (32'b00000000000000000000000000000011),
		.DEFAULT_VALUE_REG_6 (32'b00000000000000000111000000000010),
		.DEFAULT_VALUE_REG_7 (32'b00000000000000000001100000000101)
	) csr_controller (
		.csr_addr           (avl_csr_address),                                      //   input,   width = 6,                csr.address
		.csr_rd             (avl_csr_read),                                         //   input,   width = 1,                   .read
		.csr_rddata         (avl_csr_readdata),                                     //  output,  width = 32,                   .readdata
		.csr_wr             (avl_csr_write),                                        //   input,   width = 1,                   .write
		.csr_wrdata         (avl_csr_writedata),                                    //   input,  width = 32,                   .writedata
		.csr_waitrequest    (avl_csr_waitrequest),                                  //  output,   width = 1,                   .waitrequest
		.csr_rddatavalid    (avl_csr_readdatavalid),                                //  output,   width = 1,                   .readdatavalid
		.clk                (clk_clk),                                              //   input,   width = 1,                clk.clk
		.reset              (rst_controller_reset_out_reset),                       //   input,   width = 1,              reset.reset
		.cmd_channel        (csr_controller_cmd_pck_channel),                       //  output,   width = 2,            cmd_pck.channel
		.cmd_eop            (csr_controller_cmd_pck_endofpacket),                   //  output,   width = 1,                   .endofpacket
		.cmd_ready          (csr_controller_cmd_pck_ready),                         //   input,   width = 1,                   .ready
		.cmd_sop            (csr_controller_cmd_pck_startofpacket),                 //  output,   width = 1,                   .startofpacket
		.cmd_data           (csr_controller_cmd_pck_data),                          //  output,  width = 32,                   .data
		.cmd_valid          (csr_controller_cmd_pck_valid),                         //  output,   width = 1,                   .valid
		.rsp_channel        (merlin_demultiplexer_0_src1_channel),                  //   input,   width = 2,            rsp_pck.channel
		.rsp_data           (merlin_demultiplexer_0_src1_data),                     //   input,  width = 32,                   .data
		.rsp_eop            (merlin_demultiplexer_0_src1_endofpacket),              //   input,   width = 1,                   .endofpacket
		.rsp_ready          (merlin_demultiplexer_0_src1_ready),                    //  output,   width = 1,                   .ready
		.rsp_sop            (merlin_demultiplexer_0_src1_startofpacket),            //   input,   width = 1,                   .startofpacket
		.rsp_valid          (merlin_demultiplexer_0_src1_valid),                    //   input,   width = 1,                   .valid
		.addr_bytes_csr     (csr_controller_addr_bytes_csr_addr_bytes_csr),         //  output,  width = 32,     addr_bytes_csr.addr_bytes_csr
		.qspi_interface_en  (csr_controller_qspi_interface_en_qspi_interface_en),   //  output,   width = 1,  qspi_interface_en.qspi_interface_en
		.op_type            (csr_controller_op_type_op_type),                       //  output,   width = 2,            op_type.op_type
		.wr_addr_type       (csr_controller_wr_addr_type_wr_addr_type),             //  output,   width = 2,       wr_addr_type.wr_addr_type
		.wr_data_type       (csr_controller_wr_data_type_wr_data_type),             //  output,   width = 2,       wr_data_type.wr_data_type
		.rd_addr_type       (csr_controller_rd_addr_type_rd_addr_type),             //  output,   width = 2,       rd_addr_type.rd_addr_type
		.rd_data_type       (csr_controller_rd_data_type_rd_data_type),             //  output,   width = 2,       rd_data_type.rd_data_type
		.wr_en_opcode       (csr_controller_wr_en_opcode_wr_en_opcode),             //  output,   width = 8,       wr_en_opcode.wr_en_opcode
		.polling_opcode     (csr_controller_polling_opcode_polling_opcode),         //  output,   width = 8,     polling_opcode.polling_opcode
		.polling_bit        (csr_controller_polling_bit_polling_bit),               //  output,   width = 3,        polling_bit.polling_bit
		.wr_opcode          (csr_controller_wr_opcode_wr_opcode),                   //  output,   width = 8,          wr_opcode.wr_opcode
		.rd_opcode          (csr_controller_rd_opcode_rd_opcode),                   //  output,   width = 8,          rd_opcode.rd_opcode
		.rd_dummy_cycles    (csr_controller_rd_dummy_cycles_rd_dummy_cycles),       //  output,   width = 5,    rd_dummy_cycles.rd_dummy_cycles
		.is_4bytes_addr_xip (csr_controller_is_4bytes_addr_xip_is_4bytes_addr_xip), //  output,   width = 1, is_4bytes_addr_xip.is_4bytes_addr_xip
		.baud_rate_divisor  (csr_controller_baud_rate_divisor_baud_rate_divisor),   //  output,   width = 5,  baud_rate_divisor.baud_rate_divisor
		.cs_delay_setting   (csr_controller_cs_delay_setting_cs_delay_setting),     //  output,   width = 8,   cs_delay_setting.cs_delay_setting
		.read_capture_delay (csr_controller_read_capture_delay_read_capture_delay), //  output,   width = 4, read_capture_delay.read_capture_delay
		.chip_select        (csr_controller_chip_select_chip_select),               //  output,   width = 4,        chip_select.chip_select
		.in_chip_select     (4'b0000)                                               // (terminated),                                 
	);

	gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_xip_180_tsjvvby #(
		.ADDR_WIDTH (32)
	) xip_controller (
		.clk                (clk_clk),                                              //   input,   width = 1,                clk.clk
		.reset              (rst_controller_reset_out_reset),                       //   input,   width = 1,              reset.reset
		.mem_addr           (xip_addr_adaption_gen_qspi_mem_address),               //   input,  width = 32,                mem.address
		.mem_rd             (xip_addr_adaption_gen_qspi_mem_read),                  //   input,   width = 1,                   .read
		.mem_rddata         (xip_addr_adaption_gen_qspi_mem_readdata),              //  output,  width = 32,                   .readdata
		.mem_wr             (xip_addr_adaption_gen_qspi_mem_write),                 //   input,   width = 1,                   .write
		.mem_wrdata         (xip_addr_adaption_gen_qspi_mem_writedata),             //   input,  width = 32,                   .writedata
		.mem_byteenable     (xip_addr_adaption_gen_qspi_mem_byteenable),            //   input,   width = 4,                   .byteenable
		.mem_burstcount     (xip_addr_adaption_gen_qspi_mem_burstcount),            //   input,   width = 7,                   .burstcount
		.mem_waitrequest    (xip_addr_adaption_gen_qspi_mem_waitrequest),           //  output,   width = 1,                   .waitrequest
		.mem_rddatavalid    (xip_addr_adaption_gen_qspi_mem_readdatavalid),         //  output,   width = 1,                   .readdatavalid
		.addr_bytes_xip     (xip_controller_addr_bytes_xip_addr_bytes_xip),         //  output,  width = 32,     addr_bytes_xip.addr_bytes_xip
		.cmd_channel        (xip_controller_cmd_pck_channel),                       //  output,   width = 2,            cmd_pck.channel
		.cmd_eop            (xip_controller_cmd_pck_endofpacket),                   //  output,   width = 1,                   .endofpacket
		.cmd_ready          (xip_controller_cmd_pck_ready),                         //   input,   width = 1,                   .ready
		.cmd_sop            (xip_controller_cmd_pck_startofpacket),                 //  output,   width = 1,                   .startofpacket
		.cmd_data           (xip_controller_cmd_pck_data),                          //  output,  width = 32,                   .data
		.cmd_valid          (xip_controller_cmd_pck_valid),                         //  output,   width = 1,                   .valid
		.rsp_channel        (merlin_demultiplexer_0_src0_channel),                  //   input,   width = 2,            rsp_pck.channel
		.rsp_data           (merlin_demultiplexer_0_src0_data),                     //   input,  width = 32,                   .data
		.rsp_eop            (merlin_demultiplexer_0_src0_endofpacket),              //   input,   width = 1,                   .endofpacket
		.rsp_ready          (merlin_demultiplexer_0_src0_ready),                    //  output,   width = 1,                   .ready
		.rsp_sop            (merlin_demultiplexer_0_src0_startofpacket),            //   input,   width = 1,                   .startofpacket
		.rsp_valid          (merlin_demultiplexer_0_src0_valid),                    //   input,   width = 1,                   .valid
		.wr_en_opcode       (csr_controller_wr_en_opcode_wr_en_opcode),             //   input,   width = 8,       wr_en_opcode.wr_en_opcode
		.polling_opcode     (csr_controller_polling_opcode_polling_opcode),         //   input,   width = 8,     polling_opcode.polling_opcode
		.polling_bit        (csr_controller_polling_bit_polling_bit),               //   input,   width = 3,        polling_bit.polling_bit
		.wr_opcode          (csr_controller_wr_opcode_wr_opcode),                   //   input,   width = 8,          wr_opcode.wr_opcode
		.rd_opcode          (csr_controller_rd_opcode_rd_opcode),                   //   input,   width = 8,          rd_opcode.rd_opcode
		.rd_dummy_cycles    (csr_controller_rd_dummy_cycles_rd_dummy_cycles),       //   input,   width = 5,    rd_dummy_cycles.rd_dummy_cycles
		.xip_trans_type     (xip_controller_xip_trans_type_xip_trans_type),         //  output,   width = 2,     xip_trans_type.xip_trans_type
		.is_4bytes_addr_xip (csr_controller_is_4bytes_addr_xip_is_4bytes_addr_xip), //   input,   width = 1, is_4bytes_addr_xip.is_4bytes_addr_xip
		.chip_select        (csr_controller_chip_select_chip_select)                //   input,   width = 4,        chip_select.chip_select
	);

	intel_generic_serial_flash_interface_addr #(
		.ADDR_WIDTH (23)
	) xip_addr_adaption (
		.clk                       (clk_clk),                                      //   input,   width = 1,   clock_sink.clk
		.reset                     (rst_controller_reset_out_reset),               //   input,   width = 1,        reset.reset
		.avl_mem_write             (avl_mem_write),                                //   input,   width = 1,      avl_mem.write
		.avl_mem_burstcount        (avl_mem_burstcount),                           //   input,   width = 7,             .burstcount
		.avl_mem_waitrequest       (avl_mem_waitrequest),                          //  output,   width = 1,             .waitrequest
		.avl_mem_read              (avl_mem_read),                                 //   input,   width = 1,             .read
		.avl_mem_addr              (avl_mem_address),                              //   input,  width = 23,             .address
		.avl_mem_wrdata            (avl_mem_writedata),                            //   input,  width = 32,             .writedata
		.avl_mem_rddata            (avl_mem_readdata),                             //  output,  width = 32,             .readdata
		.avl_mem_rddata_valid      (avl_mem_readdatavalid),                        //  output,   width = 1,             .readdatavalid
		.avl_mem_byteenable        (avl_mem_byteenable),                           //   input,   width = 4,             .byteenable
		.gen_qspi_mem_addr         (xip_addr_adaption_gen_qspi_mem_address),       //  output,  width = 32, gen_qspi_mem.address
		.gen_qspi_mem_read         (xip_addr_adaption_gen_qspi_mem_read),          //  output,   width = 1,             .read
		.gen_qspi_mem_rddata       (xip_addr_adaption_gen_qspi_mem_readdata),      //   input,  width = 32,             .readdata
		.gen_qspi_mem_write        (xip_addr_adaption_gen_qspi_mem_write),         //  output,   width = 1,             .write
		.gen_qspi_mem_wrdata       (xip_addr_adaption_gen_qspi_mem_writedata),     //  output,  width = 32,             .writedata
		.gen_qspi_mem_byteenable   (xip_addr_adaption_gen_qspi_mem_byteenable),    //  output,   width = 4,             .byteenable
		.gen_qspi_mem_burstcount   (xip_addr_adaption_gen_qspi_mem_burstcount),    //  output,   width = 7,             .burstcount
		.gen_qspi_mem_waitrequest  (xip_addr_adaption_gen_qspi_mem_waitrequest),   //   input,   width = 1,             .waitrequest
		.gen_qspi_mem_rddata_valid (xip_addr_adaption_gen_qspi_mem_readdatavalid)  //   input,   width = 1,             .readdatavalid
	);

	gflish_intel_generic_serial_flash_interface_top_0_altera_merlin_demultiplexer_180_2jiiswq merlin_demultiplexer_0 (
		.clk                (clk_clk),                                                 //   input,   width = 1,       clk.clk
		.reset              (rst_controller_reset_out_reset),                          //   input,   width = 1, clk_reset.reset
		.sink_ready         (serial_flash_inf_cmd_gen_inst_out_rsp_pck_ready),         //  output,   width = 1,      sink.ready
		.sink_channel       (serial_flash_inf_cmd_gen_inst_out_rsp_pck_channel),       //   input,   width = 2,          .channel
		.sink_data          (serial_flash_inf_cmd_gen_inst_out_rsp_pck_data),          //   input,  width = 32,          .data
		.sink_startofpacket (serial_flash_inf_cmd_gen_inst_out_rsp_pck_startofpacket), //   input,   width = 1,          .startofpacket
		.sink_endofpacket   (serial_flash_inf_cmd_gen_inst_out_rsp_pck_endofpacket),   //   input,   width = 1,          .endofpacket
		.sink_valid         (serial_flash_inf_cmd_gen_inst_out_rsp_pck_valid),         //   input,   width = 1,          .valid
		.src0_ready         (merlin_demultiplexer_0_src0_ready),                       //   input,   width = 1,      src0.ready
		.src0_valid         (merlin_demultiplexer_0_src0_valid),                       //  output,   width = 1,          .valid
		.src0_data          (merlin_demultiplexer_0_src0_data),                        //  output,  width = 32,          .data
		.src0_channel       (merlin_demultiplexer_0_src0_channel),                     //  output,   width = 2,          .channel
		.src0_startofpacket (merlin_demultiplexer_0_src0_startofpacket),               //  output,   width = 1,          .startofpacket
		.src0_endofpacket   (merlin_demultiplexer_0_src0_endofpacket),                 //  output,   width = 1,          .endofpacket
		.src1_ready         (merlin_demultiplexer_0_src1_ready),                       //   input,   width = 1,      src1.ready
		.src1_valid         (merlin_demultiplexer_0_src1_valid),                       //  output,   width = 1,          .valid
		.src1_data          (merlin_demultiplexer_0_src1_data),                        //  output,  width = 32,          .data
		.src1_channel       (merlin_demultiplexer_0_src1_channel),                     //  output,   width = 2,          .channel
		.src1_startofpacket (merlin_demultiplexer_0_src1_startofpacket),               //  output,   width = 1,          .startofpacket
		.src1_endofpacket   (merlin_demultiplexer_0_src1_endofpacket)                  //  output,   width = 1,          .endofpacket
	);

	gflish_intel_generic_serial_flash_interface_top_0_altera_merlin_multiplexer_180_6y6egqy multiplexer (
		.clk                 (clk_clk),                              //   input,   width = 1,       clk.clk
		.reset               (rst_controller_reset_out_reset),       //   input,   width = 1, clk_reset.reset
		.src_ready           (multiplexer_src_ready),                //   input,   width = 1,       src.ready
		.src_valid           (multiplexer_src_valid),                //  output,   width = 1,          .valid
		.src_data            (multiplexer_src_data),                 //  output,  width = 32,          .data
		.src_channel         (multiplexer_src_channel),              //  output,   width = 2,          .channel
		.src_startofpacket   (multiplexer_src_startofpacket),        //  output,   width = 1,          .startofpacket
		.src_endofpacket     (multiplexer_src_endofpacket),          //  output,   width = 1,          .endofpacket
		.sink0_ready         (xip_controller_cmd_pck_ready),         //  output,   width = 1,     sink0.ready
		.sink0_valid         (xip_controller_cmd_pck_valid),         //   input,   width = 1,          .valid
		.sink0_channel       (xip_controller_cmd_pck_channel),       //   input,   width = 2,          .channel
		.sink0_data          (xip_controller_cmd_pck_data),          //   input,  width = 32,          .data
		.sink0_startofpacket (xip_controller_cmd_pck_startofpacket), //   input,   width = 1,          .startofpacket
		.sink0_endofpacket   (xip_controller_cmd_pck_endofpacket),   //   input,   width = 1,          .endofpacket
		.sink1_ready         (csr_controller_cmd_pck_ready),         //  output,   width = 1,     sink1.ready
		.sink1_valid         (csr_controller_cmd_pck_valid),         //   input,   width = 1,          .valid
		.sink1_channel       (csr_controller_cmd_pck_channel),       //   input,   width = 2,          .channel
		.sink1_data          (csr_controller_cmd_pck_data),          //   input,  width = 32,          .data
		.sink1_startofpacket (csr_controller_cmd_pck_startofpacket), //   input,   width = 1,          .startofpacket
		.sink1_endofpacket   (csr_controller_cmd_pck_endofpacket)    //   input,   width = 1,          .endofpacket
	);

	intel_generic_serial_flash_interface_cmd serial_flash_inf_cmd_gen_inst (
		.clk             (clk_clk),                                                     //   input,   width = 1,            clk.clk
		.reset           (rst_controller_reset_out_reset),                              //   input,   width = 1,          reset.reset
		.in_cmd_channel  (multiplexer_src_channel),                                     //   input,   width = 2,     in_cmd_pck.channel
		.in_cmd_eop      (multiplexer_src_endofpacket),                                 //   input,   width = 1,               .endofpacket
		.in_cmd_ready    (multiplexer_src_ready),                                       //  output,   width = 1,               .ready
		.in_cmd_sop      (multiplexer_src_startofpacket),                               //   input,   width = 1,               .startofpacket
		.in_cmd_data     (multiplexer_src_data),                                        //   input,  width = 32,               .data
		.in_cmd_valid    (multiplexer_src_valid),                                       //   input,   width = 1,               .valid
		.out_cmd_channel (serial_flash_inf_cmd_gen_inst_out_cmd_pck_channel),           //  output,   width = 9,    out_cmd_pck.channel
		.out_cmd_eop     (serial_flash_inf_cmd_gen_inst_out_cmd_pck_endofpacket),       //  output,   width = 1,               .endofpacket
		.out_cmd_ready   (serial_flash_inf_cmd_gen_inst_out_cmd_pck_ready),             //   input,   width = 1,               .ready
		.out_cmd_sop     (serial_flash_inf_cmd_gen_inst_out_cmd_pck_startofpacket),     //  output,   width = 1,               .startofpacket
		.out_cmd_data    (serial_flash_inf_cmd_gen_inst_out_cmd_pck_data),              //  output,   width = 8,               .data
		.out_cmd_valid   (serial_flash_inf_cmd_gen_inst_out_cmd_pck_valid),             //  output,   width = 1,               .valid
		.in_rsp_data     (qspi_inf_inst_out_rsp_pck_data),                              //   input,   width = 8,     in_rsp_pck.data
		.in_rsp_ready    (qspi_inf_inst_out_rsp_pck_ready),                             //  output,   width = 1,               .ready
		.in_rsp_valid    (qspi_inf_inst_out_rsp_pck_valid),                             //   input,   width = 1,               .valid
		.out_rsp_channel (serial_flash_inf_cmd_gen_inst_out_rsp_pck_channel),           //  output,   width = 2,    out_rsp_pck.channel
		.out_rsp_data    (serial_flash_inf_cmd_gen_inst_out_rsp_pck_data),              //  output,  width = 32,               .data
		.out_rsp_eop     (serial_flash_inf_cmd_gen_inst_out_rsp_pck_endofpacket),       //  output,   width = 1,               .endofpacket
		.out_rsp_ready   (serial_flash_inf_cmd_gen_inst_out_rsp_pck_ready),             //   input,   width = 1,               .ready
		.out_rsp_sop     (serial_flash_inf_cmd_gen_inst_out_rsp_pck_startofpacket),     //  output,   width = 1,               .startofpacket
		.out_rsp_valid   (serial_flash_inf_cmd_gen_inst_out_rsp_pck_valid),             //  output,   width = 1,               .valid
		.addr_bytes_csr  (csr_controller_addr_bytes_csr_addr_bytes_csr),                //   input,  width = 32, addr_bytes_csr.addr_bytes_csr
		.addr_bytes_xip  (xip_controller_addr_bytes_xip_addr_bytes_xip),                //   input,  width = 32, addr_bytes_xip.addr_bytes_xip
		.dummy_cycles    (serial_flash_inf_cmd_gen_inst_dummy_cycles_dummy_cycles),     //  output,   width = 5,   dummy_cycles.dummy_cycles
		.chip_select     (serial_flash_inf_cmd_gen_inst_chip_select_chip_select),       //  output,   width = 4,    chip_select.chip_select
		.require_rdata   (serial_flash_inf_cmd_gen_inst_require_rdata_require_rdata),   //  output,   width = 1,  require_rdata.require_rdata
		.op_type         (csr_controller_op_type_op_type),                              //   input,   width = 2,        op_type.op_type
		.wr_addr_type    (csr_controller_wr_addr_type_wr_addr_type),                    //   input,   width = 2,   wr_addr_type.wr_addr_type
		.wr_data_type    (csr_controller_wr_data_type_wr_data_type),                    //   input,   width = 2,   wr_data_type.wr_data_type
		.rd_addr_type    (csr_controller_rd_addr_type_rd_addr_type),                    //   input,   width = 2,   rd_addr_type.rd_addr_type
		.rd_data_type    (csr_controller_rd_data_type_rd_data_type),                    //   input,   width = 2,   rd_data_type.rd_data_type
		.op_num_lines    (serial_flash_inf_cmd_gen_inst_op_num_lines_op_num_lines),     //  output,   width = 4,   op_num_lines.op_num_lines
		.addr_num_lines  (serial_flash_inf_cmd_gen_inst_addr_num_lines_addr_num_lines), //  output,   width = 4, addr_num_lines.addr_num_lines
		.data_num_lines  (serial_flash_inf_cmd_gen_inst_data_num_lines_data_num_lines), //  output,   width = 4, data_num_lines.data_num_lines
		.xip_trans_type  (xip_controller_xip_trans_type_xip_trans_type)                 //   input,   width = 2, xip_trans_type.xip_trans_type
	);

	gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_if_ctrl_180_rl2nqhy #(
		.DEV_FAMILY       ("Arria 10"),
		.NCS_LENGTH       (3),
		.DATA_LENGTH      (4),
		.MODE_LENGTH      (4),
		.ENABLE_SIM_MODEL ("false")
	) qspi_inf_inst (
		.clk                (clk_clk),                                                     //   input,  width = 1,                clk.clk
		.reset              (rst_controller_reset_out_reset),                              //   input,  width = 1,              reset.reset
		.in_cmd_channel     (serial_flash_inf_cmd_gen_inst_out_cmd_pck_channel),           //   input,  width = 9,         in_cmd_pck.channel
		.in_cmd_eop         (serial_flash_inf_cmd_gen_inst_out_cmd_pck_endofpacket),       //   input,  width = 1,                   .endofpacket
		.in_cmd_ready       (serial_flash_inf_cmd_gen_inst_out_cmd_pck_ready),             //  output,  width = 1,                   .ready
		.in_cmd_sop         (serial_flash_inf_cmd_gen_inst_out_cmd_pck_startofpacket),     //   input,  width = 1,                   .startofpacket
		.in_cmd_data        (serial_flash_inf_cmd_gen_inst_out_cmd_pck_data),              //   input,  width = 8,                   .data
		.in_cmd_valid       (serial_flash_inf_cmd_gen_inst_out_cmd_pck_valid),             //   input,  width = 1,                   .valid
		.out_rsp_data       (qspi_inf_inst_out_rsp_pck_data),                              //  output,  width = 8,        out_rsp_pck.data
		.out_rsp_valid      (qspi_inf_inst_out_rsp_pck_valid),                             //  output,  width = 1,                   .valid
		.out_rsp_ready      (qspi_inf_inst_out_rsp_pck_ready),                             //   input,  width = 1,                   .ready
		.dummy_cycles       (serial_flash_inf_cmd_gen_inst_dummy_cycles_dummy_cycles),     //   input,  width = 5,       dummy_cycles.dummy_cycles
		.chip_select        (serial_flash_inf_cmd_gen_inst_chip_select_chip_select),       //   input,  width = 4,        chip_select.chip_select
		.qspi_interface_en  (csr_controller_qspi_interface_en_qspi_interface_en),          //   input,  width = 1,  qspi_interface_en.qspi_interface_en
		.require_rdata      (serial_flash_inf_cmd_gen_inst_require_rdata_require_rdata),   //   input,  width = 1,      require_rdata.require_rdata
		.op_num_lines       (serial_flash_inf_cmd_gen_inst_op_num_lines_op_num_lines),     //   input,  width = 4,       op_num_lines.op_num_lines
		.addr_num_lines     (serial_flash_inf_cmd_gen_inst_addr_num_lines_addr_num_lines), //   input,  width = 4,     addr_num_lines.addr_num_lines
		.data_num_lines     (serial_flash_inf_cmd_gen_inst_data_num_lines_data_num_lines), //   input,  width = 4,     data_num_lines.data_num_lines
		.baud_rate_divisor  (csr_controller_baud_rate_divisor_baud_rate_divisor),          //   input,  width = 5,  baud_rate_divisor.baud_rate_divisor
		.cs_delay_setting   (csr_controller_cs_delay_setting_cs_delay_setting),            //   input,  width = 8,   cs_delay_setting.cs_delay_setting
		.read_capture_delay (csr_controller_read_capture_delay_read_capture_delay)         //   input,  width = 4, read_capture_delay.read_capture_delay
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset_reset),                    //   input,  width = 1, reset_in0.reset
		.clk            (clk_clk),                        //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_in1      (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

endmodule
