# Reading C:/intelFPGA/17.1/modelsim_ase/tcl/vsim/pref.tcl cd C:/Users/anandr1x/Desktop/fft/fftsim/simulation # reading C:/intelFPGA/17.1/modelsim_ase/win32aloem/../modelsim.ini set QSYS_SIMDIR C:/Users/anandr1x/Desktop/fft/fftsim/simulation # C:/Users/anandr1x/Desktop/fft/fftsim/simulation source $QSYS_SIMDIR/mentor/msim_setup.tcl # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Platform Designer base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. dev_com # [exec] dev_com com # [exec] com # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:02 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/auk_dspip_text_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling package auk_dspip_text_pkg # -- Compiling package body auk_dspip_text_pkg # -- Loading package auk_dspip_text_pkg # End time: 10:10:02 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:02 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/auk_dspip_math_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling package auk_dspip_math_pkg # -- Compiling package body auk_dspip_math_pkg # -- Loading package auk_dspip_math_pkg # End time: 10:10:03 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:03 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/auk_dspip_lib_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Compiling package auk_dspip_lib_pkg # End time: 10:10:03 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:03 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Compiling entity auk_dspip_avalon_streaming_block_sink # -- Compiling architecture rtl of auk_dspip_avalon_streaming_block_sink # End time: 10:10:04 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:04 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Loading package altera_mf_components # -- Compiling entity auk_dspip_avalon_streaming_block_source # -- Compiling architecture rtl of auk_dspip_avalon_streaming_block_source # End time: 10:10:05 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:05 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/auk_dspip_roundsat.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity auk_dspip_roundsat # -- Compiling architecture beh of auk_dspip_roundsat # End time: 10:10:05 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:05 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/apn_fft_mult_can.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity apn_fft_mult_can # -- Compiling architecture rtl of apn_fft_mult_can # End time: 10:10:05 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:06 on Mar 21,2019 # vlog -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/apn_fft_mult_cpx_1825.v -work fft_ii_0 # # Top level modules: # End time: 10:10:07 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:08 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/apn_fft_mult_cpx.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity apn_fft_mult_cpx # -- Compiling architecture rtl of apn_fft_mult_cpx # End time: 10:10:08 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:08 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/hyper_opt_OFF_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling package hyper_opt_pkg # End time: 10:10:08 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:08 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/altera_fft_dual_port_ram.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Compiling entity altera_fft_dual_port_ram # -- Compiling architecture rtl of altera_fft_dual_port_ram # End time: 10:10:09 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:09 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/altera_fft_dual_port_rom.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Compiling entity altera_fft_dual_port_rom # -- Compiling architecture rtl of altera_fft_dual_port_rom # End time: 10:10:10 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:10 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/altera_fft_mult_add.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_SIGNED # -- Compiling entity altera_fft_mult_add # -- Compiling architecture rtl of altera_fft_mult_add # -- Loading package altera_lnsim_components # -- Compiling entity altera_fft_mult_add_new # -- Compiling architecture rtl of altera_fft_mult_add_new # -- Loading package altera_mf_components # -- Compiling entity altera_fft_mult_add_old # -- Compiling architecture rtl of altera_fft_mult_add_old # End time: 10:10:10 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:10 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/altera_fft_single_port_rom.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package altera_mf_components # -- Loading package altera_lnsim_components # -- Compiling entity altera_fft_single_port_rom # -- Compiling architecture rtl of altera_fft_single_port_rom # End time: 10:10:11 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:11 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_fft_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling package auk_fft_pkg # -- Compiling package body auk_fft_pkg # -- Loading package auk_fft_pkg # End time: 10:10:12 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:13 on Mar 21,2019 # vlog -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/hyper_pipeline_interface.v -work fft_ii_0 # # Top level modules: # End time: 10:10:14 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:14 on Mar 21,2019 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/counter_module.sv -work fft_ii_0 # # Top level modules: # End time: 10:10:16 on Mar 21,2019, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:16 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_lib_pkg.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Compiling package auk_dspip_r22sdf_lib_pkg # End time: 10:10:16 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:16 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_bit_reverse_addr_control.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_bit_reverse_addr_control # -- Compiling architecture rtl of auk_dspip_bit_reverse_addr_control # End time: 10:10:17 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:17 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_bit_reverse_core.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Loading package altera_mf_components # -- Compiling entity auk_dspip_bit_reverse_core # -- Compiling architecture rtl of auk_dspip_bit_reverse_core # End time: 10:10:17 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:18 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_bit_reverse_reverse_carry_adder.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity auk_dspip_bit_reverse_reverse_carry_adder # -- Compiling architecture rtl of auk_dspip_bit_reverse_reverse_carry_adder # End time: 10:10:18 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:18 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_adder_fp.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_SIGNED # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Compiling entity auk_dspip_r22sdf_adder_fp # -- Compiling architecture rtl of auk_dspip_r22sdf_adder_fp # End time: 10:10:18 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:18 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_addsub.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package LPM_COMPONENTS # -- Loading package altera_mf_components # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_addsub # -- Compiling architecture rtl of auk_dspip_r22sdf_addsub # End time: 10:10:19 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:20 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_bfi.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_bfi # -- Compiling architecture rtl2 of auk_dspip_r22sdf_bfi # End time: 10:10:20 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:20 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_bfii.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_bfii # -- Compiling architecture rtl of auk_dspip_r22sdf_bfii # End time: 10:10:20 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:21 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_bf_control.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_bf_control # -- Compiling architecture rtl of auk_dspip_r22sdf_bf_control # End time: 10:10:21 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:21 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_cma.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package altera_lnsim_components # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_cma # -- Compiling architecture rtl of auk_dspip_r22sdf_cma # End time: 10:10:22 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:22 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_cma_adder_fp.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package STD_LOGIC_SIGNED # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Compiling entity auk_dspip_r22sdf_cma_adder_fp # -- Compiling architecture rtl of auk_dspip_r22sdf_cma_adder_fp # End time: 10:10:22 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:22 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_cma_bfi_fp.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_cma_bfi_fp # -- Compiling architecture rtl of auk_dspip_r22sdf_cma_bfi_fp # End time: 10:10:23 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:23 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_cma_fp.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package altera_lnsim_components # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_cma_fp # -- Compiling architecture rtl of auk_dspip_r22sdf_cma_fp # End time: 10:10:23 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:23 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_core.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_text_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_core # -- Compiling architecture rtl of auk_dspip_r22sdf_core # End time: 10:10:24 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:25 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_counter.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Compiling entity auk_dspip_r22sdf_counter # -- Compiling architecture rtl of auk_dspip_r22sdf_counter # End time: 10:10:25 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:25 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_delay.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Loading package altera_mf_components # -- Compiling entity auk_dspip_r22sdf_delay # -- Compiling architecture rtl of auk_dspip_r22sdf_delay # End time: 10:10:26 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:26 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_enable_control.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_enable_control # -- Compiling architecture rtl of auk_dspip_r22sdf_enable_control # End time: 10:10:26 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:26 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_stage # -- Compiling architecture rtl of auk_dspip_r22sdf_stage # End time: 10:10:27 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:27 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_stg_out_pipe.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Compiling entity auk_dspip_r22sdf_stg_out_pipe # -- Compiling architecture rtl of auk_dspip_r22sdf_stg_out_pipe # End time: 10:10:27 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:27 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_stg_pipe.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Compiling entity auk_dspip_r22sdf_stg_pipe # -- Compiling architecture rtl of auk_dspip_r22sdf_stg_pipe # End time: 10:10:27 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:27 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_top.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package auk_dspip_lib_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Compiling entity auk_dspip_r22sdf_top # -- Compiling architecture str of auk_dspip_r22sdf_top # End time: 10:10:28 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:29 on Mar 21,2019 # vcom -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/mentor/auk_dspip_r22sdf_twrom.vhd -work fft_ii_0 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package auk_dspip_math_pkg # -- Loading package hyper_opt_pkg # -- Loading package auk_dspip_r22sdf_lib_pkg # -- Loading package altera_mf_components # -- Compiling entity auk_dspip_r22sdf_twrom # -- Compiling architecture rtl of auk_dspip_r22sdf_twrom # End time: 10:10:29 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:29 on Mar 21,2019 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/fft/fftsim/simulation/submodules/fftsim_fft_ii_0.sv -work fft_ii_0 # -- Compiling module fftsim_fft_ii_0 # # Top level modules: # fftsim_fft_ii_0 # End time: 10:10:29 on Mar 21,2019, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 10:10:29 on Mar 21,2019 # vlog -reportprogress 300 C:/Users/anandr1x/Desktop/fft/fftsim/simulation/fftsim.v # -- Compiling module fftsim # # Top level modules: # fftsim # End time: 10:10:30 on Mar 21,2019, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 elab # [exec] elab # vsim -t ps -L work -L work_lib -L fft_ii_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev fftsim # Start time: 10:11:26 on Mar 21,2019 # Loading work.fftsim # Loading sv_std.std # Loading fft_ii_0.fftsim_fft_ii_0 # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading fft_ii_0.auk_dspip_math_pkg(body) # Loading fft_ii_0.auk_dspip_lib_pkg # Loading fft_ii_0.hyper_opt_pkg # Loading fft_ii_0.auk_dspip_r22sdf_lib_pkg # Loading fft_ii_0.auk_dspip_r22sdf_top(str) # Loading fft_ii_0.auk_dspip_avalon_streaming_block_sink(rtl) # Loading altera_mf_ver.scfifo # Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES # Loading ieee.math_real(body) # Loading fft_ii_0.auk_dspip_text_pkg(body) # Loading fft_ii_0.auk_dspip_r22sdf_core(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_enable_control(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_stage(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_bfi(rtl2) # Loading lpm.lpm_components # Loading altera_mf.altera_mf_components # Loading fft_ii_0.auk_dspip_r22sdf_addsub(rtl) # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.std_logic_unsigned(body) # Loading lpm.lpm_add_sub(lpm_syn) # Loading lpm.lpm_add_sub_signed(lpm_syn) # Loading fft_ii_0.auk_dspip_r22sdf_bf_control(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_counter(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_delay(rtl) # Loading altera_lnsim.altera_lnsim_components # Loading fft_ii_0.altera_fft_dual_port_ram(rtl) # Loading altera_mf.altera_common_conversion(body) # Loading altera_mf.altera_device_families(body) # Loading altera_mf.altsyncram(translated) # Loading fft_ii_0.auk_dspip_r22sdf_bfii(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_stg_pipe(rtl) # Loading fft_ii_0.auk_dspip_r22sdf_cma(rtl) # Loading fft_ii_0.apn_fft_mult_can(rtl) # Loading fft_ii_0.auk_dspip_roundsat(beh) # Loading fft_ii_0.auk_dspip_r22sdf_twrom(rtl) # Loading fft_ii_0.altera_fft_single_port_rom(rtl) # Loading fft_ii_0.auk_dspip_avalon_streaming_block_source(rtl) # Loading altera_mf.scfifo(behavior) # ** Warning: Design size of 52214 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. # Expect performance to be adversely affected.