-- RTL for Mux_4to1

	library ieee;
	use ieee.std_logic_1164.all;
--	use ieee.std_logic_arith.all;
-- 	use ieee.std_logic_unsigned.all;
--	use ieee.numeric_std.all;
	
	entity mux_4to1 is
	port (a_in, b_in, c_in, d_in: in std_logic;
	sel_in: in std_logic_vector (1 downto 0);
	y_out: out std_logic);
	end mux_4to1;

	architecture arch_mux_4to1 of mux_4to1 is
	begin
	comb_P1: process (a_in, b_in, c_in, d_in,sel_in)
	begin
	case (sel_in) is
		when "00" => y_out<=a_in;
		when "01" => y_out<=b_in;
		when "10" => y_out<=c_in;
		when "11" => y_out<=d_in;
	end case;
	end process comb_P1; end arch_mux_4to1;
	
	-- Testbench for Mux_4to1

	library ieee;
	use ieee.std_logic_1164.all;
--	use ieee.std_logic_arith.all;
-- 	use ieee.std_logic_unsigned.all;
--	use ieee.numeric_std.all;
	
	entity testbench_mux_4to1 is
	end;

	architecture arch_testbench of testbench_mux_4to1 is
	
	component mux_4to1
	port (a_in, b_in, c_in, d_in: in std_logic;
	sel_in: in std_logic_vector (1 downto 0);
	y_out: out std_logic);
	end component;

	signal sel_in: std_logic_vector (1 downto 0);
	signal a_in, b_in, c_in, d_in,y_out: std_logic;
	
	begin
	sel_in <= "00", "01" after 20 ns, "10"after 40ns,
		"11" after 60ns, "XX" after 90ns, "00" after 110ns;
a_in <= 'X', '0' after 5ns, '1' after 10ns; 
b_in <= 'X', '0' after 20ns, '1' after 30ns;
c_in <= 'X', '0' after 40ns, '1' after 60ns;
d_in <= 'X', '0' after 100ns, '1' after 110ns;

U: mux_4to1 port map (a_in, b_in, c_in, d_in,sel_in,y_out); 
end arch_testbench;