### FPGA clock 25MHz ###
create_clock -name fpga_clk_in_25	-period "25 MHz" [get_ports FPGA_CLOCK_25MHZ]

### PLL Clocks ### 
# Do not use the derive_pll_clocks assignment before constraining individual clock since these assignments will not be used since the clock already has an assignment
#derive_pll_clocks -create_base_clocks
#create_generated_clock -name pll_clk_out_50 -source [get_ports FPGA_CLOCK_25MHZ] -multiply_by 2 [get_pins {pll_inst|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name pll_clk_out_50 -source [get_ports {FPGA_CLOCK_25MHZ}] -multiply_by 2 [get_pins {pll50Mhz_int0|altpll_component|auto_generated|pll1|clk[0]}]
# for enhancing USB BlasterII to be reliable, 25MHz - Inferred for the JTAG UART
#create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 
#set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] -add_delay
#set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] -add_delay
#set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] -add_delay


#create_generated_clock -name CBUS_Cnt_CLK -source [get_pins {pll50Mhz_int0|altpll_component|auto_generated|pll1|clk[0]}] [get_pins {WrapSyncPllBde:SyncPllUc|SyncPllVhd:SyncPll|siLocalPhaseCnt[0]}]
#create_generated_clock -name Flash -source [get_pins {pll50Mhz_int0|altpll_component|auto_generated|pll1|clk[0]}] [get_nets *flash_se_neg_reg]