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-- Your use of Intel Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "05/07/2019 16:13:17"
                                                            
-- Vhdl Test Bench template for design  :  MAIN_ENT
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY MAIN_ENT_vhd_tst IS
END MAIN_ENT_vhd_tst;
ARCHITECTURE MAIN_ENT_arch OF MAIN_ENT_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL CLK_IN : STD_LOGIC;
SIGNAL CLK_OUT : STD_LOGIC;
SIGNAL LOCKED : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
COMPONENT MAIN_ENT
	PORT (
	CLK_IN : IN STD_LOGIC;
	CLK_OUT : OUT STD_LOGIC;
	LOCKED : OUT STD_LOGIC;
	RESET : IN STD_LOGIC
	);
END COMPONENT;
BEGIN
	i1 : MAIN_ENT
	PORT MAP (
-- list connections between master ports and signals
	CLK_IN => CLK_IN,
	CLK_OUT => CLK_OUT,
	LOCKED => LOCKED,
	RESET => RESET
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once                      
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END MAIN_ENT_arch;
