library ieee;
use ieee. std_logic_1164. all;
entity MAIN_ENT is
port (
RESET  : in std_logic;
CLK_IN : in std_logic;
LOCKED : out std_logic;
CLK_OUT: out std_logic
);
end entity;
architecture BEH of MAIN_ENT is
--------------------------------------------------------------
--------------------///COMPONENTS///--------------------------
--component ALTPLL_0001 is  
--	port ( 
--		refclk   : in  std_logic := '0'; --  refclk.clk
--		rst      : in  std_logic := '0'; --   reset.reset
--		outclk_0 : out std_logic;        -- outclk0.clk
--		locked   : out std_logic         --  locked.export
--	);
--end component;
component ALTPLL_0001_0002 is
		port (
			refclk   : in  std_logic := 'X'; -- clk
			rst      : in  std_logic := 'X'; -- reset
			outclk_0 : out std_logic;        -- clk
			locked   : out std_logic         -- export
		);
	end component ALTPLL_0001_0002;   
------------------------------------------------------------------
begin
U1:  ALTPLL_0001_0002 
	port map( 
		refclk   => CLK_IN,
		rst      => RESET,
		outclk_0 => CLK_OUT,
		locked   => LOCKED
	);
end architecture;
