library ieee;
use ieee. std_logic_1164. all;
entity ALTPLL_0001_TB is
end entity;
architecture BEH of ALTPLL_0001_TB is
---------------------------------------------
--------------///COMPONENT///----------------
component MAIN_ENT is
port (
RESET  : in std_logic;
CLK_IN : in std_logic;
LOCKED : out std_logic;
CLK_OUT: out std_logic
);
end component;
---------------------------------------------
--------------///SIGNALS////-----------------
signal RESET  : std_logic;
signal CLK_IN :  std_logic:='0';
signal LOCKED :  std_logic;
signal CLK_OUT:  std_logic;
---------------------------------------------
begin
UUT1: MAIN_ENT 
port map(
RESET  =>RESET,
CLK_IN => CLK_IN,
LOCKED => LOCKED,
CLK_OUT=> CLK_OUT
);
RESET<='1', '0' after 500 ns;
CLK_IN<= not CLK_IN after 5 ns;

end architecture;
