TimeQuest Timing Analyzer report for top_andromeda Thu Jun 25 16:37:47 2020 Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. SDC File List 5. Clocks 6. Slow 1200mV 100C Model Fmax Summary 7. Slow 1200mV 100C Model Setup Summary 8. Slow 1200mV 100C Model Hold Summary 9. Slow 1200mV 100C Model Recovery Summary 10. Slow 1200mV 100C Model Removal Summary 11. Slow 1200mV 100C Model Minimum Pulse Width Summary 12. Slow 1200mV 100C Model Metastability Summary 13. Slow 1200mV -40C Model Fmax Summary 14. Slow 1200mV -40C Model Setup Summary 15. Slow 1200mV -40C Model Hold Summary 16. Slow 1200mV -40C Model Recovery Summary 17. Slow 1200mV -40C Model Removal Summary 18. Slow 1200mV -40C Model Minimum Pulse Width Summary 19. Slow 1200mV -40C Model Metastability Summary 20. Fast 1200mV -40C Model Setup Summary 21. Fast 1200mV -40C Model Hold Summary 22. Fast 1200mV -40C Model Recovery Summary 23. Fast 1200mV -40C Model Removal Summary 24. Fast 1200mV -40C Model Minimum Pulse Width Summary 25. Fast 1200mV -40C Model Metastability Summary 26. Multicorner Timing Analysis Summary 27. Board Trace Model Assignments 28. Input Transition Times 29. Signal Integrity Metrics (Slow 1200mv n40c Model) 30. Signal Integrity Metrics (Slow 1200mv 100c Model) 31. Signal Integrity Metrics (Fast 1200mv n40c Model) 32. Setup Transfers 33. Hold Transfers 34. Recovery Transfers 35. Removal Transfers 36. Report TCCS 37. Report RSKM 38. Unconstrained Paths Summary 39. Clock Status Summary 40. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +-----------------------+-----------------------------------------------------+ ; Quartus Prime Version ; Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition ; ; Timing Analyzer ; TimeQuest ; ; Revision Name ; top_andromeda ; ; Device Family ; MAX 10 ; ; Device Name ; 10M08SCU169I7G ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+-----------------------------------------------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +-------------------------------------------------------+ ; SDC File List ; +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ ; top_andromeda.sdc ; OK ; Thu Jun 25 16:37:41 2020 ; +-------------------+--------+--------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +---------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------+-----------------------------------------------------+-------------------------------------------------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +---------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------+-----------------------------------------------------+-------------------------------------------------------+ ; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; ; eth0_gtx_clk ; Generated ; 8.000 ; 125.0 MHz ; 2.000 ; 6.000 ; ; 1 ; 1 ; ; ; ; ; false ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; { eth0_gtx_clk } ; ; eth0_rx_clk ; Base ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; ; ; ; ; ; ; ; ; ; ; { eth0_rx_clk } ; ; eth0_rx_clk_virtual ; Virtual ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; ; ; ; ; ; ; ; ; ; ; { } ; ; eth1_gtx_clk ; Generated ; 8.000 ; 125.0 MHz ; 2.000 ; 6.000 ; ; 1 ; 1 ; ; ; ; ; false ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; { eth1_gtx_clk } ; ; eth1_rx_clk ; Base ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; ; ; ; ; ; ; ; ; ; ; { eth1_rx_clk } ; ; eth1_rx_clk_virtual ; Virtual ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; ; ; ; ; ; ; ; ; ; ; { } ; ; ext_clk25mhz ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { ext_clk25mhz } ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; 50.00 ; 1 ; 4 ; ; ; ; ; false ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|inclk[0] ; { i_pll|altpll_component|auto_generated|pll1|clk[0] } ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; 50.00 ; 1 ; 5 ; ; ; ; ; false ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|inclk[0] ; { i_pll|altpll_component|auto_generated|pll1|clk[1] } ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.000 ; 125.0 MHz ; 2.000 ; 6.000 ; 50.00 ; 1 ; 5 ; 90.0 ; ; ; ; false ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|inclk[0] ; { i_pll|altpll_component|auto_generated|pll1|clk[2] } ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 8.000 ; 125.0 MHz ; 0.000 ; 4.000 ; 50.00 ; 1 ; 5 ; ; ; ; ; false ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|inclk[0] ; { i_pll|altpll_component|auto_generated|pll1|clk[3] } ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 8.000 ; 125.0 MHz ; 2.000 ; 6.000 ; 50.00 ; 1 ; 5 ; 90.0 ; ; ; ; false ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|inclk[0] ; { i_pll|altpll_component|auto_generated|pll1|clk[4] } ; +---------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------+-----------------------------------------------------+-------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Fmax Summary ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ ; 88.07 MHz ; 88.07 MHz ; altera_reserved_tck ; ; ; 119.72 MHz ; 119.72 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; ; ; 129.42 MHz ; 129.42 MHz ; eth0_rx_clk ; ; ; 136.13 MHz ; 136.13 MHz ; eth1_rx_clk ; ; ; 164.23 MHz ; 164.23 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; ; ; 202.31 MHz ; 202.31 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; ; ; 710.23 MHz ; 250.0 MHz ; ext_clk25mhz ; limit due to minimum period restriction (max I/O toggle rate) ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +----------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Setup Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 0.273 ; 0.000 ; ; eth1_rx_clk ; 0.318 ; 0.000 ; ; eth1_gtx_clk ; 0.375 ; 0.000 ; ; eth0_gtx_clk ; 0.445 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 1.647 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 1.911 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.057 ; 0.000 ; ; ext_clk25mhz ; 38.592 ; 0.000 ; ; altera_reserved_tck ; 44.323 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Hold Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.256 ; 0.000 ; ; eth1_rx_clk ; 0.258 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.294 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 0.300 ; 0.000 ; ; eth0_rx_clk ; 0.338 ; 0.000 ; ; altera_reserved_tck ; 0.348 ; 0.000 ; ; ext_clk25mhz ; 0.378 ; 0.000 ; ; eth0_gtx_clk ; 0.578 ; 0.000 ; ; eth1_gtx_clk ; 0.605 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Recovery Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 1.974 ; 0.000 ; ; eth1_rx_clk ; 2.221 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 3.706 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 4.304 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 4.621 ; 0.000 ; ; altera_reserved_tck ; 48.313 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Removal Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; eth1_rx_clk ; 0.932 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.932 ; 0.000 ; ; altera_reserved_tck ; 1.091 ; 0.000 ; ; eth0_rx_clk ; 1.399 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 1.557 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 4.512 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Slow 1200mV 100C Model Minimum Pulse Width Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 3.434 ; 0.000 ; ; eth1_rx_clk ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; 3.741 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; 3.746 ; 0.000 ; ; eth0_gtx_clk ; 3.790 ; 0.000 ; ; eth1_gtx_clk ; 3.790 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 4.658 ; 0.000 ; ; ext_clk25mhz ; 19.592 ; 0.000 ; ; altera_reserved_tck ; 49.471 ; 0.000 ; +---------------------------------------------------+--------+---------------+ ------------------------------------------------ ; Slow 1200mV 100C Model Metastability Summary ; ------------------------------------------------ The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 49 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 8.539 ns +--------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Fmax Summary ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ ; 97.22 MHz ; 97.22 MHz ; altera_reserved_tck ; ; ; 133.44 MHz ; 133.44 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; ; ; 149.01 MHz ; 149.01 MHz ; eth0_rx_clk ; ; ; 154.66 MHz ; 154.66 MHz ; eth1_rx_clk ; ; ; 185.74 MHz ; 185.74 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; ; ; 228.26 MHz ; 219.01 MHz ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; limit due to minimum period restriction (tmin) ; ; 824.4 MHz ; 250.0 MHz ; ext_clk25mhz ; limit due to minimum period restriction (max I/O toggle rate) ; +------------+-----------------+---------------------------------------------------+---------------------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +----------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Setup Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth1_rx_clk ; 0.412 ; 0.000 ; ; eth1_gtx_clk ; 0.469 ; 0.000 ; ; eth0_gtx_clk ; 0.504 ; 0.000 ; ; eth0_rx_clk ; 0.613 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 2.506 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 2.616 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.619 ; 0.000 ; ; ext_clk25mhz ; 38.787 ; 0.000 ; ; altera_reserved_tck ; 44.857 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Hold Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.250 ; 0.000 ; ; eth1_rx_clk ; 0.255 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.283 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 0.288 ; 0.000 ; ; eth0_rx_clk ; 0.296 ; 0.000 ; ; altera_reserved_tck ; 0.298 ; 0.000 ; ; ext_clk25mhz ; 0.323 ; 0.000 ; ; eth0_gtx_clk ; 0.642 ; 0.000 ; ; eth1_gtx_clk ; 0.704 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Recovery Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 2.123 ; 0.000 ; ; eth1_rx_clk ; 2.391 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 4.248 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.008 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 5.047 ; 0.000 ; ; altera_reserved_tck ; 48.544 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Removal Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.833 ; 0.000 ; ; eth1_rx_clk ; 0.834 ; 0.000 ; ; altera_reserved_tck ; 0.981 ; 0.000 ; ; eth0_rx_clk ; 1.214 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 1.320 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 3.890 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Slow 1200mV -40C Model Minimum Pulse Width Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 3.434 ; 0.000 ; ; eth1_rx_clk ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.434 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; 3.754 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; 3.754 ; 0.000 ; ; eth0_gtx_clk ; 3.790 ; 0.000 ; ; eth1_gtx_clk ; 3.790 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 4.662 ; 0.000 ; ; ext_clk25mhz ; 19.553 ; 0.000 ; ; altera_reserved_tck ; 49.477 ; 0.000 ; +---------------------------------------------------+--------+---------------+ ------------------------------------------------ ; Slow 1200mV -40C Model Metastability Summary ; ------------------------------------------------ The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 49 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 9.447 ns +----------------------------------------------------------------------------+ ; Fast 1200mV -40C Model Setup Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 0.454 ; 0.000 ; ; eth1_gtx_clk ; 0.598 ; 0.000 ; ; eth1_rx_clk ; 0.625 ; 0.000 ; ; eth0_gtx_clk ; 0.639 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 5.591 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 5.810 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 6.385 ; 0.000 ; ; ext_clk25mhz ; 39.349 ; 0.000 ; ; altera_reserved_tck ; 47.939 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Fast 1200mV -40C Model Hold Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.097 ; 0.000 ; ; eth1_rx_clk ; 0.101 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.103 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 0.111 ; 0.000 ; ; eth0_rx_clk ; 0.124 ; 0.000 ; ; altera_reserved_tck ; 0.130 ; 0.000 ; ; ext_clk25mhz ; 0.158 ; 0.000 ; ; eth0_gtx_clk ; 0.830 ; 0.000 ; ; eth1_gtx_clk ; 0.846 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Fast 1200mV -40C Model Recovery Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_rx_clk ; 3.488 ; 0.000 ; ; eth1_rx_clk ; 3.567 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 6.024 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 6.470 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 7.413 ; 0.000 ; ; altera_reserved_tck ; 49.625 ; 0.000 ; +---------------------------------------------------+--------+---------------+ +---------------------------------------------------------------------------+ ; Fast 1200mV -40C Model Removal Summary ; +---------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+-------+---------------+ ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.389 ; 0.000 ; ; eth1_rx_clk ; 0.391 ; 0.000 ; ; altera_reserved_tck ; 0.452 ; 0.000 ; ; eth0_rx_clk ; 0.586 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 0.637 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 1.913 ; 0.000 ; +---------------------------------------------------+-------+---------------+ +----------------------------------------------------------------------------+ ; Fast 1200mV -40C Model Minimum Pulse Width Summary ; +---------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------------------------------------------------+--------+---------------+ ; eth0_gtx_clk ; 0.000 ; 0.000 ; ; eth1_gtx_clk ; 0.000 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; 0.000 ; 0.000 ; ; eth0_rx_clk ; 3.259 ; 0.000 ; ; eth1_rx_clk ; 3.267 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 3.731 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.731 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 4.720 ; 0.000 ; ; ext_clk25mhz ; 19.347 ; 0.000 ; ; altera_reserved_tck ; 49.252 ; 0.000 ; +---------------------------------------------------+--------+---------------+ ------------------------------------------------ ; Fast 1200mV -40C Model Metastability Summary ; ------------------------------------------------ The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 49 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 12.965 ns +----------------------------------------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +----------------------------------------------------+--------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +----------------------------------------------------+--------+-------+----------+---------+---------------------+ ; Worst-case Slack ; 0.273 ; 0.097 ; 1.974 ; 0.389 ; 0.000 ; ; altera_reserved_tck ; 44.323 ; 0.130 ; 48.313 ; 0.452 ; 49.252 ; ; eth0_gtx_clk ; 0.445 ; 0.578 ; N/A ; N/A ; 0.000 ; ; eth0_rx_clk ; 0.273 ; 0.124 ; 1.974 ; 0.586 ; 3.259 ; ; eth1_gtx_clk ; 0.375 ; 0.605 ; N/A ; N/A ; 0.000 ; ; eth1_rx_clk ; 0.318 ; 0.101 ; 2.221 ; 0.391 ; 3.267 ; ; ext_clk25mhz ; 38.592 ; 0.158 ; N/A ; N/A ; 19.347 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 1.647 ; 0.097 ; 4.304 ; 1.913 ; 4.658 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 1.911 ; 0.111 ; 3.706 ; 0.637 ; 3.434 ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 3.057 ; 0.103 ; 4.621 ; 0.389 ; 3.434 ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; altera_reserved_tck ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; eth0_gtx_clk ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ; eth0_rx_clk ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; eth1_gtx_clk ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ; eth1_rx_clk ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; ext_clk25mhz ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; +----------------------------------------------------+--------+-------+----------+---------+---------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; eth0_gtx_clk ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_tx_dv ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_tx_d[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_tx_d[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_tx_d[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_tx_d[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth0_rst_n ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_gtx_clk ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_tx_dv ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_tx_d[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_tx_d[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_tx_d[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_tx_d[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eth1_rst_n ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eths_mdc ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; dsp_spi_d1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; dsp_spi_d2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; dsp_spi_d3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; dsp_irq ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; led_n_red ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; led_n_green ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; led_n_yellow ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; eths_mdio ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; dsp_spi_d0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; altera_reserved_tdo ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +---------------------------------------------------------------------------------+ ; Input Transition Times ; +---------------------+-----------------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +---------------------+-----------------------+-----------------+-----------------+ ; eth0_link100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_int_n ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_link100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_int_n ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eths_mdio ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; dsp_spi_d0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ext_clk25mhz ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; sync_mod ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; dsp_spi_sclk ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_clk ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_clk ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; dsp_spi_cs_n ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_d[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_d[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_d[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_d[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth0_rx_dv ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_d[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_d[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_d[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_d[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; eth1_rx_dv ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; altera_reserved_tms ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; altera_reserved_tck ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; altera_reserved_tdi ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_CONFIG_SEL~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_nCONFIG~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_nSTATUS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; +---------------------+-----------------------+-----------------+-----------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv n40c Model) ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; eth0_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; ; eth0_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth0_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.15 V ; 0.246 V ; 0.362 V ; 4.49e-10 s ; 4.53e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.15 V ; 0.246 V ; 0.362 V ; 4.49e-10 s ; 4.53e-10 s ; No ; No ; ; eth0_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth0_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; ; eth0_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth0_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eth1_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eths_mdc ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.15 V ; 0.246 V ; 0.362 V ; 4.49e-10 s ; 4.53e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.15 V ; 0.246 V ; 0.362 V ; 4.49e-10 s ; 4.53e-10 s ; No ; No ; ; dsp_spi_d1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; dsp_spi_d2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; dsp_spi_d3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; dsp_irq ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; led_n_red ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; led_n_green ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; led_n_yellow ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; eths_mdio ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.22 V ; -0.147 V ; 0.246 V ; 0.363 V ; 4.5e-10 s ; 4.53e-10 s ; No ; No ; ; dsp_spi_d0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.168 V ; 0.414 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; ; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; 3.08 V ; 1.63e-08 V ; 3.24 V ; -0.165 V ; 0.415 V ; 0.315 V ; 2.89e-10 s ; 4.38e-10 s ; No ; No ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 100c Model) ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; eth0_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; ; eth0_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth0_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.056 V ; 0.353 V ; 0.29 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.056 V ; 0.353 V ; 0.29 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; ; eth0_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth0_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; ; eth0_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth0_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eth1_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eths_mdc ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.056 V ; 0.353 V ; 0.29 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.056 V ; 0.353 V ; 0.29 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; ; dsp_spi_d1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; dsp_spi_d2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; dsp_spi_d3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; dsp_irq ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; led_n_red ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; led_n_green ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; led_n_yellow ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; eths_mdio ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0564 V ; 0.355 V ; 0.291 V ; 5.23e-10 s ; 6.56e-10 s ; No ; Yes ; ; dsp_spi_d0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0632 V ; 0.27 V ; 0.221 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; ; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; 3.08 V ; 6.72e-06 V ; 3.15 V ; -0.0629 V ; 0.27 V ; 0.22 V ; 4.76e-10 s ; 6.26e-10 s ; Yes ; No ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv n40c Model) ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; eth0_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; ; eth0_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth0_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0357 V ; 0.422 V ; 0.097 V ; 2.82e-10 s ; 4.06e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0357 V ; 0.422 V ; 0.097 V ; 2.82e-10 s ; 4.06e-10 s ; No ; Yes ; ; eth0_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth0_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; ; eth0_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth0_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_gtx_clk ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_tx_dv ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_tx_d[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_tx_d[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_tx_d[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_tx_d[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eth1_rst_n ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eths_mdc ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0357 V ; 0.422 V ; 0.097 V ; 2.82e-10 s ; 4.06e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0357 V ; 0.422 V ; 0.097 V ; 2.82e-10 s ; 4.06e-10 s ; No ; Yes ; ; dsp_spi_d1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; dsp_spi_d2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; dsp_spi_d3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; dsp_irq ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; led_n_red ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; led_n_green ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; led_n_yellow ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; eths_mdio ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.66 V ; -0.0366 V ; 0.421 V ; 0.098 V ; 2.82e-10 s ; 4.07e-10 s ; No ; Yes ; ; dsp_spi_d0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.68 V ; -0.0267 V ; 0.364 V ; 0.059 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; ; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; 3.46 V ; 6.75e-08 V ; 3.67 V ; -0.0271 V ; 0.366 V ; 0.061 V ; 2.67e-10 s ; 3.36e-10 s ; No ; Yes ; +---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup Transfers ; +---------------------------------------------------+---------------------------------------------------+------------+------------+------------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +---------------------------------------------------+---------------------------------------------------+------------+------------+------------+----------+ ; altera_reserved_tck ; altera_reserved_tck ; 1280 ; 0 ; 21 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; eth0_gtx_clk ; 5 ; false path ; false path ; 5 ; ; eth0_rx_clk ; eth0_rx_clk ; 5168 ; 4 ; 0 ; 0 ; ; eth0_rx_clk_virtual ; eth0_rx_clk ; 5 ; false path ; false path ; 4 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth0_rx_clk ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; eth1_gtx_clk ; 5 ; false path ; false path ; 5 ; ; eth1_rx_clk ; eth1_rx_clk ; 5084 ; 4 ; 0 ; 0 ; ; eth1_rx_clk_virtual ; eth1_rx_clk ; 5 ; false path ; false path ; 4 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth1_rx_clk ; false path ; 0 ; 0 ; 0 ; ; ext_clk25mhz ; ext_clk25mhz ; 20 ; 0 ; 0 ; 0 ; ; eth0_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 73239 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 2023 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 2024 ; 0 ; 0 ; 0 ; +---------------------------------------------------+---------------------------------------------------+------------+------------+------------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold Transfers ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+------------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+------------+ ; altera_reserved_tck ; altera_reserved_tck ; 1280 ; 0 ; 21 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; eth0_gtx_clk ; false path ; 5 ; 5 ; false path ; ; eth0_rx_clk ; eth0_rx_clk ; 5168 ; 4 ; 0 ; 0 ; ; eth0_rx_clk_virtual ; eth0_rx_clk ; false path ; 5 ; 4 ; false path ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth0_rx_clk ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; eth1_gtx_clk ; false path ; 5 ; 5 ; false path ; ; eth1_rx_clk ; eth1_rx_clk ; 5084 ; 4 ; 0 ; 0 ; ; eth1_rx_clk_virtual ; eth1_rx_clk ; false path ; 5 ; 4 ; false path ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth1_rx_clk ; false path ; 0 ; 0 ; 0 ; ; ext_clk25mhz ; ext_clk25mhz ; 20 ; 0 ; 0 ; 0 ; ; eth0_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 73239 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 2023 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 2024 ; 0 ; 0 ; 0 ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+------------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-----------------------------------------------------------------------------------------------------------------------------------------------------+ ; Recovery Transfers ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ ; altera_reserved_tck ; altera_reserved_tck ; 47 ; 0 ; 1 ; 0 ; ; eth0_rx_clk ; eth0_rx_clk ; 130 ; 0 ; 4 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth0_rx_clk ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; eth1_rx_clk ; 130 ; 0 ; 4 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth1_rx_clk ; false path ; 0 ; 0 ; 0 ; ; eth0_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 3530 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 216 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 216 ; 0 ; 0 ; 0 ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-----------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removal Transfers ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ ; altera_reserved_tck ; altera_reserved_tck ; 47 ; 0 ; 1 ; 0 ; ; eth0_rx_clk ; eth0_rx_clk ; 130 ; 0 ; 4 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth0_rx_clk ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; eth1_rx_clk ; 130 ; 0 ; 4 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; eth1_rx_clk ; false path ; 0 ; 0 ; 0 ; ; eth0_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; eth1_rx_clk ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; ext_clk25mhz ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; 3530 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; 216 ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; false path ; 0 ; 0 ; 0 ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; 216 ; 0 ; 0 ; 0 ; +---------------------------------------------------+---------------------------------------------------+------------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 0 ; 0 ; ; Unconstrained Input Port Paths ; 0 ; 0 ; ; Unconstrained Output Ports ; 0 ; 0 ; ; Unconstrained Output Port Paths ; 0 ; 0 ; +---------------------------------+-------+------+ +---------------------------------------------------------------------------------------------------------------------------------+ ; Clock Status Summary ; +---------------------------------------------------+---------------------------------------------------+-----------+-------------+ ; Target ; Clock ; Type ; Status ; +---------------------------------------------------+---------------------------------------------------+-----------+-------------+ ; ; eth0_rx_clk_virtual ; Virtual ; Constrained ; ; ; eth1_rx_clk_virtual ; Virtual ; Constrained ; ; altera_reserved_tck ; altera_reserved_tck ; Base ; Constrained ; ; eth0_gtx_clk ; eth0_gtx_clk ; Generated ; Constrained ; ; eth0_rx_clk ; eth0_rx_clk ; Base ; Constrained ; ; eth1_gtx_clk ; eth1_gtx_clk ; Generated ; Constrained ; ; eth1_rx_clk ; eth1_rx_clk ; Base ; Constrained ; ; ext_clk25mhz ; ext_clk25mhz ; Base ; Constrained ; ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; i_pll|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; i_pll|altpll_component|auto_generated|pll1|clk[1] ; Generated ; Constrained ; ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; i_pll|altpll_component|auto_generated|pll1|clk[2] ; Generated ; Constrained ; ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; i_pll|altpll_component|auto_generated|pll1|clk[3] ; Generated ; Constrained ; ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; i_pll|altpll_component|auto_generated|pll1|clk[4] ; Generated ; Constrained ; +---------------------------------------------------+---------------------------------------------------+-----------+-------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition Info: Processing started: Thu Jun 25 16:37:39 2020 Info: Command: quartus_sta top_andromeda -c top_andromeda Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity dcfifo_l3s1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_fd9:dffpipe12|dffe13a* Info (332165): Entity sld_hub Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} Info (332104): Reading SDC File: 'top_andromeda.sdc' Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {i_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name {i_pll|altpll_component|auto_generated|pll1|clk[0]} {i_pll|altpll_component|auto_generated|pll1|clk[0]} Info (332110): create_generated_clock -source {i_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {i_pll|altpll_component|auto_generated|pll1|clk[1]} {i_pll|altpll_component|auto_generated|pll1|clk[1]} Info (332110): create_generated_clock -source {i_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -phase 90.00 -duty_cycle 50.00 -name {i_pll|altpll_component|auto_generated|pll1|clk[2]} {i_pll|altpll_component|auto_generated|pll1|clk[2]} Info (332110): create_generated_clock -source {i_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {i_pll|altpll_component|auto_generated|pll1|clk[3]} {i_pll|altpll_component|auto_generated|pll1|clk[3]} Info (332110): create_generated_clock -source {i_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -phase 90.00 -duty_cycle 50.00 -name {i_pll|altpll_component|auto_generated|pll1|clk[4]} {i_pll|altpll_component|auto_generated|pll1|clk[4]} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: [ALSE SDC CONSTRAINTS] Marvell MDIO Enabled to enable both PHYs Register 20.1 = 1 "add delay" => RGMII Rx Constraints adjusted for that Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: altera_internal_jtag from: tck to: tckutap Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332146): Worst-case setup slack is 0.273 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.273 0.000 eth0_rx_clk Info (332119): 0.318 0.000 eth1_rx_clk Info (332119): 0.375 0.000 eth1_gtx_clk Info (332119): 0.445 0.000 eth0_gtx_clk Info (332119): 1.647 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 1.911 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.057 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 38.592 0.000 ext_clk25mhz Info (332119): 44.323 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.256 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.256 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.258 0.000 eth1_rx_clk Info (332119): 0.294 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 0.300 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 0.338 0.000 eth0_rx_clk Info (332119): 0.348 0.000 altera_reserved_tck Info (332119): 0.378 0.000 ext_clk25mhz Info (332119): 0.578 0.000 eth0_gtx_clk Info (332119): 0.605 0.000 eth1_gtx_clk Info (332146): Worst-case recovery slack is 1.974 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.974 0.000 eth0_rx_clk Info (332119): 2.221 0.000 eth1_rx_clk Info (332119): 3.706 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 4.304 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 4.621 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 48.313 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 0.932 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.932 0.000 eth1_rx_clk Info (332119): 0.932 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 1.091 0.000 altera_reserved_tck Info (332119): 1.399 0.000 eth0_rx_clk Info (332119): 1.557 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 4.512 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 3.434 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.434 0.000 eth0_rx_clk Info (332119): 3.434 0.000 eth1_rx_clk Info (332119): 3.434 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.434 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 3.741 0.000 i_pll|altpll_component|auto_generated|pll1|clk[2] Info (332119): 3.746 0.000 i_pll|altpll_component|auto_generated|pll1|clk[4] Info (332119): 3.790 0.000 eth0_gtx_clk Info (332119): 3.790 0.000 eth1_gtx_clk Info (332119): 4.658 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 19.592 0.000 ext_clk25mhz Info (332119): 49.471 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 49 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 49 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 8.539 ns Info (332114): Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: altera_internal_jtag from: tck to: tckutap Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 0.412 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.412 0.000 eth1_rx_clk Info (332119): 0.469 0.000 eth1_gtx_clk Info (332119): 0.504 0.000 eth0_gtx_clk Info (332119): 0.613 0.000 eth0_rx_clk Info (332119): 2.506 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 2.616 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.619 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 38.787 0.000 ext_clk25mhz Info (332119): 44.857 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.250 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.250 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.255 0.000 eth1_rx_clk Info (332119): 0.283 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 0.288 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 0.296 0.000 eth0_rx_clk Info (332119): 0.298 0.000 altera_reserved_tck Info (332119): 0.323 0.000 ext_clk25mhz Info (332119): 0.642 0.000 eth0_gtx_clk Info (332119): 0.704 0.000 eth1_gtx_clk Info (332146): Worst-case recovery slack is 2.123 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.123 0.000 eth0_rx_clk Info (332119): 2.391 0.000 eth1_rx_clk Info (332119): 4.248 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 5.008 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 5.047 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 48.544 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 0.833 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.833 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 0.834 0.000 eth1_rx_clk Info (332119): 0.981 0.000 altera_reserved_tck Info (332119): 1.214 0.000 eth0_rx_clk Info (332119): 1.320 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.890 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 3.434 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.434 0.000 eth0_rx_clk Info (332119): 3.434 0.000 eth1_rx_clk Info (332119): 3.434 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.434 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 3.754 0.000 i_pll|altpll_component|auto_generated|pll1|clk[2] Info (332119): 3.754 0.000 i_pll|altpll_component|auto_generated|pll1|clk[4] Info (332119): 3.790 0.000 eth0_gtx_clk Info (332119): 3.790 0.000 eth1_gtx_clk Info (332119): 4.662 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 19.553 0.000 ext_clk25mhz Info (332119): 49.477 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 49 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 49 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 9.447 ns Info (332114): Info: Analyzing Fast 1200mV -40C Model Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: altera_internal_jtag from: tck to: tckutap Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 0.454 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.454 0.000 eth0_rx_clk Info (332119): 0.598 0.000 eth1_gtx_clk Info (332119): 0.625 0.000 eth1_rx_clk Info (332119): 0.639 0.000 eth0_gtx_clk Info (332119): 5.591 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 5.810 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 6.385 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 39.349 0.000 ext_clk25mhz Info (332119): 47.939 0.000 altera_reserved_tck Info (332146): Worst-case hold slack is 0.097 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.097 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.101 0.000 eth1_rx_clk Info (332119): 0.103 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 0.111 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 0.124 0.000 eth0_rx_clk Info (332119): 0.130 0.000 altera_reserved_tck Info (332119): 0.158 0.000 ext_clk25mhz Info (332119): 0.830 0.000 eth0_gtx_clk Info (332119): 0.846 0.000 eth1_gtx_clk Info (332146): Worst-case recovery slack is 3.488 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 3.488 0.000 eth0_rx_clk Info (332119): 3.567 0.000 eth1_rx_clk Info (332119): 6.024 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 6.470 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 7.413 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 49.625 0.000 altera_reserved_tck Info (332146): Worst-case removal slack is 0.389 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.389 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 0.391 0.000 eth1_rx_clk Info (332119): 0.452 0.000 altera_reserved_tck Info (332119): 0.586 0.000 eth0_rx_clk Info (332119): 0.637 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 1.913 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 0.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.000 0.000 eth0_gtx_clk Info (332119): 0.000 0.000 eth1_gtx_clk Info (332119): 0.000 0.000 i_pll|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.000 0.000 i_pll|altpll_component|auto_generated|pll1|clk[4] Info (332119): 3.259 0.000 eth0_rx_clk Info (332119): 3.267 0.000 eth1_rx_clk Info (332119): 3.731 0.000 i_pll|altpll_component|auto_generated|pll1|clk[1] Info (332119): 3.731 0.000 i_pll|altpll_component|auto_generated|pll1|clk[3] Info (332119): 4.720 0.000 i_pll|altpll_component|auto_generated|pll1|clk[0] Info (332119): 19.347 0.000 ext_clk25mhz Info (332119): 49.252 0.000 altera_reserved_tck Info (332114): Report Metastability: Found 49 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 49 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 12.965 ns Info (332114): Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning Info: Peak virtual memory: 881 megabytes Info: Processing ended: Thu Jun 25 16:37:47 2020 Info: Elapsed time: 00:00:08 Info: Total CPU time (on all processors): 00:00:08