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What is this?
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This is the readme.txt file for the example design file set of the Altera
LVDS SERDES IP. Files in this directory allow you to do
the following:

1) Create a Quartus Prime project that instantiates an LVDS 
   interface (same configuration as what you specified in generation).
   You can optionally specify the target device and pin location
   assignments, run a full compilation using the Quartus Prime software,
   verify timing closure, and test the interface on your board using the
   programming file generated by the Quartus Prime assembler.
      
2) Create simulation projects for various supported simulators. The
   simulation projects instantiate an LVDS interface (same
   configuration as what you specified in the MegaWizard),
   and an example test bench that exercises the interface.
   The projects are generated so you can run simulation and use the
   results as a way to understand the behavior of the LVDS
   interface IP. This flow only supports functional simulation. Timing
   simulation is not supported, and you must use static timing analysis
   provided by the TimeQuest software to verify timing closure.
      
Notes:
   In external PLL mode, an example external PLL is provided in a
   standalone QSYS file (lvds_external_pll.qsys).
   This can be modified and used in the user's design for external
   PLL mode. 
   In the synthesis example design, there is an example of how to
   connect the external PLL to the LVDS IP including a top-level
   SDC file.
   
   The file under the qsys_interface_bridge directory:
   qsys_interface_bridge_hw.tcl defines a custom component to help
   connect LVDS to the PLL in QSYS. It simply allows the connection
   between non-matching QSYS interfaces (i.e. clock to conduit).
   Make sure these files are added to the project directory if you 
   wish to modify either the synthesis or simulation QSYS systems.
   The qsys_interface_bridge is not needed if using the provided PLL as a
   RTL instantiation and connecting the components manually in RTL 
   rather than a QSYS system.

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Generating a Quartus Prime Example Design
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For information about supported arguments, run:
   quartus_sh -t make_qii_design.tcl -help
   
To generate a Quartus Prime example design, run:
   quartus_sh -t make_qii_design.tcl 
   
To specify an exact device to use, run:   
   quartus_sh -t make_qii_design.tcl -device [device_name]
   
The generated example design is stored under the "qii" sub-directory.
To re-generate the design, simply delete it and re-run the commands above.


To generate non-default example designs like the DPS (Dynamic Phase Shift),
combined TX/RX or others:
    quartus_sh -t make_qii_design.tcl -device [device_name] -system [system_name]

Note: [system_name] is the name of the QSYS system for the given example design.
      For the default "ed_synth.qsys" the system name is "ed_synth".

The generated example design is stored under the "qii_<system_name>" sub-directory.
   
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Generating a Simulation Example Design
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To generate simulation example designs for a Verilog or a mixed-language
simulator, run:

   quartus_sh -t make_sim_design.tcl VERILOG
   
To generate simulation example designs for a VHDL-only simulator, run:

   quartus_sh -t make_sim_design.tcl VHDL
   
The generated example designs for various simulators are stored under the "sim"
sub-directory. For example, to run simulation using Synopsys' VCS, run:

   cd sim/synopsys/vcs
   ./vcs_setup.sh