******************************************************* i++ debug log file This file contains diagnostic information. Any errors or unexpected behavior encountered when running i++ should be reported as bugs. Thank you. ******************************************************* Compiler Command: i++ counter.cpp -v -march=Arria10 -o test-fpga *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** 2020.10.26.16:36:33 Info: Doing: qsys-script --script=count.tcl --quartus-project=none 2020.10.26.16:36:36 Info: create_system count 2020.10.26.16:36:36 Info: set_project_property HIDE_FROM_IP_CATALOG false 2020.10.26.16:36:36 Info: set_project_property DEVICE_FAMILY Arria10 2020.10.26.16:36:36 Info: Info: The device and speed grade is changed to the defaults of the device family, Arria10. 2020.10.26.16:36:36 Info: set_project_property DEVICE 10AX115U1F45I1SG 2020.10.26.16:36:36 Info: add_instance count_internal_inst count_internal 2020.10.26.16:36:37 Info: set_instance_property count_internal_inst AUTO_EXPORT true 2020.10.26.16:36:37 Info: save_system count.ip *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** 2020.10.26.16:36:42 Info: Saving generation log to /mnt/data/intelFPGA_pro/20.2/hls/examples/counter/test-fpga.prj/components/count/count/count_generation.rpt 2020.10.26.16:36:42 Info: Generated by version: 20.2 build 50 2020.10.26.16:36:42 Info: Starting: Create HDL design files for synthesis 2020.10.26.16:36:42 Info: qsys-generate /mnt/data/intelFPGA_pro/20.2/hls/examples/counter/test-fpga.prj/components/count/count.ip --synthesis=VERILOG --output-directory=/mnt/data/intelFPGA_pro/20.2/hls/examples/counter/test-fpga.prj/components/count/count --family="Arria 10" --part=Unknown 2020.10.26.16:36:43 Warning: count_internal_inst: Invalid device name in input file: 10AX115U1F45I1SG 2020.10.26.16:36:43 Error: count: deviceFamily "Arria 10" is out of range: "None", "Unknown" 2020.10.26.16:36:43 Error: qsys-generate failed with exit code 3: 1 Error, 1 Warning 2020.10.26.16:36:43 Info: Finished: Create HDL design files for synthesis 2020.10.26.16:36:43 Info: Starting: IP-XACT 2020.10.26.16:36:43 Info: qsys-generate /mnt/data/intelFPGA_pro/20.2/hls/examples/counter/test-fpga.prj/components/count/count.ip --synthesis=VERILOG --ipxact --output-directory=/mnt/data/intelFPGA_pro/20.2/hls/examples/counter/test-fpga.prj/components/count/count --family="Arria 10" --part=Unknown 2020.10.26.16:36:43 Info: Finished: IP-XACT