aoc: Environment checks are completed successfully. aoc: Hardware generation completed successfully. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Jun 2 20:48:01 2021 Info: Command: quartus_sh -t /home/ml6417/debug/hw/lib/timequest.tcl Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info (23030): Evaluation of Tcl script /home/ml6417/debug/hw/lib/timequest.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1027 megabytes Info: Processing ended: Wed Jun 2 20:48:12 2021 Info: Elapsed time: 00:00:11 Info: Total CPU time (on all processors): 00:00:10 Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Split_Smack: Start STA Analysis: Split_Smack: STA for instrumenting int_add Split_Smack: (STA) Path data acquired for "int_add" Split_Smack: (STA) Path data extracted for "int_add" Split_Smack: 41 potential critical nodes SMACK: Legal nodes verified and DFFEAS instantiations extracted SMACK: 14 legal nodes instrumented SMACK: 0 illegal nodes ignored Split_Smack: "int_add" Netlist file replaced SMACK: All critical paths are legal Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Jun 2 20:49:01 2021 Info: Command: quartus_sh -t /home/ml6417/debug/hw/lib/timequest.tcl Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info (23030): Evaluation of Tcl script /home/ml6417/debug/hw/lib/timequest.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1027 megabytes Info: Processing ended: Wed Jun 2 20:49:10 2021 Info: Elapsed time: 00:00:09 Info: Total CPU time (on all processors): 00:00:09 Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Split_Smack: Start STA Analysis: Split_Smack: STA for instrumenting int_mult Split_Smack: (STA) Path data acquired for "int_mult" Split_Smack: (STA) Path data extracted for "int_mult" Split_Smack: 17 potential critical nodes SMACK: Legal nodes verified and DFFEAS instantiations extracted SMACK: 10 legal nodes instrumented SMACK: 0 illegal nodes ignored Split_Smack: "int_mult" Netlist file replaced SMACK: All critical paths are legal Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Jun 2 20:49:55 2021 Info: Command: quartus_sh --flow recompile top Info: Quartus(args): recompile top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Project Name = /home/ml6417/debug/int_add_mult/int_add_mult/top Info: Revision Name = top Info (293032): Detected changes in source files. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv has changed. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv has changed. Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Warning (292006): Can't contact license server "27004@ee-llic01.ee.ic.ac.uk" -- this server will be ignored. Info (293032): Detected changes in source files. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv has changed. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv has changed. Info (293032): Detected changes in source files. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv has changed. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv has changed. Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:50:31 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top --recompile=on Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Critical Warning (12819): Rapid Recompile may ignore modifying, adding, or deleting SDC files. Info (12845): SDC file was added: /home/ml6417/debug/int_add_mult/int_add_mult/top_guaranteed_timing.sdc. Info (20030): Parallel compilation is enabled and will use 16 of the 20 processors detected Info (12021): Found 2 design units, including 2 entities, in source file top.v Info (12023): Found entity 1: top File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 1 Info (12023): Found entity 2: async_counter_30 File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 207 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/system.v Info (12023): Found entity 1: system File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v Info (12023): Found entity 1: altera_reset_controller File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_reset_controller.v Line: 42 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v Info (12023): Found entity 1: altera_reset_synchronizer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_reset_synchronizer.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_irq_clock_crosser.sv Info (12023): Found entity 1: altera_irq_clock_crosser File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_irq_clock_crosser.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv Info (12023): Found entity 1: system_irq_mapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5.v Info (12023): Found entity 1: system_mm_interconnect_5 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_avalon_st_adapter.v Info (12023): Found entity 1: system_mm_interconnect_5_avalon_st_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_mm_interconnect_5_avalon_st_adapter_error_adapter_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_dc_fifo.v Info (12023): Found entity 1: altera_avalon_dc_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 13 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Info (12023): Found entity 1: altera_dcfifo_synchronizer_bundle File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 8 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_std_synchronizer_nocut.v Info (12023): Found entity 1: altera_std_synchronizer_nocut File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_std_synchronizer_nocut.v Line: 31 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv Info (12023): Found entity 1: altera_merlin_arbitrator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103 Info (12023): Found entity 2: altera_merlin_arb_adder File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_rsp_mux.sv Info (12023): Found entity 1: system_mm_interconnect_5_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_rsp_demux.sv Info (12023): Found entity 1: system_mm_interconnect_5_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_cmd_mux.sv Info (12023): Found entity 1: system_mm_interconnect_5_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_cmd_demux.sv Info (12023): Found entity 1: system_mm_interconnect_5_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_reorder_memory.sv Info (12023): Found entity 1: altera_merlin_reorder_memory File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28 Info (12023): Found entity 2: memory_pointer_controller File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_router_001.sv Info (12023): Found entity 1: system_mm_interconnect_5_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router_001.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_5_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_5_router.sv Info (12023): Found entity 1: system_mm_interconnect_5_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_5_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv Info (12023): Found entity 1: altera_merlin_slave_agent File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv Info (12023): Found entity 1: altera_merlin_master_agent File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_master_agent.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv Info (12023): Found entity 1: altera_merlin_slave_translator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv Info (12023): Found entity 1: altera_merlin_master_translator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_master_translator.sv Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4.v Info (12023): Found entity 1: system_mm_interconnect_4 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_avalon_st_adapter.v Info (12023): Found entity 1: system_mm_interconnect_4_avalon_st_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_mm_interconnect_4_avalon_st_adapter_error_adapter_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_rsp_mux.sv Info (12023): Found entity 1: system_mm_interconnect_4_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_cmd_mux.sv Info (12023): Found entity 1: system_mm_interconnect_4_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_cmd_demux.sv Info (12023): Found entity 1: system_mm_interconnect_4_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_router_001.sv Info (12023): Found entity 1: system_mm_interconnect_4_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router_001.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_4_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_4_router.sv Info (12023): Found entity 1: system_mm_interconnect_4_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_4_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_3.v Info (12023): Found entity 1: system_mm_interconnect_3 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_1.v Info (12023): Found entity 1: system_mm_interconnect_1 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: system_mm_interconnect_0_avalon_st_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_mm_interconnect_0_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_mm_interconnect_0_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_mm_interconnect_0_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_mm_interconnect_0_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_0_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_mm_interconnect_0_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_mm_interconnect_0_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_mm_interconnect_0.v Info (12023): Found entity 1: system_mm_interconnect_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 9 Info (12021): Found 2 design units, including 1 entities, in source file system/synthesis/submodules/smack_ctrl_modify.vhd Info (12022): Found design unit 1: smack_ctrl_modify-rtl File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 38 Info (12023): Found entity 1: smack_ctrl_modify File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 12 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Info (12023): Found entity 1: altera_avalon_mm_clock_crossing_bridge File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 30 Info (12021): Found 3 design units, including 1 entities, in source file system/synthesis/submodules/smack_shadow_circuit.vhd Info (12022): Found design unit 1: dffeas_pack (system) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_shadow_circuit.vhd Line: 6 Info (12022): Found design unit 2: smack_shadow_circuit-rtl File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_shadow_circuit.vhd Line: 83 Info (12023): Found entity 1: smack_shadow_circuit File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_shadow_circuit.vhd Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/int_add.sv Info (12023): Found entity 1: int_add_function_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/int_mult.sv Info (12023): Found entity 1: int_mult_function_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/int_add_mult_system.v Info (12023): Found entity 1: int_add_mult_system File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 4 Info (12023): Found entity 2: int_add_top_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 534 Info (12023): Found entity 3: int_mult_top_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 657 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_data_fifo.v Info (12023): Found entity 1: acl_data_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_data_fifo.v Line: 45 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_fifo.v Info (12023): Found entity 1: acl_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_fifo.v Info (12023): Found entity 1: acl_ll_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ll_fifo.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ll_ram_fifo.v Info (12023): Found entity 1: acl_ll_ram_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ll_ram_fifo.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_valid_fifo_counter.v Info (12023): Found entity 1: acl_valid_fifo_counter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_valid_fifo_counter.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_staging_reg.v Info (12023): Found entity 1: acl_staging_reg File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_staging_reg.v Line: 20 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_top.v Info (12023): Found entity 1: lsu_top File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_top.v Line: 76 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_pipelined.v Info (12023): Found entity 1: lsu_pipelined_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_pipelined.v Line: 37 Info (12023): Found entity 2: lsu_pipelined_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_pipelined.v Line: 416 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_enabled.v Info (12023): Found entity 1: lsu_enabled_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_enabled.v Line: 37 Info (12023): Found entity 2: lsu_enabled_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_enabled.v Line: 178 Info (12021): Found 4 design units, including 4 entities, in source file system/synthesis/submodules/lsu_basic_coalescer.v Info (12023): Found entity 1: lsu_basic_coalesced_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_basic_coalescer.v Line: 37 Info (12023): Found entity 2: lsu_basic_coalesced_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_basic_coalescer.v Line: 223 Info (12023): Found entity 3: lookahead_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_basic_coalescer.v Line: 474 Info (12023): Found entity 4: basic_coalescer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_basic_coalescer.v Line: 535 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_simple.v Info (12023): Found entity 1: lsu_simple_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_simple.v Line: 32 Info (12023): Found entity 2: lsu_simple_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_simple.v Line: 197 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_streaming.v Info (12023): Found entity 1: lsu_streaming_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_streaming.v Line: 35 Info (12023): Found entity 2: lsu_streaming_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_streaming.v Line: 290 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_burst_master.v Info (12023): Found entity 1: lsu_burst_read_master File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_burst_master.v Line: 26 Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/lsu_bursting_load_stores.v Info (12023): Found entity 1: lsu_bursting_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1 Info (12023): Found entity 2: acl_io_pipeline File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 404 Info (12023): Found entity 3: lsu_bursting_pipelined_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 431 Info (12023): Found entity 4: acl_stall_free_coalescer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 935 Info (12023): Found entity 5: lsu_bursting_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1076 Info (12023): Found entity 6: lsu_bursting_write_internal File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1240 Info (12023): Found entity 7: bursting_coalescer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_bursting_load_stores.v Line: 1638 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/lsu_non_aligned_write.v Info (12023): Found entity 1: lsu_non_aligned_write File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_non_aligned_write.v Line: 15 Info (12023): Found entity 2: lsu_non_aligned_write_internal File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_non_aligned_write.v Line: 163 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_read_cache.v Info (12023): Found entity 1: lsu_read_cache File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_read_cache.v Line: 41 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_atomic.v Info (12023): Found entity 1: lsu_atomic_pipelined File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_atomic.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_prefetch_block.v Info (12023): Found entity 1: lsu_prefetch_block File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_prefetch_block.v Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/lsu_wide_wrapper.v Info (12023): Found entity 1: lsu_wide_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_wide_wrapper.v Line: 4 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/lsu_streaming_prefetch.v Info (12023): Found entity 1: lsu_streaming_prefetch_read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 8 Info (12023): Found entity 2: lsu_streaming_prefetch_fifo File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 307 Info (12023): Found entity 3: lsu_streaming_prefetch_avalon_bust_master File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_streaming_prefetch.v Line: 525 Info (12021): Found 6 design units, including 6 entities, in source file system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Info (12023): Found entity 1: acl_aligned_burst_coalesced_lsu File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 61 Info (12023): Found entity 2: avalon_interface File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 306 Info (12023): Found entity 3: valid_generator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 492 Info (12023): Found entity 4: acl_lsu_buffers File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 559 Info (12023): Found entity 5: acl_burst_coalescer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 763 Info (12023): Found entity 6: acl_registered_comparison File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_aligned_burst_coalesced_lsu.v Line: 1182 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_loop_limiter.v Info (12023): Found entity 1: acl_loop_limiter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_loop_limiter.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_group_limiter.v Info (12023): Found entity 1: acl_work_group_limiter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_work_group_limiter.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_accumulator.v Info (12023): Found entity 1: acl_multistage_accumulator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_multistage_accumulator.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_item_iterator.v Info (12023): Found entity 1: acl_work_item_iterator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_work_item_iterator.v Line: 32 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_shift_register.v Info (12023): Found entity 1: acl_shift_register File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_shift_register.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_multistage_adder.v Info (12023): Found entity 1: acl_multistage_adder File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_multistage_adder.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_id_iterator.v Info (12023): Found entity 1: acl_id_iterator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_id_iterator.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_kernel_finish_detector.v Info (12023): Found entity 1: acl_kernel_finish_detector File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_kernel_finish_detector.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_work_group_dispatcher.v Info (12023): Found entity 1: acl_work_group_dispatcher File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_work_group_dispatcher.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_toggle_detect.v Info (12023): Found entity 1: acl_toggle_detect File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_toggle_detect.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_debug_mem.v Info (12023): Found entity 1: acl_debug_mem File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_debug_mem.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_int_mult.v Info (12023): Found entity 1: acl_int_mult File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_int_mult.v Line: 19 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/sv_mult27.v Info (12023): Found entity 1: sv_mult27_mult_add_cfq3 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sv_mult27.v Line: 46 Info (12023): Found entity 2: sv_mult27 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sv_mult27.v Line: 358 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_arb2.v Info (12023): Found entity 1: acl_arb2 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_arb2.v Line: 15 Info (12023): Found entity 2: acl_arb_pipeline_reg File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_arb2.v Line: 286 Info (12023): Found entity 3: acl_arb_staging_reg File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_arb2.v Line: 337 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_arb_intf.v Info (12023): Found entity 1: acl_arb_data File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_arb_intf.v Line: 15 Info (12023): Found entity 2: acl_arb_intf File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_arb_intf.v Line: 36 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_avm_to_ic.v Info (12023): Found entity 1: acl_avm_to_ic File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_avm_to_ic.v Line: 15 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/acl_ic_intf.v Info (12023): Found entity 1: acl_ic_wrp_intf File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_intf.v Line: 15 Info (12023): Found entity 2: acl_ic_rrp_intf File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_intf.v Line: 23 Info (12023): Found entity 3: acl_ic_master_intf File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_intf.v Line: 33 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_master_endpoint.v Info (12023): Found entity 1: acl_ic_master_endpoint File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_master_endpoint.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_endpoint.v Info (12023): Found entity 1: acl_ic_slave_endpoint File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_slave_endpoint.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_rrp.v Info (12023): Found entity 1: acl_ic_slave_rrp File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_slave_rrp.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_slave_wrp.v Info (12023): Found entity 1: acl_ic_slave_wrp File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_slave_wrp.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_rrp_reg.v Info (12023): Found entity 1: acl_ic_rrp_reg File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_rrp_reg.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_wrp_reg.v Info (12023): Found entity 1: acl_ic_wrp_reg File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_wrp_reg.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_ic_to_avm.v Info (12023): Found entity 1: acl_ic_to_avm File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_ic_to_avm.v Line: 15 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/acl_atomics_nostall.v Info (12023): Found entity 1: acl_atomics_nostall File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_atomics_nostall.v Line: 131 Info (12023): Found entity 2: atomic_alu File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_atomics_nostall.v Line: 1008 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/acl_atomics_arb_stall.v Info (12023): Found entity 1: acl_atomics_arb_stall File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/acl_atomics_arb_stall.v Line: 15 Info (12021): Found 11 design units, including 11 entities, in source file system/synthesis/submodules/lsu_ic_top.v Info (12023): Found entity 1: lsu_ic_top File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 4 Info (12023): Found entity 2: lsu_ic_token File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 302 Info (12023): Found entity 3: lsu_n_token File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 464 Info (12023): Found entity 4: lsu_n_fast File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 746 Info (12023): Found entity 5: lsu_ic_hybrid File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1024 Info (12023): Found entity 6: lsu_ic_unbalance File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1205 Info (12023): Found entity 7: lsu_token_ring File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1401 Info (12023): Found entity 8: lsu_swdimm_token_ring File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1996 Info (12023): Found entity 9: lsu_rd_back_n File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2216 Info (12023): Found entity 10: lsu_rd_back File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2432 Info (12023): Found entity 11: debug_io_cnt File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2694 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/cra_ring_root.sv Info (12023): Found entity 1: cra_ring_root File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/cra_ring_root.sv Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/modified_cra_ring.sv Info (12023): Found entity 1: modified_cra_ring File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/modified_cra_ring.sv Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface.v Info (12023): Found entity 1: system_acl_iface File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_irq_mapper_001.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_irq_mapper.sv Info (12023): Found entity 1: system_acl_iface_irq_mapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_irq_mapper.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_7 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv Info (12023): Found entity 1: altera_merlin_width_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv Info (12023): Found entity 1: altera_merlin_address_alignment File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_6_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_6_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_5_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_5_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_5_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv Info (12023): Found entity 1: altera_merlin_burst_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39 Info (12021): Found 5 design units, including 5 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40 Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55 Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77 Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98 Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_incr_burst_converter.sv Info (12023): Found entity 1: altera_incr_burst_converter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_wrap_burst_converter.sv Info (12023): Found entity 1: altera_wrap_burst_converter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_default_burst_converter.sv Info (12023): Found entity 1: altera_default_burst_converter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_default_burst_converter.sv Line: 30 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_4_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_4_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_4_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_axi_master_ni.sv Info (12023): Found entity 1: altera_merlin_axi_master_ni File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_3_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_3_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_3_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_2_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_2_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_001.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_1_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Info (12023): Found entity 1: system_acl_iface_mm_interconnect_1_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_mm_interconnect_1_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_mm_interconnect_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/version_id.v Info (12023): Found entity 1: version_id File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/version_id.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_pll.v Info (12023): Found entity 1: system_acl_iface_pll File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_pll.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_mm_bridge.v Info (12023): Found entity 1: altera_avalon_mm_bridge File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_bridge.v Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface.v Info (12023): Found entity 1: system_acl_iface_kernel_interface File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_handshake_clock_crosser File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 24 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_clock_crosser.v Info (12023): Found entity 1: altera_avalon_st_clock_crosser File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_st_clock_crosser.v Line: 22 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_1_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_kernel_interface_mm_interconnect_0_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/irq_ena.v Info (12023): Found entity 1: irq_ena File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/irq_ena.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_irq_bridge.v Info (12023): Found entity 1: altera_irq_bridge File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_irq_bridge.v Line: 35 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/mem_org_mode.v Info (12023): Found entity 1: mem_org_mode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/mem_org_mode.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sw_reset.v Info (12023): Found entity 1: sw_reset File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sw_reset.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_address_span_extender.sv Info (12023): Found entity 1: altera_address_span_extender File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_address_span_extender.sv Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Info (12023): Found entity 1: system_acl_iface_kernel_interface_sys_description_rom File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps.v Info (12023): Found entity 1: system_acl_iface_hps File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io.v Info (12023): Found entity 1: system_acl_iface_hps_hps_io File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram.v Info (12023): Found entity 1: hps_sdram File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_pll.sv Info (12023): Found entity 1: hps_sdram_pll File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_pll.sv Line: 25 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 29 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset.v Info (12023): Found entity 1: hps_sdram_p0_reset File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_reset_sync.v Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_iss_probe.v Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0.sv Info (12023): Found entity 1: hps_sdram_p0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Info (12023): Found entity 1: system_acl_iface_hps_hps_io_border File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Info (12023): Found entity 1: system_acl_iface_hps_fpga_interfaces File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sv Line: 14 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_rst.sv Info (12023): Found entity 1: altera_mem_if_sequencer_rst File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_rst.sv Line: 18 Info (12021): Found 3 design units, including 3 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Info (12023): Found entity 1: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 34 Info (12023): Found entity 2: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 97 Info (12023): Found entity 3: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 159 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v Info (12023): Found entity 1: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_mgr.sv Info (12023): Found entity 1: sequencer_scc_mgr File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 29 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_siii_wrapper.sv Info (12023): Found entity 1: sequencer_scc_siii_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_siii_wrapper.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_siii_phase_decode.v Info (12023): Found entity 1: sequencer_scc_siii_phase_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_siii_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_sv_wrapper.sv Info (12023): Found entity 1: sequencer_scc_sv_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_sv_wrapper.sv Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_sv_phase_decode.v Info (12023): Found entity 1: sequencer_scc_sv_phase_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_sv_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Info (12023): Found entity 1: sequencer_scc_acv_wrapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_acv_phase_decode.v Info (12023): Found entity 1: sequencer_scc_acv_phase_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_acv_phase_decode.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_scc_reg_file.v Info (12023): Found entity 1: sequencer_scc_reg_file File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/sequencer_reg_file.sv Info (12023): Found entity 1: sequencer_reg_file File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_reg_file.sv Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_simple_avalon_mm_bridge.sv Info (12023): Found entity 1: altera_mem_if_simple_avalon_mm_bridge File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_simple_avalon_mm_bridge.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Info (12023): Found entity 1: altera_mem_if_sequencer_mem_no_ifdef_params File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_irq_mapper.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_irq_mapper File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_irq_mapper.sv Line: 31 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_clock_pair_generator.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_clock_pair_generator File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_clock_pair_generator.v Line: 29 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_memphy File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_ldc.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_ldc File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_ldc.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_acv_hard_io_pads File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_generic_ddio.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_generic_ddio File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_generic_ddio.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_reset File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_reset_sync File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_phy_csr.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_phy_csr File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_phy_csr.sv Line: 31 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_iss_probe.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_iss_probe File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_iss_probe.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 18 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Info (12023): Found entity 1: system_acl_iface_fpga_sdram_p0_altdqdqs File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Info (12023): Found entity 1: system_acl_iface_fpga_sdram_pll0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 23 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Info (12023): Found entity 1: system_acl_iface_acl_memory_bank_divider File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/snoop_adapter.v Info (12023): Found entity 1: snoop_adapter File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/snoop_adapter.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 6 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux.sv Line: 43 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux.sv Line: 51 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux.sv Line: 43 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 84 Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 45 Info (12023): Found entity 2: system_acl_iface_acl_kernel_clk_mm_interconnect_0_router File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 84 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_pll_rom File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 21 Info (12021): Found 6 design units, including 6 entities, in source file system/synthesis/submodules/altera_pll_reconfig_core.v Info (12023): Found entity 1: altera_pll_reconfig_core File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 16 Info (12023): Found entity 2: self_reset File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1679 Info (12023): Found entity 3: dprio_mux File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1727 Info (12023): Found entity 4: fpll_dprio_init File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1777 Info (12023): Found entity 5: dyn_phase_shift File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1872 Info (12023): Found entity 6: generic_lcell_comb File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2100 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_pll_reconfig_top.v Info (12023): Found entity 1: altera_pll_reconfig_top File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_top.v Line: 16 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/pll_lock_avs.v Info (12023): Found entity 1: pll_lock_avs File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/pll_lock_avs.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Info (12023): Found entity 1: system_acl_iface_acl_kernel_clk_kernel_pll File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 2 Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/timer.v Info (12023): Found entity 1: acl_timer File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/timer.v Line: 1 Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for "pll_dr_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_pll.sv Line: 168 Info (12127): Elaborating entity "top" for the top level hierarchy Info (12128): Elaborating entity "system" for hierarchy "system:the_system" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 194 Info (12128): Elaborating entity "system_acl_iface" for hierarchy "system:the_system|system_acl_iface:acl_iface" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 344 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 409 Info (12128): Elaborating entity "acl_timer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|acl_timer:counter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 93 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_avalon_mm_bridge:ctrl" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 127 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_kernel_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 140 Info (12128): Elaborating entity "altera_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 251 Warning (10034): Output port "lvds_clk" at altera_pll.v(320) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 320 Warning (10034): Output port "loaden" at altera_pll.v(321) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 321 Warning (10034): Output port "extclk_out" at altera_pll.v(322) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 322 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 251 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_kernel_pll.v Line: 251 Info (12134): Parameter "fractional_vco_multiplier" = "true" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "pll_fractional_cout" = "24" Info (12134): Parameter "pll_dsm_out_sel" = "1st_order" Info (12134): Parameter "operation_mode" = "direct" Info (12134): Parameter "number_of_clocks" = "5" Info (12134): Parameter "output_clock_frequency0" = "139.999999 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "279.999998 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "279.999997 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "101.818180 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "101.818180 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "Cyclone V" Info (12134): Parameter "pll_subtype" = "Reconfigurable" Info (12134): Parameter "m_cnt_hi_div" = "11" Info (12134): Parameter "m_cnt_lo_div" = "11" Info (12134): Parameter "n_cnt_hi_div" = "256" Info (12134): Parameter "n_cnt_lo_div" = "256" Info (12134): Parameter "m_cnt_bypass_en" = "false" Info (12134): Parameter "n_cnt_bypass_en" = "true" Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false" Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false" Info (12134): Parameter "c_cnt_hi_div0" = "4" Info (12134): Parameter "c_cnt_lo_div0" = "4" Info (12134): Parameter "c_cnt_prst0" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0" Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en0" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false" Info (12134): Parameter "c_cnt_hi_div1" = "2" Info (12134): Parameter "c_cnt_lo_div1" = "2" Info (12134): Parameter "c_cnt_prst1" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0" Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en1" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false" Info (12134): Parameter "c_cnt_hi_div2" = "2" Info (12134): Parameter "c_cnt_lo_div2" = "2" Info (12134): Parameter "c_cnt_prst2" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0" Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en2" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false" Info (12134): Parameter "c_cnt_hi_div3" = "6" Info (12134): Parameter "c_cnt_lo_div3" = "5" Info (12134): Parameter "c_cnt_prst3" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0" Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en3" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "true" Info (12134): Parameter "c_cnt_hi_div4" = "6" Info (12134): Parameter "c_cnt_lo_div4" = "5" Info (12134): Parameter "c_cnt_prst4" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0" Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en4" = "false" Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "true" Info (12134): Parameter "c_cnt_hi_div5" = "1" Info (12134): Parameter "c_cnt_lo_div5" = "1" Info (12134): Parameter "c_cnt_prst5" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0" Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en5" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false" Info (12134): Parameter "c_cnt_hi_div6" = "1" Info (12134): Parameter "c_cnt_lo_div6" = "1" Info (12134): Parameter "c_cnt_prst6" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0" Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en6" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false" Info (12134): Parameter "c_cnt_hi_div7" = "1" Info (12134): Parameter "c_cnt_lo_div7" = "1" Info (12134): Parameter "c_cnt_prst7" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0" Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en7" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false" Info (12134): Parameter "c_cnt_hi_div8" = "1" Info (12134): Parameter "c_cnt_lo_div8" = "1" Info (12134): Parameter "c_cnt_prst8" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0" Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en8" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false" Info (12134): Parameter "c_cnt_hi_div9" = "1" Info (12134): Parameter "c_cnt_lo_div9" = "1" Info (12134): Parameter "c_cnt_prst9" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0" Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en9" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false" Info (12134): Parameter "c_cnt_hi_div10" = "1" Info (12134): Parameter "c_cnt_lo_div10" = "1" Info (12134): Parameter "c_cnt_prst10" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0" Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en10" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false" Info (12134): Parameter "c_cnt_hi_div11" = "1" Info (12134): Parameter "c_cnt_lo_div11" = "1" Info (12134): Parameter "c_cnt_prst11" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0" Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en11" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false" Info (12134): Parameter "c_cnt_hi_div12" = "1" Info (12134): Parameter "c_cnt_lo_div12" = "1" Info (12134): Parameter "c_cnt_prst12" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0" Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en12" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false" Info (12134): Parameter "c_cnt_hi_div13" = "1" Info (12134): Parameter "c_cnt_lo_div13" = "1" Info (12134): Parameter "c_cnt_prst13" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0" Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en13" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false" Info (12134): Parameter "c_cnt_hi_div14" = "1" Info (12134): Parameter "c_cnt_lo_div14" = "1" Info (12134): Parameter "c_cnt_prst14" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0" Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en14" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false" Info (12134): Parameter "c_cnt_hi_div15" = "1" Info (12134): Parameter "c_cnt_lo_div15" = "1" Info (12134): Parameter "c_cnt_prst15" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0" Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en15" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false" Info (12134): Parameter "c_cnt_hi_div16" = "1" Info (12134): Parameter "c_cnt_lo_div16" = "1" Info (12134): Parameter "c_cnt_prst16" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0" Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en16" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false" Info (12134): Parameter "c_cnt_hi_div17" = "1" Info (12134): Parameter "c_cnt_lo_div17" = "1" Info (12134): Parameter "c_cnt_prst17" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0" Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en17" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" Info (12134): Parameter "pll_vco_div" = "1" Info (12134): Parameter "pll_cp_current" = "20" Info (12134): Parameter "pll_bwctrl" = "4000" Info (12134): Parameter "pll_output_clk_frequency" = "1119.999986 MHz" Info (12134): Parameter "pll_fractional_division" = "6710882" Info (12134): Parameter "mimic_fbclk_type" = "none" Info (12134): Parameter "pll_fbclk_mux_1" = "glb" Info (12134): Parameter "pll_fbclk_mux_2" = "m_cnt" Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk" Info (12134): Parameter "pll_slf_rst" = "false" Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 769 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 769 Info (12128): Elaborating entity "dprio_init" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 784 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 784 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1961 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1961 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1972 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1972 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1983 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1983 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1994 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 1994 Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 2005 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 2005 Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 2224 Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(632) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 632 Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(637) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 637 Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(641) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641 Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(642) has no driver File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 642 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 2224 Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1153 Info (12131): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1153 Info (12128): Elaborating entity "pll_lock_avs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|pll_lock_avs:pll_lock_avs_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 151 Info (12128): Elaborating entity "altera_pll_reconfig_top" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 174 Info (12128): Elaborating entity "altera_pll_reconfig_core" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_top.v Line: 415 Warning (10036): Verilog HDL or VHDL warning at altera_pll_reconfig_core.v(206): object "dps_start_assert" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 206 Warning (10270): Verilog HDL Case Statement warning at altera_pll_reconfig_core.v(1498): incomplete case statement has no default case item File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1498 Warning (10270): Verilog HDL Case Statement warning at altera_pll_reconfig_core.v(1514): incomplete case statement has no default case item File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1514 Info (12128): Elaborating entity "dyn_phase_shift" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1565 Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2048 Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2059 Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_2" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2070 Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_3" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2081 Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_4" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 2092 Info (12128): Elaborating entity "self_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|self_reset:self_reset_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1569 Info (12128): Elaborating entity "dprio_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|dprio_mux:dprio_mux_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1607 Info (12128): Elaborating entity "fpll_dprio_init" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_pll_reconfig_top:pll_reconfig_0|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|fpll_dprio_init:fpll_dprio_init_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_pll_reconfig_core.v Line: 1626 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_pll_rom" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 188 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 76 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 76 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v Line: 76 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "pll_rom.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "256" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "8" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fgh1.tdf Info (12023): Found entity 1: altsyncram_fgh1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_fgh1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_fgh1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_pll_rom:pll_rom|altsyncram:the_altsyncram|altsyncram_fgh1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "sw_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|sw_reset:pll_sw_reset" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 203 Info (12128): Elaborating entity "version_id" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|version_id:version_id_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 213 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 260 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:ctrl_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 497 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_reconfig_0_mgmt_avalon_slave_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 561 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 625 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_sw_reset_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 689 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_lock_avs_0_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 753 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pll_rom_s1_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 881 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:ctrl_m0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 962 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pll_reconfig_0_mgmt_avalon_slave_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1046 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pll_reconfig_0_mgmt_avalon_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1087 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pll_rom_s1_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1712 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1728 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router:router|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router.sv Line: 189 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1744 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001:router_001|system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:ctrl_m0_limiter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1874 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1921 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 1938 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 2040 Info (12128): Elaborating entity "system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 2172 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux.sv Line: 374 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "system_mm_interconnect_5_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_5_avalon_st_adapter:avalon_st_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_mm_interconnect_0.v Line: 2201 Info (12128): Elaborating entity "system_mm_interconnect_5_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_5_avalon_st_adapter:avalon_st_adapter|system_mm_interconnect_5_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 323 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_reset_controller.v Line: 208 Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_reset_controller.v Line: 220 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|altera_reset_controller:rst_controller_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 386 Info (12128): Elaborating entity "system_acl_iface_acl_memory_bank_divider" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 438 Info (12128): Elaborating entity "snoop_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Line: 72 Info (12128): Elaborating entity "dcfifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/snoop_adapter.v Line: 108 Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_type" = "dcfifo" Info (12134): Parameter "lpm_width" = "30" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "overflow_checking" = "ON" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_e8n1.tdf Info (12023): Found entity 1: dcfifo_e8n1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 41 Info (12128): Elaborating entity "dcfifo_e8n1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/dcfifo.tdf Line: 191 Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_g9b.tdf Info (12023): Found entity 1: a_gray2bin_g9b File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_gray2bin_g9b.tdf Line: 23 Info (12128): Elaborating entity "a_gray2bin_g9b" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_gray2bin_g9b:rdptr_g_gray2bin" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 55 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_dg6.tdf Info (12023): Found entity 1: a_graycounter_dg6 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_graycounter_dg6.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_dg6" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_graycounter_dg6:rdptr_g1p" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_9ub.tdf Info (12023): Found entity 1: a_graycounter_9ub File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_graycounter_9ub.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_9ub" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|a_graycounter_9ub:wrptr_g1p" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1b81.tdf Info (12023): Found entity 1: altsyncram_1b81 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_1b81" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 59 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1v8.tdf Info (12023): Found entity 1: dffpipe_1v8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dffpipe_1v8.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_1v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|dffpipe_1v8:rs_brp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 66 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_h9l.tdf Info (12023): Found entity 1: alt_synch_pipe_h9l File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_h9l.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_h9l" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_h9l:rs_dgwp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 68 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2v8.tdf Info (12023): Found entity 1: dffpipe_2v8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dffpipe_2v8.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_2v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_h9l:rs_dgwp|dffpipe_2v8:dffpipe13" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_h9l.tdf Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_i9l.tdf Info (12023): Found entity 1: alt_synch_pipe_i9l File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_i9l.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_i9l" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_i9l:ws_dgrp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 69 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3v8.tdf Info (12023): Found entity 1: dffpipe_3v8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dffpipe_3v8.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_3v8" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|alt_synch_pipe_i9l:ws_dgrp|dffpipe_3v8:dffpipe16" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_i9l.tdf Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_1v5.tdf Info (12023): Found entity 1: cmpr_1v5 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cmpr_1v5.tdf Line: 23 Info (12128): Elaborating entity "cmpr_1v5" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|cmpr_1v5:rdempty_eq_comp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_e8n1.tdf Line: 73 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|altera_reset_controller:rst_controller" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_memory_bank_divider.v Line: 135 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_address_span_extender:address_span_extender_axi" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 477 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_address_span_extender:address_span_extender_kernel" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 516 Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 552 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(210): truncated value with size 32 to match size of target (6) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 210 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(213): truncated value with size 32 to match size of target (6) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 213 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 33 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 282 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_axi_fpga|altera_avalon_dc_fifo:rsp_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 588 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(210): truncated value with size 32 to match size of target (7) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 210 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(213): truncated value with size 32 to match size of target (7) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 213 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:cmd_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_clock_crossing_bridge:clock_cross_kernel_mem0|altera_avalon_dc_fifo:rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 282 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 691 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_pll0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 156 Info (10648): Verilog HDL Display System Task info at system_acl_iface_fpga_sdram_pll0.sv(157): Using Regular pll emif simulation models File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_pll0.sv Line: 157 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 281 Info (10648): Verilog HDL Display System Task info at system_acl_iface_fpga_sdram_p0.sv(405): Using Regular core emif simulation models File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 405 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_memphy" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sv Line: 573 Warning (10036): Verilog HDL or VHDL warning at system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v(436): object "seq_calib_init_reg" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 436 Warning (10230): Verilog HDL assignment warning at system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 557 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 487 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_afi_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 87 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_ctl_reset_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 95 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_addr_cmd_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 103 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_reset_sync" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_avl_clk" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset.v Line: 137 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_ldc" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_ldc:memphy_ldc" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 554 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_io_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_memphy.v Line: 780 Warning (10034): Output port "ddio_phy_dqdin[179..140]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[107..104]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[71..68]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Warning (10034): Output port "ddio_phy_dqdin[35..32]" at system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v(192) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 192 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 245 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:uaddress_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 157 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ubank_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 166 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ucmd_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 189 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_generic_ddio:ureset_n_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 198 Info (12128): Elaborating entity "altddio_out" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 317 Info (12134): Parameter "extend_oe_disable" = "UNUSED" Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "invert_output" = "OFF" Info (12134): Parameter "lpm_hint" = "UNUSED" Info (12134): Parameter "lpm_type" = "altddio_out" Info (12134): Parameter "oe_reg" = "UNUSED" Info (12134): Parameter "power_up_high" = "OFF" Info (12134): Parameter "width" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf Info (12023): Found entity 1: ddio_out_uqe File: /home/ml6417/debug/int_add_mult/int_add_mult/db/ddio_out_uqe.tdf Line: 28 Info (12128): Elaborating entity "ddio_out_uqe" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altddio_out.tdf Line: 101 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_clock_pair_generator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|system_acl_iface_fpga_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_p0_altdqdqs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_acv_hard_io_pads.v Line: 317 Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_altdqdqs.v Line: 143 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 303 Info (12128): Elaborating entity "altera_mem_if_sequencer_rst" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_rst:sequencer_rst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 79 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 99 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench:the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 803 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 1266 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 68 Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "maximum_depth" = "0" Info (12134): Parameter "numwords_a" = "32" Info (12134): Parameter "numwords_b" = "32" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "widthad_a" = "5" Info (12134): Parameter "widthad_b" = "5" Info (12134): Parameter "intended_device_family" = "CYCLONEV" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_mri1.tdf Info (12023): Found entity 1: altsyncram_mri1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_mri1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_mri1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a|altsyncram:the_altsyncram|altsyncram_mri1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module:altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v Line: 1288 Info (12128): Elaborating entity "sequencer_scc_mgr" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 140 Info (12128): Elaborating entity "sequencer_scc_reg_file" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 581 Info (12128): Elaborating entity "altdpram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_reg_file.v Line: 59 Info (12134): Parameter "indata_aclr" = "OFF" Info (12134): Parameter "indata_reg" = "INCLOCK" Info (12134): Parameter "intended_device_family" = "Stratix IV" Info (12134): Parameter "lpm_type" = "altdpram" Info (12134): Parameter "outdata_aclr" = "OFF" Info (12134): Parameter "outdata_reg" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "MLAB" Info (12134): Parameter "rdaddress_aclr" = "OFF" Info (12134): Parameter "rdaddress_reg" = "UNREGISTERED" Info (12134): Parameter "rdcontrol_aclr" = "OFF" Info (12134): Parameter "rdcontrol_reg" = "UNREGISTERED" Info (12134): Parameter "width" = "19" Info (12134): Parameter "widthad" = "6" Info (12134): Parameter "width_byteena" = "1" Info (12134): Parameter "wraddress_aclr" = "OFF" Info (12134): Parameter "wraddress_reg" = "INCLOCK" Info (12134): Parameter "wrcontrol_aclr" = "OFF" Info (12134): Parameter "wrcontrol_reg" = "INCLOCK" Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_k3s1.tdf Info (12023): Found entity 1: dpram_k3s1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dpram_k3s1.tdf Line: 30 Info (12128): Elaborating entity "dpram_k3s1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altdpram.tdf Line: 203 Info (12021): Found 1 design units, including 1 entities, in source file db/decode_5la.tdf Info (12023): Found entity 1: decode_5la File: /home/ml6417/debug/int_add_mult/int_add_mult/db/decode_5la.tdf Line: 23 Info (12128): Elaborating entity "decode_5la" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|decode_5la:wr_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dpram_k3s1.tdf Line: 40 Info (12021): Found 1 design units, including 1 entities, in source file db/mux_7hb.tdf Info (12023): Found entity 1: mux_7hb File: /home/ml6417/debug/int_add_mult/int_add_mult/db/mux_7hb.tdf Line: 23 Info (12128): Elaborating entity "mux_7hb" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|mux_7hb:rd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dpram_k3s1.tdf Line: 41 Info (12128): Elaborating entity "sequencer_scc_acv_wrapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_acv_wrapper:sequencer_scc_family_wrapper" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_mgr.sv Line: 680 Info (12128): Elaborating entity "sequencer_scc_acv_phase_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_acv_wrapper:sequencer_scc_family_wrapper|sequencer_scc_acv_phase_decode:sequencer_scc_phase_decode_dqe_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_scc_acv_wrapper.sv Line: 79 Info (12128): Elaborating entity "sequencer_reg_file" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 159 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/sequencer_reg_file.sv Line: 134 Info (12134): Parameter "address_aclr_b" = "CLEAR0" Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "intended_device_family" = "Stratix III" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "operation_mode" = "DUAL_PORT" Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "ram_block_type" = "MLAB" Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" Info (12134): Parameter "numwords_a" = "16" Info (12134): Parameter "numwords_b" = "16" Info (12134): Parameter "widthad_a" = "4" Info (12134): Parameter "widthad_b" = "4" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_b" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "width_byteena_b" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c9v1.tdf Info (12023): Found entity 1: altsyncram_c9v1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_c9v1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_c9v1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_mem_if_simple_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_simple_avalon_mm_bridge:hphy_bridge" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 195 Info (12128): Elaborating entity "altera_mem_if_sequencer_mem_no_ifdef_params" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 215 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv Line: 83 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "3584" Info (12134): Parameter "numwords_a" = "3584" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "32" Info (12134): Parameter "width_byteena_a" = "4" Info (12134): Parameter "widthad_a" = "12" Info (12134): Parameter "init_file" = "system_acl_iface_fpga_sdram_s0_sequencer_mem.hex" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_rbl1.tdf Info (12023): Found entity 1: altsyncram_rbl1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_rbl1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_rbl1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|altera_mem_if_sequencer_mem_no_ifdef_params:sequencer_mem|altsyncram:the_altsyncram|altsyncram_rbl1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 256 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:cpu_inst_data_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 405 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:cpu_inst_instruction_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 465 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:hphy_bridge_s0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 529 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_mem_s1_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 593 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_scc_mgr_inst_avl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 657 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:sequencer_reg_file_inst_avl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 721 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:cpu_inst_data_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 802 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:cpu_inst_instruction_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 883 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:hphy_bridge_s0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 967 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:hphy_bridge_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hphy_bridge_s0_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1008 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1399 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router:router|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router.sv Line: 182 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1415 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001:router_001|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_001.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1431 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002:router_002|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_002.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003:router_003" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1447 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003:router_003|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_router_003.sv Line: 178 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1514 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_demux_001:cmd_demux_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1531 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1548 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1571 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001.sv Line: 331 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_cmd_mux_001:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_demux_001:rsp_demux_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1645 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1714 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux.sv Line: 342 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_rsp_mux_001:rsp_mux_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1731 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0.v Line: 1760 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0:mm_interconnect_0|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_mm_interconnect_0_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_fpga_sdram_s0_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|system_acl_iface_fpga_sdram_s0_irq_mapper:irq_mapper" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0.v Line: 262 Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 859 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (256) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171 Info (12128): Elaborating entity "altera_mem_if_oct_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_oct_cyclonev:oct0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 867 Info (12128): Elaborating entity "altera_mem_if_dll_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|altera_mem_if_dll_cyclonev:dll0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram.v Line: 879 Info (12128): Elaborating entity "system_acl_iface_hps" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 828 Info (12128): Elaborating entity "system_acl_iface_hps_fpga_interfaces" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps.v Line: 260 Info (12128): Elaborating entity "system_acl_iface_hps_hps_io" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps.v Line: 307 Info (12128): Elaborating entity "system_acl_iface_hps_hps_io_border" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 101 Info (12128): Elaborating entity "hps_sdram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 254 Info (12128): Elaborating entity "hps_sdram_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram.v Line: 105 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object "pll_dr_clk" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_pll.sv Line: 168 Warning (10034): Output port "pll_locked" at hps_sdram_pll.sv(91) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_pll.sv Line: 91 Info (12128): Elaborating entity "hps_sdram_p0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram.v Line: 230 Info (10648): Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sv Line: 405 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_memphy" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sv Line: 573 Warning (10858): Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420 Warning (10230): Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 557 Warning (10030): Net "reset_n_seq_clk" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0' File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 420 Warning (10034): Output port "ctl_reset_export_n" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 222 Info (12128): Elaborating entity "hps_sdram_p0_acv_ldc" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 554 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object "phy_clk_dq" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 45 Warning (10036): Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object "phy_clk_dqs_2x" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 47 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_io_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 780 Warning (10034): Output port "ddio_phy_dqdin[179..176]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[143..140]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[107..104]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[71..68]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Warning (10034): Output port "ddio_phy_dqdin[35..32]" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 191 Info (12128): Elaborating entity "hps_sdram_p0_acv_hard_addr_cmd_pads" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 244 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 157 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 166 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 189 Info (12128): Elaborating entity "hps_sdram_p0_generic_ddio" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 198 Info (12128): Elaborating entity "hps_sdram_p0_clock_pair_generator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337 Info (12128): Elaborating entity "hps_sdram_p0_altdqdqs" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 317 Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 146 Info (12128): Elaborating entity "altera_mem_if_hhp_qseq_synth_top" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram.v Line: 238 Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram.v Line: 794 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1168 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1169 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1170 Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1171 Info (12128): Elaborating entity "system_acl_iface_kernel_interface" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 861 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_sys_description_rom" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 129 Info (12128): Elaborating entity "altsyncram" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 76 Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 76 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_sys_description_rom.v Line: 76 Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "init_file" = "sys_description.hex" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "maximum_depth" = "512" Info (12134): Parameter "numwords_a" = "512" Info (12134): Parameter "operation_mode" = "SINGLE_PORT" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "ram_block_type" = "AUTO" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "width_a" = "64" Info (12134): Parameter "width_byteena_a" = "8" Info (12134): Parameter "widthad_a" = "9" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sbi1.tdf Info (12023): Found entity 1: altsyncram_sbi1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_sbi1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_sbi1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_sys_description_rom:sys_description_rom|altsyncram:the_altsyncram|altsyncram_sbi1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_avalon_mm_bridge:kernel_cra" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 163 Info (12128): Elaborating entity "altera_address_span_extender" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_address_span_extender:address_span_extender_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 202 Info (12128): Elaborating entity "sw_reset" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|sw_reset:sw_reset" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 217 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_avalon_mm_bridge:kernel_cntrl" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 251 Info (12128): Elaborating entity "mem_org_mode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mem_org_mode:mem_org_mode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 265 Warning (10230): Verilog HDL assignment warning at mem_org_mode.v(30): truncated value with size 32 to match size of target (2) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/mem_org_mode.v Line: 30 Warning (10230): Verilog HDL assignment warning at mem_org_mode.v(35): truncated value with size 2 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/mem_org_mode.v Line: 35 Info (12128): Elaborating entity "altera_irq_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_irq_bridge:irq_bridge_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 305 Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|altera_reset_controller:reset_controller_sw" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 378 Info (12128): Elaborating entity "irq_ena" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|irq_ena:irq_ena_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 391 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 416 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:address_span_extender_0_expanded_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 190 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:kernel_cra_s0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 254 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:address_span_extender_0_expanded_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 335 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:kernel_cra_s0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 419 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:kernel_cra_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:kernel_cra_s0_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 460 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 476 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_router:router|system_acl_iface_kernel_interface_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0_router.sv Line: 174 Info (12128): Elaborating entity "system_mm_interconnect_4_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_4_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 492 Info (12128): Elaborating entity "system_mm_interconnect_4_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_4_router_001:router_001|system_mm_interconnect_4_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 509 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 526 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_acl_iface_kernel_interface_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 560 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_cmd_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 626 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 954 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:kernel_cra_s0_rsp_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 692 Info (12128): Elaborating entity "system_mm_interconnect_4_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_4_avalon_st_adapter:avalon_st_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_0.v Line: 721 Info (12128): Elaborating entity "system_mm_interconnect_4_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_4_avalon_st_adapter:avalon_st_adapter|system_mm_interconnect_4_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 475 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:kernel_cntrl_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 632 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:address_span_extender_0_windowed_slave_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 696 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:address_span_extender_0_cntl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 760 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:sys_description_rom_s1_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 824 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:sw_reset_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 888 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:mem_org_mode_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 952 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:version_id_0_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1016 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:kernel_cntrl_m0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1161 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_windowed_slave_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1245 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_windowed_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_windowed_slave_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1286 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_windowed_slave_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1327 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_cntl_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1411 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:address_span_extender_0_cntl_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_cntl_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1452 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:address_span_extender_0_cntl_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1493 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:sys_description_rom_s1_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 1618 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2134 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router:router|system_acl_iface_kernel_interface_mm_interconnect_1_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router.sv Line: 190 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2150 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_001:router_001|system_acl_iface_kernel_interface_mm_interconnect_1_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2166 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_router_002:router_002|system_acl_iface_kernel_interface_mm_interconnect_1_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_router_002.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_traffic_limiter:kernel_cntrl_m0_limiter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2296 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2349 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2366 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2485 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_demux_002:rsp_demux_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2519 Info (12128): Elaborating entity "system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2640 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux.sv Line: 390 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_kernel_interface_mm_interconnect_1_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:address_span_extender_0_cntl_cmd_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2706 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_merlin_width_adapter:address_span_extender_0_cntl_rsp_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 2904 Info (12128): Elaborating entity "altera_avalon_st_handshake_clock_crosser" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_st_handshake_clock_crosser:crosser" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface_mm_interconnect_1.v Line: 3070 Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_acl_iface_kernel_interface_mm_interconnect_1:mm_interconnect_1|altera_avalon_st_handshake_clock_crosser:crosser|altera_avalon_st_clock_crosser:clock_xer" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v Line: 149 Info (12128): Elaborating entity "system_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|system_irq_mapper:irq_mapper" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 482 Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_bridge:mm_bridge_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 895 Info (12128): Elaborating entity "system_acl_iface_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 902 Info (12128): Elaborating entity "altera_pll" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (12133): Instantiated megafunction "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_pll.v Line: 85 Info (12134): Parameter "fractional_vco_multiplier" = "false" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "operation_mode" = "normal" Info (12134): Parameter "number_of_clocks" = "1" Info (12134): Parameter "output_clock_frequency0" = "100.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "0 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "0 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "0 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "0 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "General" Info (12134): Parameter "pll_subtype" = "General" Info (12128): Elaborating entity "altera_avalon_mm_bridge" for hierarchy "system:the_system|system_acl_iface:acl_iface|altera_avalon_mm_bridge:prime_avalon_bridge" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 936 Info (12128): Elaborating entity "version_id" for hierarchy "system:the_system|system_acl_iface:acl_iface|version_id:version_id" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 946 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 971 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:acl_memory_bank_divider_bank1_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 104 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_cross_axi_fpga_s0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_0.v Line: 168 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 995 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_translator:address_span_extender_kernel_expanded_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 177 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_translator:hps_f2h_sdram0_data_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 241 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_master_agent:address_span_extender_kernel_expanded_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 322 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:hps_f2h_sdram0_data_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 406 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_merlin_slave_agent:hps_f2h_sdram0_data_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|altera_avalon_sc_fifo:hps_f2h_sdram0_data_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 447 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 463 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_router:router|system_acl_iface_mm_interconnect_1_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 479 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_router_001:router_001|system_acl_iface_mm_interconnect_1_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 496 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 513 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_1_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_acl_iface_mm_interconnect_1_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 547 Info (12128): Elaborating entity "system_mm_interconnect_0_avalon_st_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v Line: 576 Info (12128): Elaborating entity "system_mm_interconnect_0_avalon_st_adapter_error_adapter_0" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_1:mm_interconnect_1|system_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|system_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter.v Line: 200 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1019 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_translator:address_span_extender_axi_expanded_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 192 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_translator:acl_memory_bank_divider_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 256 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_master_agent:address_span_extender_axi_expanded_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 337 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_agent:acl_memory_bank_divider_s_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 421 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_slave_agent:acl_memory_bank_divider_s_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 462 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_avalon_sc_fifo:acl_memory_bank_divider_s_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 503 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 519 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_router:router|system_acl_iface_mm_interconnect_2_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2_router.sv Line: 174 Info (12128): Elaborating entity "system_mm_interconnect_0_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_mm_interconnect_0_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 535 Info (12128): Elaborating entity "system_mm_interconnect_0_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_mm_interconnect_0_router_001:router_001|system_mm_interconnect_0_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 552 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 569 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_2_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|system_acl_iface_mm_interconnect_2_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 603 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_width_adapter:acl_memory_bank_divider_s_cmd_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 669 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_width_adapter:acl_memory_bank_divider_s_cmd_width_adapter|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 954 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_2:mm_interconnect_2|altera_merlin_width_adapter:acl_memory_bank_divider_s_rsp_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v Line: 735 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1070 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:address_span_extender_axi_windowed_slave_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 235 Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_axi_master_ni:hps_h2f_axi_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 363 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_axi_master_ni:hps_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 485 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:address_span_extender_axi_windowed_slave_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 447 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_agent:address_span_extender_axi_windowed_slave_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 488 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_avalon_sc_fifo:address_span_extender_axi_windowed_slave_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 529 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 545 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router:router|system_acl_iface_mm_interconnect_3_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 577 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_router_002:router_002|system_acl_iface_mm_interconnect_3_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3_router_002.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 627 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "altera_merlin_burst_adapter_burstwrap_increment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 979 Info (12128): Elaborating entity "altera_merlin_burst_adapter_min" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 1004 Info (12128): Elaborating entity "altera_merlin_burst_adapter_subtractor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 157 Info (12128): Elaborating entity "altera_merlin_burst_adapter_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|altera_merlin_burst_adapter:address_span_extender_axi_windowed_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 88 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 644 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 684 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 707 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_3_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_3:mm_interconnect_3|system_acl_iface_mm_interconnect_3_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_3.v Line: 724 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1122 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_translator:mm_bridge_0_s0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 236 Info (12128): Elaborating entity "altera_merlin_axi_master_ni" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_axi_master_ni:hps_h2f_lw_axi_master_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 364 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_axi_master_ni:hps_h2f_lw_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 485 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_agent:mm_bridge_0_s0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 448 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_agent:mm_bridge_0_s0_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 489 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_avalon_sc_fifo:mm_bridge_0_s0_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 530 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 546 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router:router|system_acl_iface_mm_interconnect_4_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 578 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_router_002:router_002|system_acl_iface_mm_interconnect_4_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4_router_002.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 628 Info (12128): Elaborating entity "altera_merlin_burst_adapter_13_1" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 181 Info (12128): Elaborating entity "altera_merlin_address_alignment" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|altera_merlin_burst_adapter:mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 778 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 645 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 685 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 708 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_4_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_4:mm_interconnect_4|system_acl_iface_mm_interconnect_4_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_4.v Line: 725 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1159 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_translator:clock_cross_axi_fpga_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 230 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_translator:clock_cross_kernel_mem0_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 290 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_translator:fpga_sdram_avl_0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 354 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_agent:clock_cross_axi_fpga_m0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 435 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_agent:clock_cross_kernel_mem0_m0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 516 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_agent:fpga_sdram_avl_0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 600 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|altera_avalon_sc_fifo:fpga_sdram_avl_0_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 641 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 657 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router:router|system_acl_iface_mm_interconnect_5_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router.sv Line: 174 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 689 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_router_002:router_002|system_acl_iface_mm_interconnect_5_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5_router_002.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 706 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 746 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 769 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_5_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_5:mm_interconnect_5|system_acl_iface_mm_interconnect_5_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_5.v Line: 786 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1211 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_master_translator:mm_bridge_0_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 457 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:address_span_extender_axi_cntl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 521 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:kernel_interface_ctrl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 585 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:acl_kernel_clk_ctrl_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 649 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:version_id_s_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 713 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_translator:prime_avalon_bridge_s0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 777 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_master_agent:mm_bridge_0_m0_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 858 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:address_span_extender_axi_cntl_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 942 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:address_span_extender_axi_cntl_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_avalon_sc_fifo:address_span_extender_axi_cntl_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 983 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:kernel_interface_ctrl_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1067 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_slave_agent:kernel_interface_ctrl_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_avalon_sc_fifo:kernel_interface_ctrl_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1108 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_avalon_sc_fifo:acl_kernel_clk_ctrl_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1233 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1499 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router:router|system_acl_iface_mm_interconnect_6_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router.sv Line: 188 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1515 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_001_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_001:router_001|system_acl_iface_mm_interconnect_6_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_001.sv Line: 173 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_002" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_002:router_002" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1531 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_router_002_default_decode" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_router_002:router_002|system_acl_iface_mm_interconnect_6_router_002_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_router_002.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_traffic_limiter:mm_bridge_0_m0_limiter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1629 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_cmd_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1670 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_cmd_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1687 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_rsp_demux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1772 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_6_rsp_mux" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1881 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6_rsp_mux.sv Line: 358 Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|system_acl_iface_mm_interconnect_6_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 169 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_width_adapter:address_span_extender_axi_cntl_cmd_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 1947 Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 283 Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_6:mm_interconnect_6|altera_merlin_width_adapter:address_span_extender_axi_cntl_rsp_width_adapter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_6.v Line: 2013 Info (12128): Elaborating entity "system_acl_iface_mm_interconnect_7" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1235 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_mm_interconnect_7:mm_interconnect_7|altera_merlin_master_translator:clock_cross_kernel_mem1_m0_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_mm_interconnect_7.v Line: 103 Info (12128): Elaborating entity "system_acl_iface_irq_mapper" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_irq_mapper:irq_mapper" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1242 Info (12128): Elaborating entity "system_acl_iface_irq_mapper_001" for hierarchy "system:the_system|system_acl_iface:acl_iface|system_acl_iface_irq_mapper_001:irq_mapper_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface.v Line: 1248 Info (12128): Elaborating entity "modified_cra_ring" for hierarchy "system:the_system|modified_cra_ring:avs_int_add_cra_cra_ring" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 375 Warning (10230): Verilog HDL assignment warning at modified_cra_ring.sv(8): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/modified_cra_ring.sv Line: 8 Info (12128): Elaborating entity "modified_cra_ring" for hierarchy "system:the_system|modified_cra_ring:avs_int_mult_cra_cra_ring" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 406 Warning (10230): Verilog HDL assignment warning at modified_cra_ring.sv(8): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/modified_cra_ring.sv Line: 8 Info (12128): Elaborating entity "cra_ring_root" for hierarchy "system:the_system|cra_ring_root:cra_root" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 437 Info (12128): Elaborating entity "int_add_mult_system" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 488 Warning (10036): Verilog HDL or VHDL warning at int_add_mult_system.v(114): object "avm_kernel_wr_writeack_from_bridge" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 114 Warning (10034): Output port "avm_memgmem0_port_0_0_rw_enable" at int_add_mult_system.v(42) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 42 Warning (10034): Output port "avm_memgmem0_port_1_0_rw_enable" at int_add_mult_system.v(54) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 54 Info (12128): Elaborating entity "int_add_top_wrapper" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 184 Info (12128): Elaborating entity "int_add_function_wrapper" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 649 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(127): object "local_router_hang~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 127 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(128): object "avs_cra_enable~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 128 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(129): object "avm_local_bb1_ld__inst0_writeack~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 129 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(130): object "avm_local_bb1_ld__u0_inst0_writeack~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 130 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(131): object "avm_local_bb1_st_add_inst0_readdata[0]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 131 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(132): object "avm_local_bb1_st_add_inst0_readdata[1]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 132 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(133): object "avm_local_bb1_st_add_inst0_readdata[2]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 133 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(134): object "avm_local_bb1_st_add_inst0_readdata[3]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 134 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(135): object "avm_local_bb1_st_add_inst0_readdata[4]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 135 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(136): object "avm_local_bb1_st_add_inst0_readdata[5]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 136 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(137): object "avm_local_bb1_st_add_inst0_readdata[6]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 137 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(138): object "avm_local_bb1_st_add_inst0_readdata[7]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 138 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(139): object "avm_local_bb1_st_add_inst0_readdata[8]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 139 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(140): object "avm_local_bb1_st_add_inst0_readdata[9]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 140 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(141): object "avm_local_bb1_st_add_inst0_readdata[10]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 141 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(142): object "avm_local_bb1_st_add_inst0_readdata[11]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 142 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(143): object "avm_local_bb1_st_add_inst0_readdata[12]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 143 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(144): object "avm_local_bb1_st_add_inst0_readdata[13]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 144 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(145): object "avm_local_bb1_st_add_inst0_readdata[14]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 145 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(146): object "avm_local_bb1_st_add_inst0_readdata[15]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 146 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(147): object "avm_local_bb1_st_add_inst0_readdata[16]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 147 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(148): object "avm_local_bb1_st_add_inst0_readdata[17]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 148 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(149): object "avm_local_bb1_st_add_inst0_readdata[18]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 149 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(150): object "avm_local_bb1_st_add_inst0_readdata[19]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 150 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(151): object "avm_local_bb1_st_add_inst0_readdata[20]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 151 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(152): object "avm_local_bb1_st_add_inst0_readdata[21]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 152 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(153): object "avm_local_bb1_st_add_inst0_readdata[22]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 153 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(154): object "avm_local_bb1_st_add_inst0_readdata[23]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 154 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(155): object "avm_local_bb1_st_add_inst0_readdata[24]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 155 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(156): object "avm_local_bb1_st_add_inst0_readdata[25]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 156 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(157): object "avm_local_bb1_st_add_inst0_readdata[26]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 157 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(158): object "avm_local_bb1_st_add_inst0_readdata[27]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 158 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(159): object "avm_local_bb1_st_add_inst0_readdata[28]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 159 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(160): object "avm_local_bb1_st_add_inst0_readdata[29]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 160 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(161): object "avm_local_bb1_st_add_inst0_readdata[30]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 161 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(162): object "avm_local_bb1_st_add_inst0_readdata[31]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 162 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(163): object "avm_local_bb1_st_add_inst0_readdata[32]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 163 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(164): object "avm_local_bb1_st_add_inst0_readdata[33]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 164 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(165): object "avm_local_bb1_st_add_inst0_readdata[34]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 165 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(166): object "avm_local_bb1_st_add_inst0_readdata[35]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 166 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(167): object "avm_local_bb1_st_add_inst0_readdata[36]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 167 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(168): object "avm_local_bb1_st_add_inst0_readdata[37]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 168 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(169): object "avm_local_bb1_st_add_inst0_readdata[38]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 169 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(170): object "avm_local_bb1_st_add_inst0_readdata[39]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 170 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(171): object "avm_local_bb1_st_add_inst0_readdata[40]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 171 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(172): object "avm_local_bb1_st_add_inst0_readdata[41]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 172 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(173): object "avm_local_bb1_st_add_inst0_readdata[42]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 173 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(174): object "avm_local_bb1_st_add_inst0_readdata[43]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 174 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(175): object "avm_local_bb1_st_add_inst0_readdata[44]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 175 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(176): object "avm_local_bb1_st_add_inst0_readdata[45]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 176 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(177): object "avm_local_bb1_st_add_inst0_readdata[46]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 177 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(178): object "avm_local_bb1_st_add_inst0_readdata[47]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 178 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(179): object "avm_local_bb1_st_add_inst0_readdata[48]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 179 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(180): object "avm_local_bb1_st_add_inst0_readdata[49]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 180 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(181): object "avm_local_bb1_st_add_inst0_readdata[50]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 181 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(182): object "avm_local_bb1_st_add_inst0_readdata[51]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 182 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(183): object "avm_local_bb1_st_add_inst0_readdata[52]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 183 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(184): object "avm_local_bb1_st_add_inst0_readdata[53]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 184 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(185): object "avm_local_bb1_st_add_inst0_readdata[54]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 185 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(186): object "avm_local_bb1_st_add_inst0_readdata[55]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 186 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(187): object "avm_local_bb1_st_add_inst0_readdata[56]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 187 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(188): object "avm_local_bb1_st_add_inst0_readdata[57]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 188 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(189): object "avm_local_bb1_st_add_inst0_readdata[58]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 189 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(190): object "avm_local_bb1_st_add_inst0_readdata[59]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 190 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(191): object "avm_local_bb1_st_add_inst0_readdata[60]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 191 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(192): object "avm_local_bb1_st_add_inst0_readdata[61]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 192 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(193): object "avm_local_bb1_st_add_inst0_readdata[62]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 193 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(194): object "avm_local_bb1_st_add_inst0_readdata[63]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 194 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(195): object "avm_local_bb1_st_add_inst0_readdata[64]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 195 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(196): object "avm_local_bb1_st_add_inst0_readdata[65]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 196 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(197): object "avm_local_bb1_st_add_inst0_readdata[66]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 197 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(198): object "avm_local_bb1_st_add_inst0_readdata[67]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 198 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(199): object "avm_local_bb1_st_add_inst0_readdata[68]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 199 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(200): object "avm_local_bb1_st_add_inst0_readdata[69]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 200 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(201): object "avm_local_bb1_st_add_inst0_readdata[70]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 201 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(202): object "avm_local_bb1_st_add_inst0_readdata[71]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 202 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(203): object "avm_local_bb1_st_add_inst0_readdata[72]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 203 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(204): object "avm_local_bb1_st_add_inst0_readdata[73]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 204 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(205): object "avm_local_bb1_st_add_inst0_readdata[74]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 205 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(206): object "avm_local_bb1_st_add_inst0_readdata[75]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 206 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(207): object "avm_local_bb1_st_add_inst0_readdata[76]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 207 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(208): object "avm_local_bb1_st_add_inst0_readdata[77]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 208 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(209): object "avm_local_bb1_st_add_inst0_readdata[78]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 209 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(210): object "avm_local_bb1_st_add_inst0_readdata[79]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 210 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(211): object "avm_local_bb1_st_add_inst0_readdata[80]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 211 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(212): object "avm_local_bb1_st_add_inst0_readdata[81]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 212 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(213): object "avm_local_bb1_st_add_inst0_readdata[82]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 213 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(214): object "avm_local_bb1_st_add_inst0_readdata[83]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 214 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(215): object "avm_local_bb1_st_add_inst0_readdata[84]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 215 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(216): object "avm_local_bb1_st_add_inst0_readdata[85]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 216 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(217): object "avm_local_bb1_st_add_inst0_readdata[86]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 217 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(218): object "avm_local_bb1_st_add_inst0_readdata[87]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 218 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(219): object "avm_local_bb1_st_add_inst0_readdata[88]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 219 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(220): object "avm_local_bb1_st_add_inst0_readdata[89]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 220 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(221): object "avm_local_bb1_st_add_inst0_readdata[90]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 221 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(222): object "avm_local_bb1_st_add_inst0_readdata[91]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 222 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(223): object "avm_local_bb1_st_add_inst0_readdata[92]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 223 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(224): object "avm_local_bb1_st_add_inst0_readdata[93]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 224 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(225): object "avm_local_bb1_st_add_inst0_readdata[94]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 225 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(226): object "avm_local_bb1_st_add_inst0_readdata[95]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 226 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(227): object "avm_local_bb1_st_add_inst0_readdata[96]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 227 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(228): object "avm_local_bb1_st_add_inst0_readdata[97]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 228 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(229): object "avm_local_bb1_st_add_inst0_readdata[98]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 229 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(230): object "avm_local_bb1_st_add_inst0_readdata[99]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 230 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(231): object "avm_local_bb1_st_add_inst0_readdata[100]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 231 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(232): object "avm_local_bb1_st_add_inst0_readdata[101]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 232 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(233): object "avm_local_bb1_st_add_inst0_readdata[102]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 233 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(234): object "avm_local_bb1_st_add_inst0_readdata[103]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 234 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(235): object "avm_local_bb1_st_add_inst0_readdata[104]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 235 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(236): object "avm_local_bb1_st_add_inst0_readdata[105]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 236 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(237): object "avm_local_bb1_st_add_inst0_readdata[106]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 237 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(238): object "avm_local_bb1_st_add_inst0_readdata[107]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 238 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(239): object "avm_local_bb1_st_add_inst0_readdata[108]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 239 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(240): object "avm_local_bb1_st_add_inst0_readdata[109]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 240 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(241): object "avm_local_bb1_st_add_inst0_readdata[110]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 241 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(242): object "avm_local_bb1_st_add_inst0_readdata[111]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 242 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(243): object "avm_local_bb1_st_add_inst0_readdata[112]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 243 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(244): object "avm_local_bb1_st_add_inst0_readdata[113]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 244 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(245): object "avm_local_bb1_st_add_inst0_readdata[114]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 245 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(246): object "avm_local_bb1_st_add_inst0_readdata[115]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 246 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(247): object "avm_local_bb1_st_add_inst0_readdata[116]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 247 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(248): object "avm_local_bb1_st_add_inst0_readdata[117]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 248 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(249): object "avm_local_bb1_st_add_inst0_readdata[118]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 249 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(250): object "avm_local_bb1_st_add_inst0_readdata[119]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 250 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(251): object "avm_local_bb1_st_add_inst0_readdata[120]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 251 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(252): object "avm_local_bb1_st_add_inst0_readdata[121]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 252 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(253): object "avm_local_bb1_st_add_inst0_readdata[122]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 253 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(254): object "avm_local_bb1_st_add_inst0_readdata[123]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 254 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(255): object "avm_local_bb1_st_add_inst0_readdata[124]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 255 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(256): object "avm_local_bb1_st_add_inst0_readdata[125]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 256 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(257): object "avm_local_bb1_st_add_inst0_readdata[126]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 257 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(258): object "avm_local_bb1_st_add_inst0_readdata[127]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 258 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(259): object "avm_local_bb1_st_add_inst0_readdata[128]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 259 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(260): object "avm_local_bb1_st_add_inst0_readdata[129]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 260 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(261): object "avm_local_bb1_st_add_inst0_readdata[130]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 261 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(262): object "avm_local_bb1_st_add_inst0_readdata[131]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 262 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(263): object "avm_local_bb1_st_add_inst0_readdata[132]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 263 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(264): object "avm_local_bb1_st_add_inst0_readdata[133]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 264 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(265): object "avm_local_bb1_st_add_inst0_readdata[134]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 265 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(266): object "avm_local_bb1_st_add_inst0_readdata[135]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 266 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(267): object "avm_local_bb1_st_add_inst0_readdata[136]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 267 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(268): object "avm_local_bb1_st_add_inst0_readdata[137]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 268 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(269): object "avm_local_bb1_st_add_inst0_readdata[138]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 269 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(270): object "avm_local_bb1_st_add_inst0_readdata[139]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 270 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(271): object "avm_local_bb1_st_add_inst0_readdata[140]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 271 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(272): object "avm_local_bb1_st_add_inst0_readdata[141]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 272 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(273): object "avm_local_bb1_st_add_inst0_readdata[142]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 273 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(274): object "avm_local_bb1_st_add_inst0_readdata[143]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 274 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(275): object "avm_local_bb1_st_add_inst0_readdata[144]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 275 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(276): object "avm_local_bb1_st_add_inst0_readdata[145]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 276 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(277): object "avm_local_bb1_st_add_inst0_readdata[146]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 277 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(278): object "avm_local_bb1_st_add_inst0_readdata[147]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 278 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(279): object "avm_local_bb1_st_add_inst0_readdata[148]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 279 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(280): object "avm_local_bb1_st_add_inst0_readdata[149]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 280 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(281): object "avm_local_bb1_st_add_inst0_readdata[150]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 281 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(282): object "avm_local_bb1_st_add_inst0_readdata[151]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 282 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(283): object "avm_local_bb1_st_add_inst0_readdata[152]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 283 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(284): object "avm_local_bb1_st_add_inst0_readdata[153]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 284 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(285): object "avm_local_bb1_st_add_inst0_readdata[154]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 285 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(286): object "avm_local_bb1_st_add_inst0_readdata[155]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 286 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(287): object "avm_local_bb1_st_add_inst0_readdata[156]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 287 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(288): object "avm_local_bb1_st_add_inst0_readdata[157]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 288 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(289): object "avm_local_bb1_st_add_inst0_readdata[158]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 289 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(290): object "avm_local_bb1_st_add_inst0_readdata[159]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 290 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(291): object "avm_local_bb1_st_add_inst0_readdata[160]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 291 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(292): object "avm_local_bb1_st_add_inst0_readdata[161]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 292 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(293): object "avm_local_bb1_st_add_inst0_readdata[162]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 293 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(294): object "avm_local_bb1_st_add_inst0_readdata[163]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 294 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(295): object "avm_local_bb1_st_add_inst0_readdata[164]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 295 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(296): object "avm_local_bb1_st_add_inst0_readdata[165]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 296 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(297): object "avm_local_bb1_st_add_inst0_readdata[166]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 297 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(298): object "avm_local_bb1_st_add_inst0_readdata[167]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 298 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(299): object "avm_local_bb1_st_add_inst0_readdata[168]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 299 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(300): object "avm_local_bb1_st_add_inst0_readdata[169]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 300 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(301): object "avm_local_bb1_st_add_inst0_readdata[170]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 301 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(302): object "avm_local_bb1_st_add_inst0_readdata[171]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 302 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(303): object "avm_local_bb1_st_add_inst0_readdata[172]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 303 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(304): object "avm_local_bb1_st_add_inst0_readdata[173]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 304 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(305): object "avm_local_bb1_st_add_inst0_readdata[174]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 305 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(306): object "avm_local_bb1_st_add_inst0_readdata[175]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 306 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(307): object "avm_local_bb1_st_add_inst0_readdata[176]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 307 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(308): object "avm_local_bb1_st_add_inst0_readdata[177]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 308 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(309): object "avm_local_bb1_st_add_inst0_readdata[178]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 309 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(310): object "avm_local_bb1_st_add_inst0_readdata[179]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 310 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(311): object "avm_local_bb1_st_add_inst0_readdata[180]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 311 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(312): object "avm_local_bb1_st_add_inst0_readdata[181]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 312 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(313): object "avm_local_bb1_st_add_inst0_readdata[182]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 313 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(314): object "avm_local_bb1_st_add_inst0_readdata[183]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 314 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(315): object "avm_local_bb1_st_add_inst0_readdata[184]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 315 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(316): object "avm_local_bb1_st_add_inst0_readdata[185]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 316 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(317): object "avm_local_bb1_st_add_inst0_readdata[186]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 317 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(318): object "avm_local_bb1_st_add_inst0_readdata[187]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 318 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(319): object "avm_local_bb1_st_add_inst0_readdata[188]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 319 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(320): object "avm_local_bb1_st_add_inst0_readdata[189]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 320 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(321): object "avm_local_bb1_st_add_inst0_readdata[190]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 321 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(322): object "avm_local_bb1_st_add_inst0_readdata[191]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 322 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(323): object "avm_local_bb1_st_add_inst0_readdata[192]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 323 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(324): object "avm_local_bb1_st_add_inst0_readdata[193]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 324 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(325): object "avm_local_bb1_st_add_inst0_readdata[194]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 325 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(326): object "avm_local_bb1_st_add_inst0_readdata[195]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 326 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(327): object "avm_local_bb1_st_add_inst0_readdata[196]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 327 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(328): object "avm_local_bb1_st_add_inst0_readdata[197]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 328 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(329): object "avm_local_bb1_st_add_inst0_readdata[198]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 329 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(330): object "avm_local_bb1_st_add_inst0_readdata[199]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 330 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(331): object "avm_local_bb1_st_add_inst0_readdata[200]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 331 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(332): object "avm_local_bb1_st_add_inst0_readdata[201]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 332 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(333): object "avm_local_bb1_st_add_inst0_readdata[202]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 333 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(334): object "avm_local_bb1_st_add_inst0_readdata[203]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 334 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(335): object "avm_local_bb1_st_add_inst0_readdata[204]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 335 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(336): object "avm_local_bb1_st_add_inst0_readdata[205]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 336 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(337): object "avm_local_bb1_st_add_inst0_readdata[206]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 337 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(338): object "avm_local_bb1_st_add_inst0_readdata[207]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 338 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(339): object "avm_local_bb1_st_add_inst0_readdata[208]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 339 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(340): object "avm_local_bb1_st_add_inst0_readdata[209]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 340 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(341): object "avm_local_bb1_st_add_inst0_readdata[210]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 341 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(342): object "avm_local_bb1_st_add_inst0_readdata[211]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 342 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(343): object "avm_local_bb1_st_add_inst0_readdata[212]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 343 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(344): object "avm_local_bb1_st_add_inst0_readdata[213]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 344 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(345): object "avm_local_bb1_st_add_inst0_readdata[214]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 345 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(346): object "avm_local_bb1_st_add_inst0_readdata[215]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 346 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(347): object "avm_local_bb1_st_add_inst0_readdata[216]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 347 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(348): object "avm_local_bb1_st_add_inst0_readdata[217]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 348 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(349): object "avm_local_bb1_st_add_inst0_readdata[218]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 349 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(350): object "avm_local_bb1_st_add_inst0_readdata[219]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 350 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(351): object "avm_local_bb1_st_add_inst0_readdata[220]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 351 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(352): object "avm_local_bb1_st_add_inst0_readdata[221]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 352 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(353): object "avm_local_bb1_st_add_inst0_readdata[222]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 353 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(354): object "avm_local_bb1_st_add_inst0_readdata[223]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 354 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(355): object "avm_local_bb1_st_add_inst0_readdata[224]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 355 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(356): object "avm_local_bb1_st_add_inst0_readdata[225]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 356 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(357): object "avm_local_bb1_st_add_inst0_readdata[226]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 357 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(358): object "avm_local_bb1_st_add_inst0_readdata[227]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 358 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(359): object "avm_local_bb1_st_add_inst0_readdata[228]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 359 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(360): object "avm_local_bb1_st_add_inst0_readdata[229]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 360 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(361): object "avm_local_bb1_st_add_inst0_readdata[230]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 361 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(362): object "avm_local_bb1_st_add_inst0_readdata[231]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 362 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(363): object "avm_local_bb1_st_add_inst0_readdata[232]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 363 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(364): object "avm_local_bb1_st_add_inst0_readdata[233]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 364 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(365): object "avm_local_bb1_st_add_inst0_readdata[234]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 365 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(366): object "avm_local_bb1_st_add_inst0_readdata[235]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 366 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(367): object "avm_local_bb1_st_add_inst0_readdata[236]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 367 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(368): object "avm_local_bb1_st_add_inst0_readdata[237]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 368 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(369): object "avm_local_bb1_st_add_inst0_readdata[238]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 369 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(370): object "avm_local_bb1_st_add_inst0_readdata[239]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 370 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(371): object "avm_local_bb1_st_add_inst0_readdata[240]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 371 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(372): object "avm_local_bb1_st_add_inst0_readdata[241]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 372 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(373): object "avm_local_bb1_st_add_inst0_readdata[242]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 373 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(374): object "avm_local_bb1_st_add_inst0_readdata[243]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 374 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(375): object "avm_local_bb1_st_add_inst0_readdata[244]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 375 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(376): object "avm_local_bb1_st_add_inst0_readdata[245]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 376 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(377): object "avm_local_bb1_st_add_inst0_readdata[246]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 377 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(378): object "avm_local_bb1_st_add_inst0_readdata[247]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 378 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(379): object "avm_local_bb1_st_add_inst0_readdata[248]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 379 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(380): object "avm_local_bb1_st_add_inst0_readdata[249]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 380 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(381): object "avm_local_bb1_st_add_inst0_readdata[250]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 381 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(382): object "avm_local_bb1_st_add_inst0_readdata[251]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 382 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(383): object "avm_local_bb1_st_add_inst0_readdata[252]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 383 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(384): object "avm_local_bb1_st_add_inst0_readdata[253]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 384 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(385): object "avm_local_bb1_st_add_inst0_readdata[254]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 385 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(386): object "avm_local_bb1_st_add_inst0_readdata[255]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 386 Warning (10036): Verilog HDL or VHDL warning at int_add.sv(387): object "avm_local_bb1_st_add_inst0_readdatavalid~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 387 Info (12128): Elaborating entity "smack_shadow_circuit" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|smack_shadow_circuit:ssc0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 149901 Info (12128): Elaborating entity "int_mult_top_wrapper" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 242 Info (12128): Elaborating entity "int_mult_function_wrapper" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 772 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(209): object "local_router_hang~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 209 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(210): object "avs_cra_enable~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 210 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(211): object "avm_local_bb1_ld__inst0_writeack~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 211 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(212): object "avm_local_bb1_ld__u0_inst0_writeack~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 212 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(213): object "avm_local_bb1_st_mul_inst0_readdata[0]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 213 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(214): object "avm_local_bb1_st_mul_inst0_readdata[1]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 214 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(215): object "avm_local_bb1_st_mul_inst0_readdata[2]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 215 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(216): object "avm_local_bb1_st_mul_inst0_readdata[3]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 216 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(217): object "avm_local_bb1_st_mul_inst0_readdata[4]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 217 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(218): object "avm_local_bb1_st_mul_inst0_readdata[5]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 218 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(219): object "avm_local_bb1_st_mul_inst0_readdata[6]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 219 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(220): object "avm_local_bb1_st_mul_inst0_readdata[7]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 220 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(221): object "avm_local_bb1_st_mul_inst0_readdata[8]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 221 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(222): object "avm_local_bb1_st_mul_inst0_readdata[9]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 222 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(223): object "avm_local_bb1_st_mul_inst0_readdata[10]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 223 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(224): object "avm_local_bb1_st_mul_inst0_readdata[11]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 224 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(225): object "avm_local_bb1_st_mul_inst0_readdata[12]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 225 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(226): object "avm_local_bb1_st_mul_inst0_readdata[13]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 226 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(227): object "avm_local_bb1_st_mul_inst0_readdata[14]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 227 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(228): object "avm_local_bb1_st_mul_inst0_readdata[15]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 228 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(229): object "avm_local_bb1_st_mul_inst0_readdata[16]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 229 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(230): object "avm_local_bb1_st_mul_inst0_readdata[17]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 230 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(231): object "avm_local_bb1_st_mul_inst0_readdata[18]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 231 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(232): object "avm_local_bb1_st_mul_inst0_readdata[19]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 232 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(233): object "avm_local_bb1_st_mul_inst0_readdata[20]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 233 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(234): object "avm_local_bb1_st_mul_inst0_readdata[21]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 234 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(235): object "avm_local_bb1_st_mul_inst0_readdata[22]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 235 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(236): object "avm_local_bb1_st_mul_inst0_readdata[23]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 236 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(237): object "avm_local_bb1_st_mul_inst0_readdata[24]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 237 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(238): object "avm_local_bb1_st_mul_inst0_readdata[25]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 238 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(239): object "avm_local_bb1_st_mul_inst0_readdata[26]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 239 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(240): object "avm_local_bb1_st_mul_inst0_readdata[27]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 240 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(241): object "avm_local_bb1_st_mul_inst0_readdata[28]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 241 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(242): object "avm_local_bb1_st_mul_inst0_readdata[29]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 242 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(243): object "avm_local_bb1_st_mul_inst0_readdata[30]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 243 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(244): object "avm_local_bb1_st_mul_inst0_readdata[31]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 244 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(245): object "avm_local_bb1_st_mul_inst0_readdata[32]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 245 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(246): object "avm_local_bb1_st_mul_inst0_readdata[33]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 246 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(247): object "avm_local_bb1_st_mul_inst0_readdata[34]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 247 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(248): object "avm_local_bb1_st_mul_inst0_readdata[35]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 248 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(249): object "avm_local_bb1_st_mul_inst0_readdata[36]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 249 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(250): object "avm_local_bb1_st_mul_inst0_readdata[37]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 250 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(251): object "avm_local_bb1_st_mul_inst0_readdata[38]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 251 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(252): object "avm_local_bb1_st_mul_inst0_readdata[39]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 252 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(253): object "avm_local_bb1_st_mul_inst0_readdata[40]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 253 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(254): object "avm_local_bb1_st_mul_inst0_readdata[41]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 254 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(255): object "avm_local_bb1_st_mul_inst0_readdata[42]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 255 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(256): object "avm_local_bb1_st_mul_inst0_readdata[43]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 256 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(257): object "avm_local_bb1_st_mul_inst0_readdata[44]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 257 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(258): object "avm_local_bb1_st_mul_inst0_readdata[45]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 258 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(259): object "avm_local_bb1_st_mul_inst0_readdata[46]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 259 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(260): object "avm_local_bb1_st_mul_inst0_readdata[47]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 260 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(261): object "avm_local_bb1_st_mul_inst0_readdata[48]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 261 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(262): object "avm_local_bb1_st_mul_inst0_readdata[49]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 262 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(263): object "avm_local_bb1_st_mul_inst0_readdata[50]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 263 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(264): object "avm_local_bb1_st_mul_inst0_readdata[51]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 264 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(265): object "avm_local_bb1_st_mul_inst0_readdata[52]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 265 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(266): object "avm_local_bb1_st_mul_inst0_readdata[53]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 266 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(267): object "avm_local_bb1_st_mul_inst0_readdata[54]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 267 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(268): object "avm_local_bb1_st_mul_inst0_readdata[55]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 268 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(269): object "avm_local_bb1_st_mul_inst0_readdata[56]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 269 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(270): object "avm_local_bb1_st_mul_inst0_readdata[57]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 270 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(271): object "avm_local_bb1_st_mul_inst0_readdata[58]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 271 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(272): object "avm_local_bb1_st_mul_inst0_readdata[59]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 272 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(273): object "avm_local_bb1_st_mul_inst0_readdata[60]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 273 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(274): object "avm_local_bb1_st_mul_inst0_readdata[61]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 274 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(275): object "avm_local_bb1_st_mul_inst0_readdata[62]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 275 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(276): object "avm_local_bb1_st_mul_inst0_readdata[63]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 276 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(277): object "avm_local_bb1_st_mul_inst0_readdata[64]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 277 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(278): object "avm_local_bb1_st_mul_inst0_readdata[65]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 278 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(279): object "avm_local_bb1_st_mul_inst0_readdata[66]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 279 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(280): object "avm_local_bb1_st_mul_inst0_readdata[67]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 280 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(281): object "avm_local_bb1_st_mul_inst0_readdata[68]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 281 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(282): object "avm_local_bb1_st_mul_inst0_readdata[69]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 282 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(283): object "avm_local_bb1_st_mul_inst0_readdata[70]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 283 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(284): object "avm_local_bb1_st_mul_inst0_readdata[71]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 284 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(285): object "avm_local_bb1_st_mul_inst0_readdata[72]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 285 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(286): object "avm_local_bb1_st_mul_inst0_readdata[73]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 286 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(287): object "avm_local_bb1_st_mul_inst0_readdata[74]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 287 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(288): object "avm_local_bb1_st_mul_inst0_readdata[75]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 288 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(289): object "avm_local_bb1_st_mul_inst0_readdata[76]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 289 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(290): object "avm_local_bb1_st_mul_inst0_readdata[77]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 290 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(291): object "avm_local_bb1_st_mul_inst0_readdata[78]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 291 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(292): object "avm_local_bb1_st_mul_inst0_readdata[79]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 292 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(293): object "avm_local_bb1_st_mul_inst0_readdata[80]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 293 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(294): object "avm_local_bb1_st_mul_inst0_readdata[81]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 294 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(295): object "avm_local_bb1_st_mul_inst0_readdata[82]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 295 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(296): object "avm_local_bb1_st_mul_inst0_readdata[83]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 296 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(297): object "avm_local_bb1_st_mul_inst0_readdata[84]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 297 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(298): object "avm_local_bb1_st_mul_inst0_readdata[85]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 298 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(299): object "avm_local_bb1_st_mul_inst0_readdata[86]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 299 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(300): object "avm_local_bb1_st_mul_inst0_readdata[87]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 300 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(301): object "avm_local_bb1_st_mul_inst0_readdata[88]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 301 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(302): object "avm_local_bb1_st_mul_inst0_readdata[89]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 302 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(303): object "avm_local_bb1_st_mul_inst0_readdata[90]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 303 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(304): object "avm_local_bb1_st_mul_inst0_readdata[91]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 304 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(305): object "avm_local_bb1_st_mul_inst0_readdata[92]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 305 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(306): object "avm_local_bb1_st_mul_inst0_readdata[93]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 306 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(307): object "avm_local_bb1_st_mul_inst0_readdata[94]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 307 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(308): object "avm_local_bb1_st_mul_inst0_readdata[95]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 308 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(309): object "avm_local_bb1_st_mul_inst0_readdata[96]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 309 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(310): object "avm_local_bb1_st_mul_inst0_readdata[97]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 310 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(311): object "avm_local_bb1_st_mul_inst0_readdata[98]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 311 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(312): object "avm_local_bb1_st_mul_inst0_readdata[99]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 312 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(313): object "avm_local_bb1_st_mul_inst0_readdata[100]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 313 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(314): object "avm_local_bb1_st_mul_inst0_readdata[101]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 314 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(315): object "avm_local_bb1_st_mul_inst0_readdata[102]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 315 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(316): object "avm_local_bb1_st_mul_inst0_readdata[103]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 316 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(317): object "avm_local_bb1_st_mul_inst0_readdata[104]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 317 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(318): object "avm_local_bb1_st_mul_inst0_readdata[105]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 318 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(319): object "avm_local_bb1_st_mul_inst0_readdata[106]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 319 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(320): object "avm_local_bb1_st_mul_inst0_readdata[107]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 320 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(321): object "avm_local_bb1_st_mul_inst0_readdata[108]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 321 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(322): object "avm_local_bb1_st_mul_inst0_readdata[109]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 322 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(323): object "avm_local_bb1_st_mul_inst0_readdata[110]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 323 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(324): object "avm_local_bb1_st_mul_inst0_readdata[111]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 324 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(325): object "avm_local_bb1_st_mul_inst0_readdata[112]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 325 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(326): object "avm_local_bb1_st_mul_inst0_readdata[113]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 326 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(327): object "avm_local_bb1_st_mul_inst0_readdata[114]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 327 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(328): object "avm_local_bb1_st_mul_inst0_readdata[115]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 328 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(329): object "avm_local_bb1_st_mul_inst0_readdata[116]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 329 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(330): object "avm_local_bb1_st_mul_inst0_readdata[117]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 330 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(331): object "avm_local_bb1_st_mul_inst0_readdata[118]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 331 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(332): object "avm_local_bb1_st_mul_inst0_readdata[119]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 332 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(333): object "avm_local_bb1_st_mul_inst0_readdata[120]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 333 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(334): object "avm_local_bb1_st_mul_inst0_readdata[121]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 334 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(335): object "avm_local_bb1_st_mul_inst0_readdata[122]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 335 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(336): object "avm_local_bb1_st_mul_inst0_readdata[123]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 336 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(337): object "avm_local_bb1_st_mul_inst0_readdata[124]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 337 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(338): object "avm_local_bb1_st_mul_inst0_readdata[125]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 338 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(339): object "avm_local_bb1_st_mul_inst0_readdata[126]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 339 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(340): object "avm_local_bb1_st_mul_inst0_readdata[127]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 340 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(341): object "avm_local_bb1_st_mul_inst0_readdata[128]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 341 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(342): object "avm_local_bb1_st_mul_inst0_readdata[129]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 342 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(343): object "avm_local_bb1_st_mul_inst0_readdata[130]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 343 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(344): object "avm_local_bb1_st_mul_inst0_readdata[131]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 344 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(345): object "avm_local_bb1_st_mul_inst0_readdata[132]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 345 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(346): object "avm_local_bb1_st_mul_inst0_readdata[133]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 346 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(347): object "avm_local_bb1_st_mul_inst0_readdata[134]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 347 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(348): object "avm_local_bb1_st_mul_inst0_readdata[135]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 348 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(349): object "avm_local_bb1_st_mul_inst0_readdata[136]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 349 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(350): object "avm_local_bb1_st_mul_inst0_readdata[137]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 350 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(351): object "avm_local_bb1_st_mul_inst0_readdata[138]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 351 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(352): object "avm_local_bb1_st_mul_inst0_readdata[139]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 352 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(353): object "avm_local_bb1_st_mul_inst0_readdata[140]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 353 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(354): object "avm_local_bb1_st_mul_inst0_readdata[141]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 354 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(355): object "avm_local_bb1_st_mul_inst0_readdata[142]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 355 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(356): object "avm_local_bb1_st_mul_inst0_readdata[143]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 356 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(357): object "avm_local_bb1_st_mul_inst0_readdata[144]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 357 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(358): object "avm_local_bb1_st_mul_inst0_readdata[145]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 358 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(359): object "avm_local_bb1_st_mul_inst0_readdata[146]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 359 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(360): object "avm_local_bb1_st_mul_inst0_readdata[147]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 360 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(361): object "avm_local_bb1_st_mul_inst0_readdata[148]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 361 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(362): object "avm_local_bb1_st_mul_inst0_readdata[149]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 362 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(363): object "avm_local_bb1_st_mul_inst0_readdata[150]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 363 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(364): object "avm_local_bb1_st_mul_inst0_readdata[151]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 364 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(365): object "avm_local_bb1_st_mul_inst0_readdata[152]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 365 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(366): object "avm_local_bb1_st_mul_inst0_readdata[153]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 366 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(367): object "avm_local_bb1_st_mul_inst0_readdata[154]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 367 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(368): object "avm_local_bb1_st_mul_inst0_readdata[155]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 368 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(369): object "avm_local_bb1_st_mul_inst0_readdata[156]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 369 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(370): object "avm_local_bb1_st_mul_inst0_readdata[157]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 370 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(371): object "avm_local_bb1_st_mul_inst0_readdata[158]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 371 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(372): object "avm_local_bb1_st_mul_inst0_readdata[159]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 372 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(373): object "avm_local_bb1_st_mul_inst0_readdata[160]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 373 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(374): object "avm_local_bb1_st_mul_inst0_readdata[161]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 374 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(375): object "avm_local_bb1_st_mul_inst0_readdata[162]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 375 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(376): object "avm_local_bb1_st_mul_inst0_readdata[163]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 376 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(377): object "avm_local_bb1_st_mul_inst0_readdata[164]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 377 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(378): object "avm_local_bb1_st_mul_inst0_readdata[165]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 378 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(379): object "avm_local_bb1_st_mul_inst0_readdata[166]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 379 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(380): object "avm_local_bb1_st_mul_inst0_readdata[167]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 380 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(381): object "avm_local_bb1_st_mul_inst0_readdata[168]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 381 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(382): object "avm_local_bb1_st_mul_inst0_readdata[169]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 382 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(383): object "avm_local_bb1_st_mul_inst0_readdata[170]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 383 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(384): object "avm_local_bb1_st_mul_inst0_readdata[171]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 384 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(385): object "avm_local_bb1_st_mul_inst0_readdata[172]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 385 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(386): object "avm_local_bb1_st_mul_inst0_readdata[173]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 386 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(387): object "avm_local_bb1_st_mul_inst0_readdata[174]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 387 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(388): object "avm_local_bb1_st_mul_inst0_readdata[175]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 388 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(389): object "avm_local_bb1_st_mul_inst0_readdata[176]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 389 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(390): object "avm_local_bb1_st_mul_inst0_readdata[177]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 390 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(391): object "avm_local_bb1_st_mul_inst0_readdata[178]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 391 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(392): object "avm_local_bb1_st_mul_inst0_readdata[179]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 392 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(393): object "avm_local_bb1_st_mul_inst0_readdata[180]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 393 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(394): object "avm_local_bb1_st_mul_inst0_readdata[181]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 394 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(395): object "avm_local_bb1_st_mul_inst0_readdata[182]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 395 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(396): object "avm_local_bb1_st_mul_inst0_readdata[183]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 396 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(397): object "avm_local_bb1_st_mul_inst0_readdata[184]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 397 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(398): object "avm_local_bb1_st_mul_inst0_readdata[185]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 398 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(399): object "avm_local_bb1_st_mul_inst0_readdata[186]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 399 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(400): object "avm_local_bb1_st_mul_inst0_readdata[187]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 400 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(401): object "avm_local_bb1_st_mul_inst0_readdata[188]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 401 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(402): object "avm_local_bb1_st_mul_inst0_readdata[189]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 402 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(403): object "avm_local_bb1_st_mul_inst0_readdata[190]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 403 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(404): object "avm_local_bb1_st_mul_inst0_readdata[191]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 404 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(405): object "avm_local_bb1_st_mul_inst0_readdata[192]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 405 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(406): object "avm_local_bb1_st_mul_inst0_readdata[193]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 406 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(407): object "avm_local_bb1_st_mul_inst0_readdata[194]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 407 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(408): object "avm_local_bb1_st_mul_inst0_readdata[195]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 408 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(409): object "avm_local_bb1_st_mul_inst0_readdata[196]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 409 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(410): object "avm_local_bb1_st_mul_inst0_readdata[197]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 410 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(411): object "avm_local_bb1_st_mul_inst0_readdata[198]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 411 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(412): object "avm_local_bb1_st_mul_inst0_readdata[199]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 412 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(413): object "avm_local_bb1_st_mul_inst0_readdata[200]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 413 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(414): object "avm_local_bb1_st_mul_inst0_readdata[201]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 414 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(415): object "avm_local_bb1_st_mul_inst0_readdata[202]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 415 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(416): object "avm_local_bb1_st_mul_inst0_readdata[203]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 416 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(417): object "avm_local_bb1_st_mul_inst0_readdata[204]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 417 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(418): object "avm_local_bb1_st_mul_inst0_readdata[205]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 418 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(419): object "avm_local_bb1_st_mul_inst0_readdata[206]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 419 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(420): object "avm_local_bb1_st_mul_inst0_readdata[207]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 420 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(421): object "avm_local_bb1_st_mul_inst0_readdata[208]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 421 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(422): object "avm_local_bb1_st_mul_inst0_readdata[209]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 422 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(423): object "avm_local_bb1_st_mul_inst0_readdata[210]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 423 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(424): object "avm_local_bb1_st_mul_inst0_readdata[211]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 424 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(425): object "avm_local_bb1_st_mul_inst0_readdata[212]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 425 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(426): object "avm_local_bb1_st_mul_inst0_readdata[213]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 426 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(427): object "avm_local_bb1_st_mul_inst0_readdata[214]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 427 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(428): object "avm_local_bb1_st_mul_inst0_readdata[215]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 428 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(429): object "avm_local_bb1_st_mul_inst0_readdata[216]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 429 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(430): object "avm_local_bb1_st_mul_inst0_readdata[217]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 430 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(431): object "avm_local_bb1_st_mul_inst0_readdata[218]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 431 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(432): object "avm_local_bb1_st_mul_inst0_readdata[219]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 432 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(433): object "avm_local_bb1_st_mul_inst0_readdata[220]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 433 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(434): object "avm_local_bb1_st_mul_inst0_readdata[221]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 434 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(435): object "avm_local_bb1_st_mul_inst0_readdata[222]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 435 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(436): object "avm_local_bb1_st_mul_inst0_readdata[223]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 436 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(437): object "avm_local_bb1_st_mul_inst0_readdata[224]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 437 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(438): object "avm_local_bb1_st_mul_inst0_readdata[225]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 438 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(439): object "avm_local_bb1_st_mul_inst0_readdata[226]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 439 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(440): object "avm_local_bb1_st_mul_inst0_readdata[227]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 440 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(441): object "avm_local_bb1_st_mul_inst0_readdata[228]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 441 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(442): object "avm_local_bb1_st_mul_inst0_readdata[229]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 442 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(443): object "avm_local_bb1_st_mul_inst0_readdata[230]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 443 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(444): object "avm_local_bb1_st_mul_inst0_readdata[231]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 444 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(445): object "avm_local_bb1_st_mul_inst0_readdata[232]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 445 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(446): object "avm_local_bb1_st_mul_inst0_readdata[233]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 446 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(447): object "avm_local_bb1_st_mul_inst0_readdata[234]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 447 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(448): object "avm_local_bb1_st_mul_inst0_readdata[235]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 448 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(449): object "avm_local_bb1_st_mul_inst0_readdata[236]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 449 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(450): object "avm_local_bb1_st_mul_inst0_readdata[237]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 450 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(451): object "avm_local_bb1_st_mul_inst0_readdata[238]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 451 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(452): object "avm_local_bb1_st_mul_inst0_readdata[239]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 452 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(453): object "avm_local_bb1_st_mul_inst0_readdata[240]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 453 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(454): object "avm_local_bb1_st_mul_inst0_readdata[241]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 454 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(455): object "avm_local_bb1_st_mul_inst0_readdata[242]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 455 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(456): object "avm_local_bb1_st_mul_inst0_readdata[243]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 456 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(457): object "avm_local_bb1_st_mul_inst0_readdata[244]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 457 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(458): object "avm_local_bb1_st_mul_inst0_readdata[245]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 458 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(459): object "avm_local_bb1_st_mul_inst0_readdata[246]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 459 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(460): object "avm_local_bb1_st_mul_inst0_readdata[247]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 460 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(461): object "avm_local_bb1_st_mul_inst0_readdata[248]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 461 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(462): object "avm_local_bb1_st_mul_inst0_readdata[249]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 462 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(463): object "avm_local_bb1_st_mul_inst0_readdata[250]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 463 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(464): object "avm_local_bb1_st_mul_inst0_readdata[251]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 464 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(465): object "avm_local_bb1_st_mul_inst0_readdata[252]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 465 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(466): object "avm_local_bb1_st_mul_inst0_readdata[253]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 466 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(467): object "avm_local_bb1_st_mul_inst0_readdata[254]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 467 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(468): object "avm_local_bb1_st_mul_inst0_readdata[255]~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 468 Warning (10036): Verilog HDL or VHDL warning at int_mult.sv(469): object "avm_local_bb1_st_mul_inst0_readdatavalid~input0" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 469 Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|altera_avalon_mm_clock_crossing_bridge:cra_int_add_clk_bridge" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 270 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(192): truncated value with size 32 to match size of target (3) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 192 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(194): truncated value with size 32 to match size of target (3) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 194 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|altera_avalon_mm_clock_crossing_bridge:cra_int_add_clk_bridge|altera_avalon_dc_fifo:cmd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|altera_avalon_mm_clock_crossing_bridge:cra_int_add_clk_bridge|altera_avalon_dc_fifo:rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 282 Info (12128): Elaborating entity "altera_avalon_mm_clock_crossing_bridge" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|altera_avalon_mm_clock_crossing_bridge:lsu_int_add_clk_bridge_read0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 298 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(210): truncated value with size 32 to match size of target (6) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 210 Warning (10230): Verilog HDL assignment warning at altera_avalon_mm_clock_crossing_bridge.v(213): truncated value with size 32 to match size of target (6) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 213 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|altera_avalon_mm_clock_crossing_bridge:lsu_int_add_clk_bridge_read0|altera_avalon_dc_fifo:cmd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v Line: 149 Info (12128): Elaborating entity "lsu_ic_top" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 509 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(106): object "o_id" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 106 Info (12128): Elaborating entity "lsu_swdimm_token_ring" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 244 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(2106): object "rd_data" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2106 Info (12128): Elaborating entity "lsu_token_ring" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2173 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(1882): object "to_avm_port_num" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1882 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(1700): truncated value with size 32 to match size of target (5) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1700 Warning (10034): Output port "o_id" at lsu_ic_top.v(1425) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1425 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "rd_data" into its bus Info (12128): Elaborating entity "lsu_n_token" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_n_token:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.rd_ring" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1622 Warning (10034): Output port "o_ext_waitrequest" at lsu_ic_top.v(472) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 472 Warning (10034): Output port "o_avm_byteenable" at lsu_ic_top.v(541) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 541 Warning (10034): Output port "o_active" at lsu_ic_top.v(487) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 487 Warning (10034): Output port "o_avm_writedata" at lsu_ic_top.v(549) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 549 Warning (10034): Output port "o_avm_write" at lsu_ic_top.v(544) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 544 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_id" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_byteenable" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_address" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_burstcount" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_writedata" into its bus Info (12128): Elaborating entity "lsu_n_fast" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_n_token:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.rd_ring|lsu_n_fast:GEN_ENABLE_FAST.lsu_n_fast" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 613 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(833): object "ext_req" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 833 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(856): truncated value with size 321 to match size of target (33) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 856 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(934): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 934 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(976): truncated value with size 32 to match size of target (2) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 976 Warning (10034): Output port "o_avm_writedata" at lsu_ic_top.v(826) has no driver File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 826 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1656 Info (12130): Elaborated megafunction instantiation "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1656 Info (12133): Instantiated megafunction "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1656 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "512" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "30" Info (12134): Parameter "lpm_widthu" = "9" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "499" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_2cc1.tdf Info (12023): Found entity 1: scfifo_2cc1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_2cc1.tdf Line: 25 Info (12128): Elaborating entity "scfifo_2cc1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_et91.tdf Info (12023): Found entity 1: a_dpfifo_et91 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 33 Info (12128): Elaborating entity "a_dpfifo_et91" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_2cc1.tdf Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5kn1.tdf Info (12023): Found entity 1: altsyncram_5kn1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_5kn1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_5kn1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|altsyncram_5kn1:FIFOram" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 46 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_8l8.tdf Info (12023): Found entity 1: cmpr_8l8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cmpr_8l8.tdf Line: 23 Info (12128): Elaborating entity "cmpr_8l8" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|cmpr_8l8:almost_full_comparer" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 54 Info (12128): Elaborating entity "cmpr_8l8" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|cmpr_8l8:two_comparison" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 55 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_lgb.tdf Info (12023): Found entity 1: cntr_lgb File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cntr_lgb.tdf Line: 26 Info (12128): Elaborating entity "cntr_lgb" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|cntr_lgb:rd_ptr_msb" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 56 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_2h7.tdf Info (12023): Found entity 1: cntr_2h7 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cntr_2h7.tdf Line: 26 Info (12128): Elaborating entity "cntr_2h7" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|cntr_2h7:usedw_counter" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 57 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_mgb.tdf Info (12023): Found entity 1: cntr_mgb File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cntr_mgb.tdf Line: 26 Info (12128): Elaborating entity "cntr_mgb" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_RD.GEN_RD_SET[0].rd_fifo|scfifo_2cc1:auto_generated|a_dpfifo_et91:dpfifo|cntr_mgb:wr_ptr" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_et91.tdf Line: 58 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1727 Info (12130): Elaborated megafunction instantiation "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1727 Info (12133): Instantiated megafunction "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1727 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "512" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "318" Info (12134): Parameter "lpm_widthu" = "9" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12134): Parameter "almost_full_value" = "503" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ddc1.tdf Info (12023): Found entity 1: scfifo_ddc1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_ddc1.tdf Line: 25 Info (12128): Elaborating entity "scfifo_ddc1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo|scfifo_ddc1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_7v91.tdf Info (12023): Found entity 1: a_dpfifo_7v91 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_7v91.tdf Line: 33 Info (12128): Elaborating entity "a_dpfifo_7v91" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo|scfifo_ddc1:auto_generated|a_dpfifo_7v91:dpfifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_ddc1.tdf Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nnn1.tdf Info (12023): Found entity 1: altsyncram_nnn1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_nnn1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_nnn1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[0].wr_fifo|scfifo_ddc1:auto_generated|a_dpfifo_7v91:dpfifo|altsyncram_nnn1:FIFOram" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_7v91.tdf Line: 46 Info (12128): Elaborating entity "lsu_n_token" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_n_token:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_SINGLE_WR_RING.wr_ring" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1849 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(644): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 644 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(659): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 659 Warning (10030): Net "ci_writedata[0][0]" at lsu_ic_top.v(572) has no driver or initial value, using a default initial value '0' File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 572 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_id" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_byteenable" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_address" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_burstcount" into its bus Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ci_writedata" into its bus Info (12128): Elaborating entity "lsu_ic_token" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_n_token:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_SINGLE_WR_RING.wr_ring|lsu_ic_token:GEN_DISABLE_FAST.GEN_IC[0].ic" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 704 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(399): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 399 Warning (10240): Verilog HDL Always Construct warning at lsu_ic_top.v(393): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 393 Info (12128): Elaborating entity "lsu_ic_token" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_n_token:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_SINGLE_WR_RING.wr_ring|lsu_ic_token:GEN_DISABLE_FAST.GEN_IC[1].ic" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 704 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(399): truncated value with size 32 to match size of target (1) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 399 Warning (10240): Verilog HDL Always Construct warning at lsu_ic_top.v(393): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 393 Info (12128): Elaborating entity "lsu_rd_back" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 1983 Warning (10858): Verilog HDL warning at lsu_ic_top.v(2495): object port_num used but never assigned File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2495 Warning (10858): Verilog HDL warning at lsu_ic_top.v(2499): object rd_data_en used but never assigned File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2499 Warning (10858): Verilog HDL warning at lsu_ic_top.v(2499): object data_empty used but never assigned File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2499 Warning (10858): Verilog HDL warning at lsu_ic_top.v(2500): object data_out used but never assigned File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2500 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(2501): object "R_rd_port_num" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2501 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(2505): object "data_to_ic_en" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2505 Warning (10036): Verilog HDL or VHDL warning at lsu_ic_top.v(2506): object "R_o_avm_burstcnt" assigned a value but never read File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2506 Warning (10230): Verilog HDL assignment warning at lsu_ic_top.v(2553): truncated value with size 32 to match size of target (5) File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2553 Warning (10030): Net "rd_data_en[0]" at lsu_ic_top.v(2499) has no driver or initial value, using a default initial value '0' File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2499 Warning (10030): Net "data_empty[0]" at lsu_ic_top.v(2499) has no driver or initial value, using a default initial value '0' File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2499 Info (12128): Elaborating entity "scfifo" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2690 Info (12130): Elaborated megafunction instantiation "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2690 Info (12133): Instantiated megafunction "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/lsu_ic_top.v Line: 2690 Info (12134): Parameter "add_ram_output_register" = "ON" Info (12134): Parameter "intended_device_family" = "Stratix V" Info (12134): Parameter "lpm_numwords" = "512" Info (12134): Parameter "lpm_widthu" = "9" Info (12134): Parameter "lpm_showahead" = "OFF" Info (12134): Parameter "lpm_type" = "scfifo" Info (12134): Parameter "lpm_width" = "7" Info (12134): Parameter "almost_full_value" = "499" Info (12134): Parameter "overflow_checking" = "OFF" Info (12134): Parameter "underflow_checking" = "ON" Info (12134): Parameter "use_eab" = "ON" Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_mac1.tdf Info (12023): Found entity 1: scfifo_mac1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_mac1.tdf Line: 25 Info (12128): Elaborating entity "scfifo_mac1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo|scfifo_mac1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/scfifo.tdf Line: 300 Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_2s91.tdf Info (12023): Found entity 1: a_dpfifo_2s91 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_2s91.tdf Line: 33 Info (12128): Elaborating entity "a_dpfifo_2s91" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo|scfifo_mac1:auto_generated|a_dpfifo_2s91:dpfifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/scfifo_mac1.tdf Line: 37 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dhn1.tdf Info (12023): Found entity 1: altsyncram_dhn1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_dhn1.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_dhn1" for hierarchy "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|lsu_rd_back:GEN_DISABLE_DATA_REORDER.GEN_DATA_VALID[0].lsu_rd_back|scfifo:port_num_fifo|scfifo_mac1:auto_generated|a_dpfifo_2s91:dpfifo|altsyncram_dhn1:FIFOram" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_dpfifo_2s91.tdf Line: 46 Info (12128): Elaborating entity "smack_ctrl_modify" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 508 Warning (10492): VHDL Process Statement warning at smack_ctrl_modify.vhd(140): signal "kernel_cnt" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 140 Warning (10492): VHDL Process Statement warning at smack_ctrl_modify.vhd(147): signal "shadow_cnt" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 147 Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 294 Info (12130): Elaborated megafunction instantiation "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 294 Info (12133): Instantiated megafunction "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 294 Info (12134): Parameter "intended_device_family" = "Cyclone V" Info (12134): Parameter "lpm_numwords" = "256" Info (12134): Parameter "lpm_showahead" = "ON" Info (12134): Parameter "lpm_width" = "1" Info (12134): Parameter "lpm_widthu" = "8" Info (12134): Parameter "lpm_widthu_r" = "3" Info (12134): Parameter "lpm_width_r" = "32" Info (12134): Parameter "rdsync_delaypipe" = "4" Info (12134): Parameter "wrsync_delaypipe" = "4" Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_img1.tdf Info (12023): Found entity 1: dcfifo_img1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 39 Info (12128): Elaborating entity "dcfifo_img1" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf Line: 79 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_8g6.tdf Info (12023): Found entity 1: a_graycounter_8g6 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_graycounter_8g6.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_8g6" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|a_graycounter_8g6:rdptr_g1p" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 52 Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_3ub.tdf Info (12023): Found entity 1: a_graycounter_3ub File: /home/ml6417/debug/int_add_mult/int_add_mult/db/a_graycounter_3ub.tdf Line: 25 Info (12128): Elaborating entity "a_graycounter_3ub" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|a_graycounter_3ub:wrptr_g1p" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 53 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_it41.tdf Info (12023): Found entity 1: altsyncram_it41 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_it41.tdf Line: 28 Info (12128): Elaborating entity "altsyncram_it41" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|altsyncram_it41:fifo_ram" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 54 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_c9l.tdf Info (12023): Found entity 1: alt_synch_pipe_c9l File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_c9l.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_c9l" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|alt_synch_pipe_c9l:rs_dgwp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 58 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_tu8.tdf Info (12023): Found entity 1: dffpipe_tu8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dffpipe_tu8.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_tu8" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|alt_synch_pipe_c9l:rs_dgwp|dffpipe_tu8:dffpipe10" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_c9l.tdf Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_d9l.tdf Info (12023): Found entity 1: alt_synch_pipe_d9l File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_d9l.tdf Line: 27 Info (12128): Elaborating entity "alt_synch_pipe_d9l" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|alt_synch_pipe_d9l:ws_dgrp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 59 Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_uu8.tdf Info (12023): Found entity 1: dffpipe_uu8 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dffpipe_uu8.tdf Line: 25 Info (12128): Elaborating entity "dffpipe_uu8" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|alt_synch_pipe_d9l:ws_dgrp|dffpipe_uu8:dffpipe13" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/alt_synch_pipe_d9l.tdf Line: 34 Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_su5.tdf Info (12023): Found entity 1: cmpr_su5 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cmpr_su5.tdf Line: 23 Info (12128): Elaborating entity "cmpr_su5" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|cmpr_su5:rdempty_eq_comp" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 60 Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_eed.tdf Info (12023): Found entity 1: cntr_eed File: /home/ml6417/debug/int_add_mult/int_add_mult/db/cntr_eed.tdf Line: 28 Info (12128): Elaborating entity "cntr_eed" for hierarchy "system:the_system|smack_ctrl_modify:int_add_smack_ctrl|dcfifo_mixed_widths:smack_fifo|dcfifo_img1:auto_generated|cntr_eed:cntr_b" File: /home/ml6417/debug/int_add_mult/int_add_mult/db/dcfifo_img1.tdf Line: 63 Info (12128): Elaborating entity "smack_ctrl_modify" for hierarchy "system:the_system|smack_ctrl_modify:int_mult_smack_ctrl" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 528 Warning (10492): VHDL Process Statement warning at smack_ctrl_modify.vhd(140): signal "kernel_cnt" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 140 Warning (10492): VHDL Process Statement warning at smack_ctrl_modify.vhd(147): signal "shadow_cnt" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/smack_ctrl_modify.vhd Line: 147 Info (12128): Elaborating entity "system_mm_interconnect_0" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 555 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:int_add_mult_system_avm_memgmem0_port_0_0_rw_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 340 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:acl_iface_kernel_mem0_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 465 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:acl_iface_kernel_mem0_agent_rdata_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 506 Info (12128): Elaborating entity "system_mm_interconnect_0_router" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_0_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 522 Info (12128): Elaborating entity "system_mm_interconnect_0_router_default_decode" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_0_router:router|system_mm_interconnect_0_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0_router.sv Line: 174 Info (12128): Elaborating entity "system_mm_interconnect_0_cmd_demux" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_0_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 555 Info (12128): Elaborating entity "system_mm_interconnect_0_cmd_mux" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_0_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 572 Info (12128): Elaborating entity "system_mm_interconnect_0_rsp_mux" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|system_mm_interconnect_0_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 606 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_0.v Line: 646 Info (12128): Elaborating entity "altera_dcfifo_synchronizer_bundle" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo|altera_dcfifo_synchronizer_bundle:write_crosser" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_avalon_dc_fifo.v Line: 373 Info (12128): Elaborating entity "altera_std_synchronizer_nocut" for hierarchy "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[0].u" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v Line: 33 Info (12128): Elaborating entity "system_mm_interconnect_1" for hierarchy "system:the_system|system_mm_interconnect_1:mm_interconnect_1" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 582 Info (12128): Elaborating entity "system_mm_interconnect_3" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 602 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3|altera_merlin_master_translator:avs_int_mult_cra_cra_ring_cra_master_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_3.v Line: 99 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_mm_interconnect_3:mm_interconnect_3|altera_merlin_slave_translator:int_add_mult_system_avs_int_mult_cra_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_3.v Line: 163 Info (12128): Elaborating entity "system_mm_interconnect_4" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 628 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|altera_merlin_master_translator:acl_iface_kernel_cra_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 194 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|altera_merlin_slave_translator:cra_root_cra_slave_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 258 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|altera_merlin_master_agent:acl_iface_kernel_cra_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 339 Info (12128): Elaborating entity "system_mm_interconnect_4_router" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|system_mm_interconnect_4_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 521 Info (12128): Elaborating entity "system_mm_interconnect_4_router_default_decode" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|system_mm_interconnect_4_router:router|system_mm_interconnect_4_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4_router.sv Line: 174 Info (12128): Elaborating entity "system_mm_interconnect_4_cmd_demux" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|system_mm_interconnect_4_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 554 Info (12128): Elaborating entity "system_mm_interconnect_4_cmd_mux" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|system_mm_interconnect_4_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 571 Info (12128): Elaborating entity "system_mm_interconnect_4_rsp_mux" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|system_mm_interconnect_4_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 605 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_mm_interconnect_4:mm_interconnect_4|altera_avalon_dc_fifo:async_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_4.v Line: 645 Info (12128): Elaborating entity "system_mm_interconnect_5" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 658 Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_translator:acl_iface_prime_bus_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 282 Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_translator:int_add_smack_ctrl_bus_translator" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 346 Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_master_agent:acl_iface_prime_bus_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 491 Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_agent:int_add_smack_ctrl_bus_agent" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 575 Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_slave_agent:int_add_smack_ctrl_bus_agent|altera_merlin_burst_uncompressor:uncompressor" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 608 Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_sc_fifo:int_add_smack_ctrl_bus_agent_rsp_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 616 Info (12128): Elaborating entity "system_mm_interconnect_5_router" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_router:router" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 839 Info (12128): Elaborating entity "system_mm_interconnect_5_router_default_decode" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_router:router|system_mm_interconnect_5_router_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router.sv Line: 180 Info (12128): Elaborating entity "system_mm_interconnect_5_router_001" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_router_001:router_001" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 855 Info (12128): Elaborating entity "system_mm_interconnect_5_router_001_default_decode" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_router_001:router_001|system_mm_interconnect_5_router_001_default_decode:the_default_decode" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_router_001.sv Line: 173 Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_merlin_traffic_limiter:acl_iface_prime_bus_limiter" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 921 Info (12128): Elaborating entity "system_mm_interconnect_5_cmd_demux" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_cmd_demux:cmd_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 944 Info (12128): Elaborating entity "system_mm_interconnect_5_cmd_mux" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_cmd_mux:cmd_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 961 Info (12128): Elaborating entity "system_mm_interconnect_5_rsp_demux" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_rsp_demux:rsp_demux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 995 Info (12128): Elaborating entity "system_mm_interconnect_5_rsp_mux" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_rsp_mux:rsp_mux" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 1035 Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|system_mm_interconnect_5_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5_rsp_mux.sv Line: 310 Info (12128): Elaborating entity "altera_avalon_dc_fifo" for hierarchy "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_mm_interconnect_5.v Line: 1075 Info (12128): Elaborating entity "altera_irq_clock_crosser" for hierarchy "system:the_system|altera_irq_clock_crosser:irq_synchronizer" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 676 Info (12128): Elaborating entity "altera_std_synchronizer_bundle" for hierarchy "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_irq_clock_crosser.sv Line: 45 Info (12130): Elaborated megafunction instantiation "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_irq_clock_crosser.sv Line: 45 Info (12133): Instantiated megafunction "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync" with the following parameter: File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/altera_irq_clock_crosser.sv Line: 45 Info (12134): Parameter "depth" = "3" Info (12134): Parameter "width" = "1" Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v Line: 41 Info (12131): Elaborated megafunction instantiation "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync|altera_std_synchronizer:sync[0].u", which is child of megafunction instantiation "system:the_system|altera_irq_clock_crosser:irq_synchronizer|altera_std_synchronizer_bundle:sync" File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v Line: 41 Info (12128): Elaborating entity "async_counter_30" for hierarchy "async_counter_30:AC30" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 200 Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "system:the_system|int_add_mult_system:int_add_mult_system|avm_kernel_wr_waitrequest[0]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add_mult_system.v Line: 111 Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[63]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[62]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[61]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[60]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[59]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[58]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[57]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[56]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[55]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[54]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[53]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[52]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[51]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[50]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[49]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[48]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[47]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[46]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[45]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[44]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[43]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[42]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[41]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[40]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[39]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[38]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[37]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[36]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[35]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[34]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[33]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[32]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[31]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[30]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[29]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[28]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[27]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[26]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[25]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[24]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[23]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[22]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[21]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[20]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[19]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[18]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[17]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[16]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[15]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[14]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[13]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[12]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[11]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[10]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[9]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[8]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[7]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[6]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[5]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[4]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[3]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[2]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_sw_reset_s_readdata[1]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 91 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[31]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[30]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[29]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[28]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[27]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[26]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[25]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[24]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[23]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[22]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[21]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[20]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[19]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[18]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[17]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[16]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[15]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[14]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[13]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[12]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[11]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[10]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[9]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[8]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[7]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[6]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[5]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[4]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[3]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[2]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_kernel_interface:kernel_interface|mm_interconnect_1_mem_org_mode_s_readdata[1]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_kernel_interface.v Line: 97 Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic. File: /mnt/applications/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 2224 Warning (12011): Net is missing source, defaulting to GND Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[31]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[30]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[29]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[28]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[27]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[26]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[25]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[24]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[23]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[22]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[21]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[20]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[19]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[18]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[17]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[16]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[15]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[14]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[13]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[12]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[11]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[10]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[9]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[8]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[7]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[6]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[5]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[4]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[3]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[2]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_sw_reset_s_readdata[1]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 55 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[31]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[30]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[29]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[28]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[27]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[26]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[25]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[24]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[23]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[22]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[21]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[20]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[19]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[18]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[17]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[16]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[15]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[14]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[13]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[12]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[11]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[10]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[9]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[8]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[7]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[6]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[5]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[4]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[3]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[2]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Warning (12110): Net "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|mm_interconnect_0_pll_lock_avs_0_s_readdata[1]" is missing source, defaulting to GND File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v Line: 61 Info (12205): 1 design partition requires Analysis and Synthesis Info (12210): Partition "Top" requires synthesis because its netlist type is Source File Info (12207): 1 design partition does not require synthesis Info (12225): Partition "acl_iface_partition" does not require synthesis because you disabled automatic resynthesis for this partition, which is Post-Fit (Strict) Info (12244): Starting Rapid Recompile for partition "Top" Info (12244): Starting Rapid Recompile for partition "system_acl_iface_hps_hps_io_border:border" Warning (12241): 131 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (281037): Using 16 processors to synthesize 2 partitions in parallel Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:52:36 2021 Info: Command: quartus_map --recompile=on --parallel=1 --helper=2 --helper_type=user_partition --partition=system_acl_iface_hps_hps_io_border:border top -c top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:52:36 2021 Info: Command: quartus_map --recompile=on --parallel=1 --helper=0 --helper_type=user_partition --partition=Top top -c top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info (281019): Starting Logic Optimization and Technology Mapping for Partition system_acl_iface_hps_hps_io_border:border File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 101 Info (19000): Inferred 6 megafunctions from design logic Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_003|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_002|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 33 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 33 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_001|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 8 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 8 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 8 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 8 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_1:mm_interconnect_1|altera_avalon_dc_fifo:async_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 328 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 328 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (276029): Inferred altsyncram megafunction from the following design logic: "system:the_system|system_mm_interconnect_0:mm_interconnect_0|altera_avalon_dc_fifo:async_fifo|mem_rtl_0" Info (286033): Parameter OPERATION_MODE set to DUAL_PORT Info (286033): Parameter WIDTH_A set to 328 Info (286033): Parameter WIDTHAD_A set to 3 Info (286033): Parameter NUMWORDS_A set to 8 Info (286033): Parameter WIDTH_B set to 328 Info (286033): Parameter WIDTHAD_B set to 3 Info (286033): Parameter NUMWORDS_B set to 8 Info (286033): Parameter ADDRESS_ACLR_A set to NONE Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED Info (286033): Parameter ADDRESS_ACLR_B set to NONE Info (286033): Parameter OUTDATA_ACLR_B set to NONE Info (286033): Parameter ADDRESS_REG_B set to CLOCK1 Info (286033): Parameter INDATA_ACLR_A set to NONE Info (286033): Parameter WRCONTROL_ACLR_A set to NONE Info (12130): Elaborated megafunction instantiation "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_003|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_003|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "33" Info (12134): Parameter "WIDTHAD_A" = "3" Info (12134): Parameter "NUMWORDS_A" = "8" Info (12134): Parameter "WIDTH_B" = "33" Info (12134): Parameter "WIDTHAD_B" = "3" Info (12134): Parameter "NUMWORDS_B" = "8" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_83j1.tdf Info (12023): Found entity 1: altsyncram_83j1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_83j1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_001|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_mm_interconnect_5:mm_interconnect_5|altera_avalon_dc_fifo:async_fifo_001|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "8" Info (12134): Parameter "WIDTHAD_A" = "3" Info (12134): Parameter "NUMWORDS_A" = "8" Info (12134): Parameter "WIDTH_B" = "8" Info (12134): Parameter "WIDTHAD_B" = "3" Info (12134): Parameter "NUMWORDS_B" = "8" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c0j1.tdf Info (12023): Found entity 1: altsyncram_c0j1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_c0j1.tdf Line: 28 Info (12130): Elaborated megafunction instantiation "system:the_system|system_mm_interconnect_1:mm_interconnect_1|altera_avalon_dc_fifo:async_fifo|altsyncram:mem_rtl_0" Info (12133): Instantiated megafunction "system:the_system|system_mm_interconnect_1:mm_interconnect_1|altera_avalon_dc_fifo:async_fifo|altsyncram:mem_rtl_0" with the following parameter: Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT" Info (12134): Parameter "WIDTH_A" = "328" Info (12134): Parameter "WIDTHAD_A" = "3" Info (12134): Parameter "NUMWORDS_A" = "8" Info (12134): Parameter "WIDTH_B" = "328" Info (12134): Parameter "WIDTHAD_B" = "3" Info (12134): Parameter "NUMWORDS_B" = "8" Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1" Info (12134): Parameter "INDATA_ACLR_A" = "NONE" Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_m6j1.tdf Info (12023): Found entity 1: altsyncram_m6j1 File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_m6j1.tdf Line: 28 Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition Warning (13034): The following nodes have both tri-state and non-tri-state drivers Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_emac0_inst_MDIO[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 40 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_CMD[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 48 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D0[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 49 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D1[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 50 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D2[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 52 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D3[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 53 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO41[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 58 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO42[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 59 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO43[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 60 Warning (13035): Inserted always-enabled tri-state buffer between "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO44[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 61 Info (13060): One or more bidirectional pins are fed by always enabled tri-state buffers Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_emac0_inst_MDIO[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 40 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_CMD[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 48 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D0[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 49 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D1[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 50 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D2[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 52 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D3[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 53 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO41[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 58 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO42[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 59 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO43[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 60 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO44[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 61 Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_emac0_inst_MDIO[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 40 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_CMD[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 48 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D0[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 49 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D1[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 50 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D2[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 52 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_sdio_inst_D3[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 53 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO41[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 58 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO42[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 59 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO43[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 60 Warning (13010): Node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_io_gpio_inst_GPIO44[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sv Line: 61 Info (21057): Implemented 919 device resources after synthesis - the final resource count might be different Info (21058): Implemented 8 input pins Info (21059): Implemented 41 output pins Info (21060): Implemented 62 bidirectional pins Info (21061): Implemented 46 logic cells Info (21066): Implemented 1 delay-locked loops Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 22 warnings Info: Peak virtual memory: 1538 megabytes Info: Processing ended: Wed Jun 2 20:53:03 2021 Info: Elapsed time: 00:00:27 Info: Total CPU time (on all processors): 00:00:26 Warning (13034): The following nodes have both tri-state and non-tri-state drivers Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[4]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[5]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[6]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[7]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[8]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[9]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[10]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[11]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[12]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[13]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[14]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[15]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[16]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[17]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[18]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[19]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[20]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[21]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[22]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[23]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[24]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[25]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[26]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[27]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[28]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[29]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[30]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[31]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[32]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[33]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[34]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[35]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[36]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[37]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[38]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dq[39]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs[4]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs_n[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs_n[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs_n[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs_n[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13035): Inserted always-enabled tri-state buffer between "memory_mem_dqs_n[4]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13035): Inserted always-enabled tri-state buffer between "emac_mdio" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 80 Warning (13035): Inserted always-enabled tri-state buffer between "sd_cmd" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 89 Warning (13035): Inserted always-enabled tri-state buffer between "sd_d[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13035): Inserted always-enabled tri-state buffer between "sd_d[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13035): Inserted always-enabled tri-state buffer between "sd_d[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13035): Inserted always-enabled tri-state buffer between "sd_d[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13035): Inserted always-enabled tri-state buffer between "led[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13035): Inserted always-enabled tri-state buffer between "led[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13035): Inserted always-enabled tri-state buffer between "led[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13035): Inserted always-enabled tri-state buffer between "led[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13035): Inserted always-enabled tri-state buffer between "i2c_sda" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 96 Warning (13035): Inserted always-enabled tri-state buffer between "i2c_scl" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 95 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[4]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[5]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[6]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[7]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[8]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[9]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[10]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[11]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[12]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[13]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[14]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[15]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[16]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[17]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[18]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[19]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[20]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[21]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[22]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[23]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[24]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[25]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[26]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[27]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[28]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[29]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[30]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dq[31]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs_n[0]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs_n[1]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs_n[2]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13035): Inserted always-enabled tri-state buffer between "fpga_memory_mem_dqs_n[3]" and its non-tri-state driver. File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (13060): One or more bidirectional pins are fed by always enabled tri-state buffers Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[4]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[5]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[6]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[7]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[8]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[9]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[10]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[11]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[12]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[13]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[14]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[15]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[16]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[17]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[18]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[19]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[20]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[21]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[22]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[23]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[24]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[25]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[26]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[27]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[28]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[29]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[30]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[31]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[32]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[33]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[34]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[35]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[36]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[37]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[38]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dq[39]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs[4]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs_n[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs_n[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs_n[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs_n[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "memory_mem_dqs_n[4]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "emac_mdio" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 80 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "sd_cmd" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 89 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "sd_d[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "sd_d[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "sd_d[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "sd_d[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "led[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "led[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "led[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "led[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "i2c_sda" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 96 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "i2c_scl" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 95 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[4]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[5]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[6]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[7]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[8]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[9]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[10]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[11]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[12]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[13]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[14]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[15]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[16]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[17]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[18]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[19]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[20]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[21]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[22]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[23]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[24]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[25]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[26]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[27]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[28]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[29]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[30]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dq[31]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs_n[0]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs_n[1]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs_n[2]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (13061): Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "fpga_memory_mem_dqs_n[3]" is moved to its source File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "memory_mem_dq[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[4]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[5]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[6]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[7]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[8]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[9]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[10]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[11]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[12]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[13]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[14]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[15]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[16]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[17]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[18]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[19]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[20]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[21]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[22]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[23]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[24]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[25]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[26]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[27]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[28]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[29]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[30]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[31]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[32]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[33]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[34]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[35]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[36]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[37]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[38]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dq[39]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Warning (13010): Node "memory_mem_dqs[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13010): Node "memory_mem_dqs[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13010): Node "memory_mem_dqs[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13010): Node "memory_mem_dqs[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13010): Node "memory_mem_dqs[4]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Warning (13010): Node "memory_mem_dqs_n[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13010): Node "memory_mem_dqs_n[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13010): Node "memory_mem_dqs_n[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13010): Node "memory_mem_dqs_n[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13010): Node "memory_mem_dqs_n[4]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Warning (13010): Node "emac_mdio~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 80 Warning (13010): Node "sd_cmd~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 89 Warning (13010): Node "sd_d[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13010): Node "sd_d[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13010): Node "sd_d[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13010): Node "sd_d[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 91 Warning (13010): Node "led[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13010): Node "led[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13010): Node "led[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13010): Node "led[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 94 Warning (13010): Node "i2c_sda~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 96 Warning (13010): Node "i2c_scl~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 95 Warning (13010): Node "fpga_memory_mem_dq[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[4]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[5]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[6]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[7]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[8]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[9]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[10]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[11]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[12]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[13]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[14]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[15]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[16]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[17]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[18]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[19]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[20]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[21]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[22]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[23]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[24]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[25]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[26]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[27]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[28]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[29]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[30]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dq[31]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Warning (13010): Node "fpga_memory_mem_dqs[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13010): Node "fpga_memory_mem_dqs[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13010): Node "fpga_memory_mem_dqs[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13010): Node "fpga_memory_mem_dqs[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Warning (13010): Node "fpga_memory_mem_dqs_n[0]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13010): Node "fpga_memory_mem_dqs_n[1]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13010): Node "fpga_memory_mem_dqs_n[2]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Warning (13010): Node "fpga_memory_mem_dqs_n[3]~synth" File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (17016): Found the following redundant logic cells in design Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|avs_cra_readdatavalid~reg0feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75669 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|cra_read_st1_NO_SHIFT_REG~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75654 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|has_a_lsu_active~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 69492 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75673 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76771 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79736 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78639 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|avs_cra_readdata[9]~reg0feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75414 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|avs_cra_readdata[12]~reg0feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75519 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_st_add|sync_rstn_MS[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 22941 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75658 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 50611 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79721 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78105 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78128 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76233 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75174 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78151 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75197 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79266 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75220 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75243 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78220 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76369 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75300 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75323 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76415 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78329 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75369 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75398 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76518 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75461 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78454 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79552 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79575 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78540 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76673 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79638 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76702 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79667 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75627 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76731 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75063 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79138 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76146 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75086 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75100 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78065 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56782 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 49106 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76184 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79177 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75142 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79211 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79234 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78182 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76281 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79280 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76314 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79303 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78234 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76337 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78291 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79377 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76429 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79400 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78343 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76452 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78366 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79440 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75412 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78389 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79480 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79503 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75475 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76549 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75498 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78485 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76589 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76612 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76635 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79606 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75572 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79698 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52538 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52463 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52413 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56550 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56482 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48909 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48791 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53991 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 56768 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53889 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54122 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|cra_addr_st1_NO_SHIFT_REG[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 73914 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|cra_addr_st1_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 73929 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75082 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75172 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75214 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75256 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75298 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75430 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75577 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51559 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78079 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76218 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46587 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57472 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46889 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78205 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52056 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52722 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52081 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57223 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52836 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57189 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45996 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52802 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76400 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51844 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78314 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75354 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53443 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75383 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46336 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46396 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53052 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52010 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56985 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78439 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46720 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57339 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53660 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46780 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52588 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56516 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52563 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 78525 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53923 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56630 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76658 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52488 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56664 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76687 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 79652 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 75612 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 76716 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52438 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56728 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 49047 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52513 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51478 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51512 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51444 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 53300 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51878 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51810 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51970 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51930 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51636 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51730 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51586 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52115 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51755 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51689 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51895 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51947 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51987 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56584 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57364 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57304 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56837 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56871 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56905 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56951 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57019 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57072 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57142 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57107 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57258 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57498 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57431 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48659 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48731 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48943 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48977 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46686 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46030 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46055 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46263 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46229 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46136 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46473 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46447 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46509 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46545 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46827 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46853 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 49073 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52992 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53112 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53159 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53191 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53217 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53363 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53281 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53322 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53409 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53477 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53549 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53626 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54166 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54200 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54063 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53948 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74028 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74155 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74197 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74239 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74281 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74335 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|status_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 75480 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|status_NO_SHIFT_REG[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 74463 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52278 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52236 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52192 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[92]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 55980 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48829 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48757 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 49013 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[89]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53773 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[92]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53719 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[94]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54089 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46572 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57457 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51274 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[75]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52650 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[77]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56226 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45818 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[77]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52748 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51210 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[80]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52902 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46302 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46362 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[82]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53018 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51158 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[83]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56136 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46642 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[85]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56104 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[85]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53582 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46746 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52310 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[87]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56060 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52294 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[88]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53789 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[90]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56018 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52252 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 52220 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51126 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51142 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51098 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51184 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51621 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51715 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51248 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51290 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 51674 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[88]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56044 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[86]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56088 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[84]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56120 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[79]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56188 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[81]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56162 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 57057 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[75]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56252 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[74]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 56268 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41137 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41789 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46948 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48685 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48855 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46626 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45856 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46163 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46102 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 46413 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45872 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47692 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47817 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[81]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52874 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[83]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53078 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53176 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53348 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[74]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52678 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53307 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[78]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 52928 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[84]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53515 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[86]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53566 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[90]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53757 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[93]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 54029 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|kernel_arguments_NO_SHIFT_REG[87]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 53805 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46657 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41567 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41552 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45557 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29563 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29547 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29479 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29391 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29695 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29146 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29202 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29174 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29579 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29611 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29595 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29643 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29659 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29627 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29270 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29254 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29286 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 29228 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 28031 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27687 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27653 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 28067 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27883 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25294 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25312 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25410 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25392 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 26219 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 26237 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25630 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25646 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25662 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25494 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25428 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25446 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25464 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25566 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25536 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25710 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25694 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25678 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25614 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24991 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25047 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25019 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25095 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25079 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25063 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27572 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25143 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25111 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 25127 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27397 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27381 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 27468 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25378 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25580 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25610 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25628 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25530 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25562 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25488 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25470 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27184 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27773 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27212 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27338 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27370 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27354 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27228 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27731 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27747 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27302 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27274 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25919 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25969 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25951 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26025 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26335 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26043 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26079 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26061 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26097 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26365 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26395 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26255 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26287 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26305 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26544 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26562 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26580 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26688 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26652 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26670 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26598 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26616 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26634 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26814 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[1][30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 26512 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25250 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25268 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25300 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25318 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 30292 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[2][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 25348 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27577 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27699 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27715 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27673 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27593 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27625 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|local_size_NO_SHIFT_REG[0][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 27609 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70894 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 71022 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42109 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46470 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46485 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46551 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46536 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46255 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46313 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][60]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41710 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45050 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45074 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44038 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44053 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48070 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48085 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 51943 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45720 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45705 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41503 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45617 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45330 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45388 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47782 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 43400 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 43385 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46689 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][37]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45532 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43211 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][38]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46348 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45477 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43338 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46132 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46147 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45173 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45158 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46078 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45052 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43450 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46000 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 40808 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45871 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45886 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41879 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44652 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44667 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44525 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44574 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44598 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45487 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45536 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 42100 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44240 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44225 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44107 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44165 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42414 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42293 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48145 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41994 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42043 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42058 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41876 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41934 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68958 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69184 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69312 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70910 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70952 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70968 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70936 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 71070 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 71006 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 71038 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 71054 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45369 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45427 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45194 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45252 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45179 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42151 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43706 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][58]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45109 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43509 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43567 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45693 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45708 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43631 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43616 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][37]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46402 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46444 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46583 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43289 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46287 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41120 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][59]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 44981 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48597 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47877 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47892 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47047 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47952 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47967 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][58]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 43969 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][55]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48002 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44818 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44885 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44998 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44930 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44450 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44474 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41477 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][36]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45592 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45362 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41625 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45285 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 43914 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41535 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45205 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43380 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][42]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46044 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45093 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][43]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45975 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 40782 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][43]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45764 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44753 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][46]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44702 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][49]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45462 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 42074 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][50]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44327 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43663 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][51]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45287 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44272 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44139 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][53]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42337 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42379 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][54]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42215 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48187 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][54]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48120 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][56]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41969 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41908 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][57]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 41851 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32693 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32709 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 33387 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32725 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32767 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34651 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 35467 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34501 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34975 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34545 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34529 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 35346 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24285 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24109 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24079 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24443 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24303 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24321 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68984 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68942 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69200 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69232 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69258 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69216 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69030 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69058 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69084 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69136 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69110 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69328 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69274 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69344 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69392 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69360 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 69376 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70660 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70708 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|workgroup_size_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 70744 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45401 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45226 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][55]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42093 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][44]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45921 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][47]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45634 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][48]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45580 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][36]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46520 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][40]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 46182 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43263 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45033 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48571 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47089 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][57]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47852 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][56]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47927 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44021 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 48053 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44859 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][49]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44381 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45688 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41599 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][40]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 45260 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43321 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43433 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45854 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 41862 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][48]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44509 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44557 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45519 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rcnode_323to324_rc0_bb1_inc_0_reg_324_fifo|acl_ll_fifo:fifo|data[0][51]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44209 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42276 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 42026 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32899 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 33019 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 33003 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32967 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32751 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 32793 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 23914 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 23798 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 23932 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 23770 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34731 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34667 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34747 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34695 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 35031 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 35083 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 35067 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34599 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34625 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 34583 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24383 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24413 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24365 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24213 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24195 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24139 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24231 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24249 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24267 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24505 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24559 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24461 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24577 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24523 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 24541 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31707 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 34409 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 34695 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31761 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31809 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31733 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36171 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36023 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 35966 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][29]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 37065 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][27]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36820 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 37157 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 37191 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][31]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32775 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33083 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rcnode_320to321_rc0_bb1_inc_0_reg_321_fifo|acl_ll_fifo:fifo|data[0][52]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45163 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43492 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43550 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 45676 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_0:int_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 43599 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 47030 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_bb1_mul_valid_out_NO_SHIFT_REG~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 51975 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44981 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_0:int_mult_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 44433 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31777 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31793 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32150 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32252 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32178 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32194 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32226 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32210 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31919 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31855 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31935 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[1][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 31883 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36051 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][24]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36067 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36135 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 35634 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 35678 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 35662 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 35694 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36249 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36931 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36207 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36265 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[2][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 36223 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33009 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33051 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32853 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 32931 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33025 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33067 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33099 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33159 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33143 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|num_groups_NO_SHIFT_REG[0][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 33127 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_1to320_input_global_id_0_0_reg_320_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_j6d1:auto_generated|a_dpfifo_d9a1:dpfifo|wrreq_delaya[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 22546 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_319to320_t_01_0_reg_320_fifo|acl_ll_fifo:fifo|data[0][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68155 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_bb1_mul_valid_pipe_0_NO_SHIFT_REG~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 51982 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57881 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58265 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57948 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_319to320_t_01_0_reg_320_fifo|acl_ll_fifo:fifo|data[0][7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67733 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_319to320_t_01_0_reg_320_fifo|acl_ll_fifo:fifo|data[0][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67471 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57707 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58192 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_322to323_t_01_0_reg_323_fifo|acl_ll_fifo:fifo|data[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58009 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67843 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68137 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 66853 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67819 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67898 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67715 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68020 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67959 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 68075 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57863 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57079 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57930 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58315 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58174 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58119 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57991 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67782 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67654 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67996 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67935 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57802 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57055 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57906 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58247 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58058 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_st_mul|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 23199 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 66838 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67758 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67624 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67700 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57848 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 57778 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58217 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58034 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58104 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 67639 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 58232 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 50173 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49004 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_st_add|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 63016 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_st_add|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 63191 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49094 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49036 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49052 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49483 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49760 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49794 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_st_add|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 63225 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|lsu_top:lsu_local_bb1_st_add|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 63287 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_st_mul|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 66590 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49136 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49168 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49363 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49639 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49551 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49854 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49894 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49936 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49952 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 49984 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|int_add_function:int_add_function_inst0|int_add_basic_block_1:int_add_basic_block_1|acl_data_fifo:rnode_160to161_bb1_arrayidx5_RM_0_reg_161_fifo|acl_staging_reg:staging_reg|r_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_add.sv Line: 50000 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 62612 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 62952 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63104 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63382 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_st_mul|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 66408 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|lsu_top:lsu_local_bb1_st_mul|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 66516 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 62690 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 62740 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 62782 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63041 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63271 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63193 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63416 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_staging_reg:staging_reg|r_data[11]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63432 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63464 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63526 Info (17048): Logic cell "system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|int_mult_function:int_mult_function_inst0|int_mult_basic_block_1:int_mult_basic_block_1|acl_data_fifo:rnode_163to164_bb1_arrayidx5_RM_0_reg_164_fifo|acl_staging_reg:staging_reg|r_data[14]~feeder" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/int_mult.sv Line: 63588 Info (21057): Implemented 18961 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins Info (21059): Implemented 76 output pins Info (21060): Implemented 102 bidirectional pins Info (21061): Implemented 16536 logic cells Info (21064): Implemented 2231 RAM segments Info (21071): Implemented 1 partitions Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 206 warnings Info: Peak virtual memory: 1515 megabytes Info: Processing ended: Wed Jun 2 20:53:13 2021 Info: Elapsed time: 00:00:37 Info: Total CPU time (on all processors): 00:00:36 Info (281038): Finished parallel synthesis of all partitions Info (144001): Generated suppressed messages file /home/ml6417/debug/int_add_mult/int_add_mult/top.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1010 warnings Info: Peak virtual memory: 3093 megabytes Info: Processing ended: Wed Jun 2 20:57:13 2021 Info: Elapsed time: 00:06:42 Info: Total CPU time (on all processors): 00:07:30 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:57:15 2021 Info: Command: quartus_cdb -t scripts/post_module.tcl quartus_map top top Info: Quartus(args): quartus_map top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post_module.tcl script Info: Skipping import since acl_iface_partition.qxp not found Info (23030): Evaluation of Tcl script scripts/post_module.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1284 megabytes Info: Processing ended: Wed Jun 2 20:57:16 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 Info: ******************************************************************* Info: Running Quartus Prime Partition Merge Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:57:17 2021 Info: Command: quartus_cdb --read_settings_files=on --write_settings_files=off top -c top --merge=on --recompile=on Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Critical Warning (12819): Rapid Recompile may ignore modifying, adding, or deleting SDC files. Info (12845): SDC file was added: /home/ml6417/debug/int_add_mult/int_add_mult/top_guaranteed_timing.sdc. Info (12849): Using Hybrid (Rapid Recompile) netlist for partition "Top" Info (35006): Using previously generated Fitter netlist for partition "acl_iface_partition" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/system.v Line: 344 Info (35007): Using synthesis netlist for partition "system_acl_iface_hps_hps_io_border:border" File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io.v Line: 101 Info (35002): Resolved and merged 3 partition(s) Warning (16710): Found unconnected port system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_ready on design partition acl_iface_partition -- port will be tied to GND Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1043 node(s), including 284 DDIO, 7 PLL, 0 transceiver and 64 LCELL Info (35048): Found 9 ports with constant drivers. For more information, refer to the Partition Merger report Info (35047): Found 621 ports with no fan-out. For more information, refer to the Partition Merger report Warning (35016): Found partition port(s) not driving logic, possibly wasting area Warning (35018): Partition port "system:the_system|system_acl_iface:acl_iface|kernel_mem1_debugaccess", driven by node "~GND", does not drive logic Warning (35018): Partition port "system:the_system|system_acl_iface:acl_iface|kernel_mem0_debugaccess", driven by node "~GND", does not drive logic Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[0]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[29]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[28]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[27]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[26]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[25]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[24]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[23]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[22]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[21]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[20]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[19]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[18]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[17]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[16]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[15]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[14]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35017): Partition port "system:the_system|system_acl_iface:acl_iface|acl_internal_snoop_data[13]", driven by node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_memory_bank_divider:acl_memory_bank_divider|snoop_adapter:acl_snoop_adapter_0|dcfifo:dcfifo_component|dcfifo_e8n1:auto_generated|altsyncram_1b81:fifo_ram|ram_block11a0", does not drive logic File: /home/ml6417/debug/int_add_mult/int_add_mult/db/altsyncram_1b81.tdf Line: 40 Warning (35039): Only the first 20 ports are reported. For a full list of ports, refer to the Partition Warnings panel in the Partition Merge report Info (21057): Implemented 31525 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins Info (21059): Implemented 76 output pins Info (21060): Implemented 102 bidirectional pins Info (21061): Implemented 28100 logic cells Info (21064): Implemented 1782 RAM segments Info (21065): Implemented 7 PLLs Info (21066): Implemented 2 delay-locked loops Warning (20013): Ignored 1 assignments for entity "altsyncram_00n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_00n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_0aj1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_0aj1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g3n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g3n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_k9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_k9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_s5j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_s5j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_u2n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_u2n1 -tag quartusii was ignored Info: Quartus Prime Partition Merge was successful. 0 errors, 38 warnings Info: Peak virtual memory: 2319 megabytes Info: Processing ended: Wed Jun 2 20:58:08 2021 Info: Elapsed time: 00:00:51 Info: Total CPU time (on all processors): 00:00:48 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:58:10 2021 Info: Command: quartus_cdb -t scripts/post_module.tcl quartus_cdb top top Info: Quartus(args): quartus_cdb top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post_module.tcl script Info (23030): Evaluation of Tcl script scripts/post_module.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1284 megabytes Info: Processing ended: Wed Jun 2 20:58:10 2021 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 20:58:11 2021 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off top -c top --recompile=on Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: qfit2_default_script.tcl version: #1 Info: Project = top Info: Revision = top Info (20030): Parallel compilation is enabled and will use 16 of the 20 processors detected Info (119006): Selected device 5CSXFC6D6F31C6 for design "top" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Warning (21300): LOCKED port on the PLL is not properly connected on instance "system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i|general[0].gpll". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready. Info (119042): Found RAM instances in design that are actually implemented as ROM because the write logic is always disabled. One such instance is listed below for example. Info (119043): Atom "system:the_system|int_add_mult_system:int_add_mult_system|lsu_ic_top:lsu_ic_top|lsu_swdimm_token_ring:GEN_SW_DIMM.lsu_ic|lsu_token_ring:lsu_token_ring|scfifo:GEN_MULTIPLE_PORT.GEN_ENABLE_WRITE_RING.GEN_WR_ROOT_FIFOS[1].wr_fifo|scfifo_ddc1:auto_generated|a_dpfifo_7v91:dpfifo|altsyncram_nnn1:FIFOram|ram_block1a317" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Critical Warning (12819): Rapid Recompile may ignore modifying, adding, or deleting SDC files. Info (12845): SDC file was added: /home/ml6417/debug/int_add_mult/int_add_mult/top_guaranteed_timing.sdc. Info (13184): Fitter is attempting to run in Rapid Recompile mode. Info (13190): Rapid Recompile is not required for 1 out of 4 design partition(s): Info (13191): Rapid Recompile is not required to preserve results for design partition "acl_iface_partition" because of user-set partition settings Info (13185): Rapid Recompile is attempting to preserve results from 1 out of 4 design partition(s): Info (13186): Partition "Top" -- Placement preservation requested is 70.55 percent. Info (13187): Rapid Recompile has disengaged on 2 out of 4 design partition(s) prior to fitting: Info (13188): Partition "system_acl_iface_hps_hps_io_border:border" -- Rapid Recompile not attempted: incremental compilation databases not found. Info (13188): Partition "hard_block:auto_generated_inst" -- Rapid Recompile disengaged: recompiling hard block partition because other partition(s) disengaged. Info (171122): Fitter is preserving placement for 76.54 percent of the design from 1 Post-Fit partition(s) and 0 imported partition(s) of 4 total partition(s) Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_scc_clk|reset_reg[13]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_scc_clk|reset_reg[1]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_scc_clk|reset_reg[0]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_scc_clk|reset_reg[2]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_scc_clk|reset_reg[3]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_avl_clk|reset_reg[1]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Warning (176050): Can't implement Global Signal option for node "system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_reset:ureset|system_acl_iface_fpga_sdram_p0_reset_sync:ureset_avl_clk|reset_reg[0]~feeder" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_p0_reset_sync.v Line: 48 Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (184020): Starting Fitter periphery placement operations Warning (177007): PLL(s) placed in location FRACTIONALPLL_X89_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll1~FRACTIONAL_PLL Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y15_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL Info (11178): Promoted 14 clocks (13 global, 1 regional) Info (11162): system:the_system|altera_reset_controller:rst_controller_003|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 with 4248 fanout uses global clock CLKCTRL_G3 Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays Info (11162): system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|clock~CLKENA0_I with 2894 fanout uses global clock CLKCTRL_G6 Info (11162): system:the_system|int_add_mult_system:int_add_mult_system|int_add_top_wrapper:int_add|int_add_function_wrapper:kernel|resetn~CLKENA0_I with 1218 fanout uses global clock CLKCTRL_G15 Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays Info (11162): system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|clock~CLKENA0_I with 2930 fanout uses global clock CLKCTRL_G7 Info (11162): system:the_system|int_add_mult_system:int_add_mult_system|int_mult_top_wrapper:int_mult|int_mult_function_wrapper:kernel|resetn~CLKENA0_I with 1244 fanout uses global clock CLKCTRL_G2 Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 6 fanout uses global clock CLKCTRL_G8 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[1]~CLKENA0 with 106 fanout uses global clock CLKCTRL_G4 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[4]~CLKENA0 with 96 fanout uses regional clock CLKCTRL_R36 Info (11177): Node drives Regional Clock Region 1 from (0, 0) to (44, 36) Info (11186): Fanout is constrained to region from (34, 31) to (44, 31) Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[2]~CLKENA0 with 9419 fanout uses global clock CLKCTRL_G1 Info (11162): fpga_clk_50~inputCLKENA0 with 4016 fanout uses global clock CLKCTRL_G0 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll_afi_clk~CLKENA0 with 9 fanout uses global clock CLKCTRL_G9 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll_avl_clk~CLKENA0 with 728 fanout uses global clock CLKCTRL_G10 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_pll0:pll0|pll_config_clk~CLKENA0 with 277 fanout uses global clock CLKCTRL_G11 Info (11162): system:the_system|system_acl_iface:acl_iface|system_acl_iface_pll:pll|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 924 fanout uses global clock CLKCTRL_G5 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:03 Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_e8n1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* Info (332165): Entity dcfifo_img1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_uu8:dffpipe13|dffe14a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_tu8:dffpipe10|dffe11a* Info (332104): Reading SDC File: 'top.sdc' Warning (332174): Ignored filter at top.sdc(5): altera_reserved_tck could not be matched with a port or pin or register or keeper or net or combinational node or node File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332049): Ignored create_clock at top.sdc(5): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Info (332050): create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tdi could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tck could not be matched with a clock File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(7): altera_reserved_tms could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332174): Ignored filter at top.sdc(8): altera_reserved_tdo could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Info (332050): set_output_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdo] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332174): Ignored filter at top.sdc(14): fpga_button_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332049): Ignored set_false_path at top.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Info (332050): set_false_path -from [get_ports {fpga_button_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332174): Ignored filter at top.sdc(15): fpga_button_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332049): Ignored set_false_path at top.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Info (332050): set_false_path -from [get_ports {fpga_button_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332174): Ignored filter at top.sdc(16): fpga_dipsw_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332049): Ignored set_false_path at top.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332174): Ignored filter at top.sdc(17): fpga_dipsw_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332049): Ignored set_false_path at top.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332174): Ignored filter at top.sdc(18): fpga_dipsw_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332049): Ignored set_false_path at top.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332174): Ignored filter at top.sdc(19): fpga_dipsw_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332049): Ignored set_false_path at top.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332174): Ignored filter at top.sdc(20): fpga_led_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332049): Ignored set_false_path at top.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[0]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332174): Ignored filter at top.sdc(21): fpga_led_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332049): Ignored set_false_path at top.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[1]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332174): Ignored filter at top.sdc(22): fpga_led_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332049): Ignored set_false_path at top.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[2]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332174): Ignored filter at top.sdc(23): fpga_led_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332049): Ignored set_false_path at top.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[3]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332174): Ignored filter at top.sdc(26): hps_emac1_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332049): Ignored set_false_path at top.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332174): Ignored filter at top.sdc(27): hps_emac1_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332049): Ignored set_false_path at top.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332174): Ignored filter at top.sdc(28): hps_emac1_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332049): Ignored set_false_path at top.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332174): Ignored filter at top.sdc(29): hps_emac1_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332049): Ignored set_false_path at top.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332174): Ignored filter at top.sdc(30): hps_emac1_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332049): Ignored set_false_path at top.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332174): Ignored filter at top.sdc(31): hps_emac1_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332049): Ignored set_false_path at top.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDC}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332174): Ignored filter at top.sdc(32): hps_emac1_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332049): Ignored set_false_path at top.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CTL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332174): Ignored filter at top.sdc(33): hps_qspi_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332049): Ignored set_false_path at top.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332174): Ignored filter at top.sdc(34): hps_qspi_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332049): Ignored set_false_path at top.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332174): Ignored filter at top.sdc(35): hps_sdio_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332049): Ignored set_false_path at top.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332174): Ignored filter at top.sdc(36): hps_usb1_STP could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332049): Ignored set_false_path at top.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_STP}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332174): Ignored filter at top.sdc(37): hps_spim0_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332049): Ignored set_false_path at top.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332174): Ignored filter at top.sdc(38): hps_spim0_MOSI could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332049): Ignored set_false_path at top.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_MOSI}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332174): Ignored filter at top.sdc(39): hps_spim0_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332049): Ignored set_false_path at top.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332174): Ignored filter at top.sdc(40): hps_uart0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332049): Ignored set_false_path at top.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports {hps_uart0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332174): Ignored filter at top.sdc(41): hps_can0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332049): Ignored set_false_path at top.sdc(41): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Info (332050): set_false_path -from * -to [get_ports {hps_can0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332174): Ignored filter at top.sdc(42): hps_trace_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332049): Ignored set_false_path at top.sdc(42): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Info (332050): set_false_path -from * -to [get_ports {hps_trace_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332174): Ignored filter at top.sdc(43): hps_trace_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332049): Ignored set_false_path at top.sdc(43): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332174): Ignored filter at top.sdc(44): hps_trace_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332049): Ignored set_false_path at top.sdc(44): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332174): Ignored filter at top.sdc(45): hps_trace_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332049): Ignored set_false_path at top.sdc(45): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332174): Ignored filter at top.sdc(46): hps_trace_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332049): Ignored set_false_path at top.sdc(46): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332174): Ignored filter at top.sdc(47): hps_trace_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332049): Ignored set_false_path at top.sdc(47): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332174): Ignored filter at top.sdc(48): hps_trace_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332049): Ignored set_false_path at top.sdc(48): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332174): Ignored filter at top.sdc(49): hps_trace_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332049): Ignored set_false_path at top.sdc(49): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332174): Ignored filter at top.sdc(50): hps_trace_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332049): Ignored set_false_path at top.sdc(50): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332174): Ignored filter at top.sdc(52): hps_emac1_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332049): Ignored set_false_path at top.sdc(52): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDIO}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332174): Ignored filter at top.sdc(53): hps_qspi_IO0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332049): Ignored set_false_path at top.sdc(53): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332174): Ignored filter at top.sdc(54): hps_qspi_IO1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332049): Ignored set_false_path at top.sdc(54): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332174): Ignored filter at top.sdc(55): hps_qspi_IO2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332049): Ignored set_false_path at top.sdc(55): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332174): Ignored filter at top.sdc(56): hps_qspi_IO3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332049): Ignored set_false_path at top.sdc(56): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332174): Ignored filter at top.sdc(57): hps_sdio_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332049): Ignored set_false_path at top.sdc(57): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CMD}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332174): Ignored filter at top.sdc(58): hps_sdio_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332049): Ignored set_false_path at top.sdc(58): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332174): Ignored filter at top.sdc(59): hps_sdio_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332049): Ignored set_false_path at top.sdc(59): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332174): Ignored filter at top.sdc(60): hps_sdio_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332049): Ignored set_false_path at top.sdc(60): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332174): Ignored filter at top.sdc(61): hps_sdio_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332049): Ignored set_false_path at top.sdc(61): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332174): Ignored filter at top.sdc(62): hps_usb1_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332049): Ignored set_false_path at top.sdc(62): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332174): Ignored filter at top.sdc(63): hps_usb1_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332049): Ignored set_false_path at top.sdc(63): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332174): Ignored filter at top.sdc(64): hps_usb1_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332049): Ignored set_false_path at top.sdc(64): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332174): Ignored filter at top.sdc(65): hps_usb1_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332049): Ignored set_false_path at top.sdc(65): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332174): Ignored filter at top.sdc(66): hps_usb1_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332049): Ignored set_false_path at top.sdc(66): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332174): Ignored filter at top.sdc(67): hps_usb1_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332049): Ignored set_false_path at top.sdc(67): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332174): Ignored filter at top.sdc(68): hps_usb1_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332049): Ignored set_false_path at top.sdc(68): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332174): Ignored filter at top.sdc(69): hps_usb1_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332049): Ignored set_false_path at top.sdc(69): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332174): Ignored filter at top.sdc(70): hps_i2c0_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332049): Ignored set_false_path at top.sdc(70): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SDA}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332174): Ignored filter at top.sdc(71): hps_i2c0_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332049): Ignored set_false_path at top.sdc(71): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SCL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332174): Ignored filter at top.sdc(72): hps_gpio_GPIO09 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332049): Ignored set_false_path at top.sdc(72): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO09}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332174): Ignored filter at top.sdc(73): hps_gpio_GPIO35 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332049): Ignored set_false_path at top.sdc(73): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO35}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332174): Ignored filter at top.sdc(74): hps_gpio_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332049): Ignored set_false_path at top.sdc(74): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO41}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332174): Ignored filter at top.sdc(75): hps_gpio_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332049): Ignored set_false_path at top.sdc(75): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO42}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332174): Ignored filter at top.sdc(76): hps_gpio_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332049): Ignored set_false_path at top.sdc(76): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO43}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332174): Ignored filter at top.sdc(77): hps_gpio_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(77): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO44}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(79): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Info (332050): set_false_path -from [get_ports {hps_emac1_MDIO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Warning (332049): Ignored set_false_path at top.sdc(80): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Info (332050): set_false_path -from [get_ports {hps_qspi_IO0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Warning (332049): Ignored set_false_path at top.sdc(81): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Info (332050): set_false_path -from [get_ports {hps_qspi_IO1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Warning (332049): Ignored set_false_path at top.sdc(82): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Info (332050): set_false_path -from [get_ports {hps_qspi_IO2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Warning (332049): Ignored set_false_path at top.sdc(83): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Info (332050): set_false_path -from [get_ports {hps_qspi_IO3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Warning (332049): Ignored set_false_path at top.sdc(84): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Info (332050): set_false_path -from [get_ports {hps_sdio_CMD}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Warning (332049): Ignored set_false_path at top.sdc(85): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Info (332050): set_false_path -from [get_ports {hps_sdio_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Warning (332049): Ignored set_false_path at top.sdc(86): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Info (332050): set_false_path -from [get_ports {hps_sdio_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Warning (332049): Ignored set_false_path at top.sdc(87): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Info (332050): set_false_path -from [get_ports {hps_sdio_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Warning (332049): Ignored set_false_path at top.sdc(88): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Info (332050): set_false_path -from [get_ports {hps_sdio_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Warning (332049): Ignored set_false_path at top.sdc(89): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Info (332050): set_false_path -from [get_ports {hps_usb1_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Warning (332049): Ignored set_false_path at top.sdc(90): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Info (332050): set_false_path -from [get_ports {hps_usb1_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Warning (332049): Ignored set_false_path at top.sdc(91): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Info (332050): set_false_path -from [get_ports {hps_usb1_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Warning (332049): Ignored set_false_path at top.sdc(92): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Info (332050): set_false_path -from [get_ports {hps_usb1_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Warning (332049): Ignored set_false_path at top.sdc(93): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Info (332050): set_false_path -from [get_ports {hps_usb1_D4}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Warning (332049): Ignored set_false_path at top.sdc(94): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Info (332050): set_false_path -from [get_ports {hps_usb1_D5}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Warning (332049): Ignored set_false_path at top.sdc(95): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Info (332050): set_false_path -from [get_ports {hps_usb1_D6}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Warning (332049): Ignored set_false_path at top.sdc(96): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Info (332050): set_false_path -from [get_ports {hps_usb1_D7}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Warning (332049): Ignored set_false_path at top.sdc(97): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Info (332050): set_false_path -from [get_ports {hps_i2c0_SDA}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Warning (332049): Ignored set_false_path at top.sdc(98): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Info (332050): set_false_path -from [get_ports {hps_i2c0_SCL}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Warning (332049): Ignored set_false_path at top.sdc(99): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO09}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Warning (332049): Ignored set_false_path at top.sdc(100): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO35}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Warning (332049): Ignored set_false_path at top.sdc(101): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO41}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Warning (332049): Ignored set_false_path at top.sdc(102): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO42}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Warning (332049): Ignored set_false_path at top.sdc(103): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO43}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Warning (332049): Ignored set_false_path at top.sdc(104): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO44}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Warning (332174): Ignored filter at top.sdc(106): hps_usb1_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332049): Ignored set_false_path at top.sdc(106): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Info (332050): set_false_path -from [get_ports {hps_usb1_CLK}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332174): Ignored filter at top.sdc(107): hps_usb1_DIR could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332049): Ignored set_false_path at top.sdc(107): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Info (332050): set_false_path -from [get_ports {hps_usb1_DIR}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332174): Ignored filter at top.sdc(108): hps_usb1_NXT could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332049): Ignored set_false_path at top.sdc(108): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Info (332050): set_false_path -from [get_ports {hps_usb1_NXT}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332174): Ignored filter at top.sdc(109): hps_spim0_MISO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332049): Ignored set_false_path at top.sdc(109): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Info (332050): set_false_path -from [get_ports {hps_spim0_MISO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332174): Ignored filter at top.sdc(110): hps_uart0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332049): Ignored set_false_path at top.sdc(110): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Info (332050): set_false_path -from [get_ports {hps_uart0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332174): Ignored filter at top.sdc(111): hps_can0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332049): Ignored set_false_path at top.sdc(111): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Info (332050): set_false_path -from [get_ports {hps_can0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332174): Ignored filter at top.sdc(158): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332049): Ignored set_false_path at top.sdc(158): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332174): Ignored filter at top.sdc(159): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Warning (332049): Ignored set_false_path at top.sdc(159): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Warning (332174): Ignored filter at top.sdc(163): system:the_system|system_fpga_sdram:fpga_sdram|altera_mem_if_hard_memory_controller_top_cyclonev:c0|hmc_inst~FF_* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 163 Warning (332049): Ignored set_min_delay at top.sdc(163): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 163 Info (332050): set_min_delay -from system:the_system|system_fpga_sdram:fpga_sdram|altera_mem_if_hard_memory_controller_top_cyclonev:c0|hmc_inst~FF_* 0.5 File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 163 Warning (332049): Ignored set_min_delay at top.sdc(164): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 164 Info (332050): set_min_delay -to system:the_system|system_fpga_sdram:fpga_sdram|altera_mem_if_hard_memory_controller_top_cyclonev:c0|hmc_inst~FF_* 1.0 File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 164 Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin} -divide_by 512 -multiply_by 11479 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]} -divide_by 8 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|vco0ph[0]} -divide_by 4 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|vco0ph[0]} -divide_by 4 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|refclkin} -multiply_by 24 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 18 -phase 9.98 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 54 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -phase 270.00 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/mem_org_mode.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/hps_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332174): Ignored filter at hps_sdram_p0.sdc(551): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(551): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Info (332050): set_false_path -from ${prefix}|*s0|* -to [get_clocks $local_pll_write_clk] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332174): Ignored filter at hps_sdram_p0.sdc(552): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(552): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info (332050): set_false_path -from [get_clocks $local_pll_write_clk] -to ${prefix}|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc' Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(1): hps_io_hps_io_emac0_inst_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(1): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(2): hps_io_hps_io_emac0_inst_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(2): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(3): hps_io_hps_io_emac0_inst_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(3): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(4): hps_io_hps_io_emac0_inst_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(4): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(5): hps_io_hps_io_emac0_inst_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(5): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(6): hps_io_hps_io_emac0_inst_RXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(7): hps_io_hps_io_emac0_inst_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_MDIO] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDIO] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(9): hps_io_hps_io_emac0_inst_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(9): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDC] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(10): hps_io_hps_io_emac0_inst_RX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(10): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CTL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(11): hps_io_hps_io_emac0_inst_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(11): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CTL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(12): hps_io_hps_io_emac0_inst_RX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(12): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CLK] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(13): hps_io_hps_io_emac0_inst_RXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(13): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(14): hps_io_hps_io_emac0_inst_RXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(15): hps_io_hps_io_emac0_inst_RXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(16): hps_io_hps_io_sdio_inst_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(18): hps_io_hps_io_sdio_inst_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(20): hps_io_hps_io_sdio_inst_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(22): hps_io_hps_io_sdio_inst_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(23): hps_io_hps_io_sdio_inst_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(24): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(25): hps_io_hps_io_sdio_inst_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(25): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(27): hps_io_hps_io_uart0_inst_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Info (332050): set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(28): hps_io_hps_io_uart0_inst_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(29): hps_io_hps_io_i2c0_inst_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(31): hps_io_hps_io_i2c0_inst_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(33): hps_io_hps_io_gpio_inst_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO41] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO41] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(35): hps_io_hps_io_gpio_inst_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO42] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO42] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(37): hps_io_hps_io_gpio_inst_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO43] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO43] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(39): hps_io_hps_io_gpio_inst_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO44] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO44] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'top_post.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'top_guaranteed_timing.sdc' Warning (332060): Node: async_counter_30:AC30|count_a[14] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register async_counter_30:AC30|count_b[0] is being clocked by async_counter_30:AC30|count_a[14] Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[3] to: clkout Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_REFCLK_SELECT from: clkin[1] to: clkout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[0] to: lvdsclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|cmd_port_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_764 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_7 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_6 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_5 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_4 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_3 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_2 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_1 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_0 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga_light_weight|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2821 Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): From: the_system|acl_iface|hps|hps_io|border|i2c0_inst|i2c_clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|i2c0_inst~FF_3393 Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[3] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_ck (Rise) has uncertainty 0.226 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 50 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 20.000 fpga_clk_50 Info (332111): 2.500 fpga_memory_mem_ck Info (332111): 2.500 fpga_memory_mem_ck_n Info (332111): 2.500 fpga_memory_mem_dqs[0]_IN Info (332111): 2.500 fpga_memory_mem_dqs[0]_OUT Info (332111): 2.500 fpga_memory_mem_dqs[1]_IN Info (332111): 2.500 fpga_memory_mem_dqs[1]_OUT Info (332111): 2.500 fpga_memory_mem_dqs[2]_IN Info (332111): 2.500 fpga_memory_mem_dqs[2]_OUT Info (332111): 2.500 fpga_memory_mem_dqs[3]_IN Info (332111): 2.500 fpga_memory_mem_dqs[3]_OUT Info (332111): 2.500 fpga_memory_mem_dqs_n[0]_OUT Info (332111): 2.500 fpga_memory_mem_dqs_n[1]_OUT Info (332111): 2.500 fpga_memory_mem_dqs_n[2]_OUT Info (332111): 2.500 fpga_memory_mem_dqs_n[3]_OUT Info (332111): 300.000 i2c_scl Info (332111): 2.500 memory_mem_ck Info (332111): 2.500 memory_mem_ck_n Info (332111): 2.500 memory_mem_dqs[0]_IN Info (332111): 2.500 memory_mem_dqs[0]_OUT Info (332111): 2.500 memory_mem_dqs[1]_IN Info (332111): 2.500 memory_mem_dqs[1]_OUT Info (332111): 2.500 memory_mem_dqs[2]_IN Info (332111): 2.500 memory_mem_dqs[2]_OUT Info (332111): 2.500 memory_mem_dqs[3]_IN Info (332111): 2.500 memory_mem_dqs[3]_OUT Info (332111): 2.500 memory_mem_dqs[4]_IN Info (332111): 2.500 memory_mem_dqs[4]_OUT Info (332111): 2.500 memory_mem_dqs_n[0]_OUT Info (332111): 2.500 memory_mem_dqs_n[1]_OUT Info (332111): 2.500 memory_mem_dqs_n[2]_OUT Info (332111): 2.500 memory_mem_dqs_n[3]_OUT Info (332111): 2.500 memory_mem_dqs_n[4]_OUT Info (332111): 2.500 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332111): 2.500 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk Info (332111): 7.136 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332111): 3.568 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332111): 3.568 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332111): 9.812 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332111): 9.812 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332111): 0.892 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info (332111): 0.833 the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0] Info (332111): 2.500 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332111): 2.500 the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk Info (332111): 15.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332111): 45.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332111): 2.500 the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock Info (332111): 2.500 the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock Info (332111): 3.333 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332111): 10.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176218): Packed 736 registers into blocks of type EC Info (11798): Fitter preparation operations ending: elapsed time is 00:01:16 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:18 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:01:14 Info (170193): Fitter routing operations beginning Info (170239): Router is attempting to preserve 72.90 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements. Info (170195): Router estimated average interconnect usage is 12% of the available device resources Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22 Info (188005): Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the "Estimated Delay Added for Hold Timing" section in the Fitter report. Info (170194): Fitter routing operations ending: elapsed time is 00:13:33 Info (11888): Total time spent on timing analysis during the Fitter is 51.88 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11801): Fitter post-fit operations ending: elapsed time is 00:01:00 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info (169186): Following groups of pins have the same dynamic on-chip termination control Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin memory_mem_dqs_n[4] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin memory_mem_dqs_n[3] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin memory_mem_dqs_n[2] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin memory_mem_dqs_n[1] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin memory_mem_dqs_n[0] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 75 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin memory_mem_dqs[4] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin memory_mem_dqs[3] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin memory_mem_dqs[2] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin memory_mem_dqs[1] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin memory_mem_dqs[0] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 74 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[39] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[38] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[37] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[36] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[35] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[34] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[33] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[32] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[31] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[30] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[29] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[28] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[27] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[26] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[25] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[24] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[23] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[22] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[21] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[20] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[19] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[18] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[17] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[16] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[15] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[14] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[13] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[12] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[11] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[10] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[9] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[8] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[7] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[6] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[21] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[20] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[19] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[18] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[17] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[16] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[15] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[14] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[13] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[12] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[11] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[10] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[0] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[1] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[2] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[3] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[4] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[5] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[6] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[7] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[8] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[9] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[22] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[23] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[24] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[25] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[26] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[27] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[28] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[29] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[30] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin fpga_memory_mem_dq[31] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 110 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[0] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin fpga_memory_mem_dqs[0] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[1] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin fpga_memory_mem_dqs[1] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[2] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin fpga_memory_mem_dqs[2] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[3] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc Info (169066): Type bi-directional pin fpga_memory_mem_dqs[3] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 112 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[4] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin fpga_memory_mem_dqs_n[0] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct Info (169066): Type bi-directional pin memory_mem_dq[5] uses the SSTL-15 Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 73 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin fpga_memory_mem_dqs_n[1] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin fpga_memory_mem_dqs_n[2] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (169185): Following pins have the same dynamic on-chip termination control: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_p0:p0|system_acl_iface_fpga_sdram_p0_acv_hard_memphy:umemphy|system_acl_iface_fpga_sdram_p0_acv_hard_io_pads:uio_pads|system_acl_iface_fpga_sdram_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|diff_dtc_bar Info (169066): Type bi-directional pin fpga_memory_mem_dqs_n[3] uses the Differential 1.5-V SSTL Class I I/O standard File: /home/ml6417/debug/int_add_mult/int_add_mult/top.v Line: 114 Info (144001): Generated suppressed messages file /home/ml6417/debug/int_add_mult/int_add_mult/top.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 265 warnings Info: Peak virtual memory: 5141 megabytes Info: Processing ended: Wed Jun 2 21:17:40 2021 Info: Elapsed time: 00:19:29 Info: Total CPU time (on all processors): 00:27:42 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:17:44 2021 Info: Command: quartus_cdb -t scripts/post_module.tcl quartus_fit top top Info: Quartus(args): quartus_fit top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post_module.tcl script Info (23030): Evaluation of Tcl script scripts/post_module.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1284 megabytes Info: Processing ended: Wed Jun 2 21:17:44 2021 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 Info (293026): Skipped module Rapid Recompile Assembler due to the assignment FLOW_DISABLE_ASSEMBLER Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:17:45 2021 Info: Command: quartus_sta top -c top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: qsta_default_script.tcl version: #2 Warning (20013): Ignored 1 assignments for entity "altsyncram_00n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_00n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_0aj1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_0aj1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g3n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g3n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_k9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_k9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_s5j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_s5j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_u2n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_u2n1 -tag quartusii was ignored Info (20030): Parallel compilation is enabled and will use 16 of the 20 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_e8n1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* Info (332165): Entity dcfifo_img1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_uu8:dffpipe13|dffe14a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_tu8:dffpipe10|dffe11a* Info (332104): Reading SDC File: 'top.sdc' Warning (332174): Ignored filter at top.sdc(5): altera_reserved_tck could not be matched with a port or pin or register or keeper or net or combinational node or node File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332049): Ignored create_clock at top.sdc(5): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Info (332050): create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tdi could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tck could not be matched with a clock File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(7): altera_reserved_tms could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332174): Ignored filter at top.sdc(8): altera_reserved_tdo could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Info (332050): set_output_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdo] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332174): Ignored filter at top.sdc(14): fpga_button_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332049): Ignored set_false_path at top.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Info (332050): set_false_path -from [get_ports {fpga_button_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332174): Ignored filter at top.sdc(15): fpga_button_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332049): Ignored set_false_path at top.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Info (332050): set_false_path -from [get_ports {fpga_button_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332174): Ignored filter at top.sdc(16): fpga_dipsw_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332049): Ignored set_false_path at top.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332174): Ignored filter at top.sdc(17): fpga_dipsw_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332049): Ignored set_false_path at top.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332174): Ignored filter at top.sdc(18): fpga_dipsw_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332049): Ignored set_false_path at top.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332174): Ignored filter at top.sdc(19): fpga_dipsw_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332049): Ignored set_false_path at top.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332174): Ignored filter at top.sdc(20): fpga_led_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332049): Ignored set_false_path at top.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[0]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332174): Ignored filter at top.sdc(21): fpga_led_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332049): Ignored set_false_path at top.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[1]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332174): Ignored filter at top.sdc(22): fpga_led_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332049): Ignored set_false_path at top.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[2]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332174): Ignored filter at top.sdc(23): fpga_led_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332049): Ignored set_false_path at top.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[3]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332174): Ignored filter at top.sdc(26): hps_emac1_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332049): Ignored set_false_path at top.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332174): Ignored filter at top.sdc(27): hps_emac1_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332049): Ignored set_false_path at top.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332174): Ignored filter at top.sdc(28): hps_emac1_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332049): Ignored set_false_path at top.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332174): Ignored filter at top.sdc(29): hps_emac1_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332049): Ignored set_false_path at top.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332174): Ignored filter at top.sdc(30): hps_emac1_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332049): Ignored set_false_path at top.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332174): Ignored filter at top.sdc(31): hps_emac1_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332049): Ignored set_false_path at top.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDC}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332174): Ignored filter at top.sdc(32): hps_emac1_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332049): Ignored set_false_path at top.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CTL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332174): Ignored filter at top.sdc(33): hps_qspi_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332049): Ignored set_false_path at top.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332174): Ignored filter at top.sdc(34): hps_qspi_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332049): Ignored set_false_path at top.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332174): Ignored filter at top.sdc(35): hps_sdio_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332049): Ignored set_false_path at top.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332174): Ignored filter at top.sdc(36): hps_usb1_STP could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332049): Ignored set_false_path at top.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_STP}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332174): Ignored filter at top.sdc(37): hps_spim0_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332049): Ignored set_false_path at top.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332174): Ignored filter at top.sdc(38): hps_spim0_MOSI could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332049): Ignored set_false_path at top.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_MOSI}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332174): Ignored filter at top.sdc(39): hps_spim0_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332049): Ignored set_false_path at top.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332174): Ignored filter at top.sdc(40): hps_uart0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332049): Ignored set_false_path at top.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports {hps_uart0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332174): Ignored filter at top.sdc(41): hps_can0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332049): Ignored set_false_path at top.sdc(41): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Info (332050): set_false_path -from * -to [get_ports {hps_can0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332174): Ignored filter at top.sdc(42): hps_trace_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332049): Ignored set_false_path at top.sdc(42): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Info (332050): set_false_path -from * -to [get_ports {hps_trace_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332174): Ignored filter at top.sdc(43): hps_trace_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332049): Ignored set_false_path at top.sdc(43): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332174): Ignored filter at top.sdc(44): hps_trace_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332049): Ignored set_false_path at top.sdc(44): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332174): Ignored filter at top.sdc(45): hps_trace_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332049): Ignored set_false_path at top.sdc(45): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332174): Ignored filter at top.sdc(46): hps_trace_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332049): Ignored set_false_path at top.sdc(46): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332174): Ignored filter at top.sdc(47): hps_trace_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332049): Ignored set_false_path at top.sdc(47): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332174): Ignored filter at top.sdc(48): hps_trace_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332049): Ignored set_false_path at top.sdc(48): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332174): Ignored filter at top.sdc(49): hps_trace_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332049): Ignored set_false_path at top.sdc(49): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332174): Ignored filter at top.sdc(50): hps_trace_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332049): Ignored set_false_path at top.sdc(50): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332174): Ignored filter at top.sdc(52): hps_emac1_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332049): Ignored set_false_path at top.sdc(52): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDIO}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332174): Ignored filter at top.sdc(53): hps_qspi_IO0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332049): Ignored set_false_path at top.sdc(53): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332174): Ignored filter at top.sdc(54): hps_qspi_IO1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332049): Ignored set_false_path at top.sdc(54): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332174): Ignored filter at top.sdc(55): hps_qspi_IO2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332049): Ignored set_false_path at top.sdc(55): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332174): Ignored filter at top.sdc(56): hps_qspi_IO3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332049): Ignored set_false_path at top.sdc(56): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332174): Ignored filter at top.sdc(57): hps_sdio_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332049): Ignored set_false_path at top.sdc(57): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CMD}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332174): Ignored filter at top.sdc(58): hps_sdio_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332049): Ignored set_false_path at top.sdc(58): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332174): Ignored filter at top.sdc(59): hps_sdio_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332049): Ignored set_false_path at top.sdc(59): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332174): Ignored filter at top.sdc(60): hps_sdio_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332049): Ignored set_false_path at top.sdc(60): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332174): Ignored filter at top.sdc(61): hps_sdio_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332049): Ignored set_false_path at top.sdc(61): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332174): Ignored filter at top.sdc(62): hps_usb1_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332049): Ignored set_false_path at top.sdc(62): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332174): Ignored filter at top.sdc(63): hps_usb1_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332049): Ignored set_false_path at top.sdc(63): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332174): Ignored filter at top.sdc(64): hps_usb1_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332049): Ignored set_false_path at top.sdc(64): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332174): Ignored filter at top.sdc(65): hps_usb1_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332049): Ignored set_false_path at top.sdc(65): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332174): Ignored filter at top.sdc(66): hps_usb1_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332049): Ignored set_false_path at top.sdc(66): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332174): Ignored filter at top.sdc(67): hps_usb1_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332049): Ignored set_false_path at top.sdc(67): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332174): Ignored filter at top.sdc(68): hps_usb1_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332049): Ignored set_false_path at top.sdc(68): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332174): Ignored filter at top.sdc(69): hps_usb1_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332049): Ignored set_false_path at top.sdc(69): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332174): Ignored filter at top.sdc(70): hps_i2c0_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332049): Ignored set_false_path at top.sdc(70): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SDA}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332174): Ignored filter at top.sdc(71): hps_i2c0_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332049): Ignored set_false_path at top.sdc(71): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SCL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332174): Ignored filter at top.sdc(72): hps_gpio_GPIO09 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332049): Ignored set_false_path at top.sdc(72): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO09}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332174): Ignored filter at top.sdc(73): hps_gpio_GPIO35 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332049): Ignored set_false_path at top.sdc(73): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO35}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332174): Ignored filter at top.sdc(74): hps_gpio_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332049): Ignored set_false_path at top.sdc(74): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO41}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332174): Ignored filter at top.sdc(75): hps_gpio_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332049): Ignored set_false_path at top.sdc(75): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO42}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332174): Ignored filter at top.sdc(76): hps_gpio_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332049): Ignored set_false_path at top.sdc(76): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO43}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332174): Ignored filter at top.sdc(77): hps_gpio_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(77): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO44}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(79): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Info (332050): set_false_path -from [get_ports {hps_emac1_MDIO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Warning (332049): Ignored set_false_path at top.sdc(80): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Info (332050): set_false_path -from [get_ports {hps_qspi_IO0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Warning (332049): Ignored set_false_path at top.sdc(81): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Info (332050): set_false_path -from [get_ports {hps_qspi_IO1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Warning (332049): Ignored set_false_path at top.sdc(82): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Info (332050): set_false_path -from [get_ports {hps_qspi_IO2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Warning (332049): Ignored set_false_path at top.sdc(83): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Info (332050): set_false_path -from [get_ports {hps_qspi_IO3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Warning (332049): Ignored set_false_path at top.sdc(84): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Info (332050): set_false_path -from [get_ports {hps_sdio_CMD}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Warning (332049): Ignored set_false_path at top.sdc(85): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Info (332050): set_false_path -from [get_ports {hps_sdio_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Warning (332049): Ignored set_false_path at top.sdc(86): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Info (332050): set_false_path -from [get_ports {hps_sdio_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Warning (332049): Ignored set_false_path at top.sdc(87): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Info (332050): set_false_path -from [get_ports {hps_sdio_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Warning (332049): Ignored set_false_path at top.sdc(88): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Info (332050): set_false_path -from [get_ports {hps_sdio_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Warning (332049): Ignored set_false_path at top.sdc(89): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Info (332050): set_false_path -from [get_ports {hps_usb1_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Warning (332049): Ignored set_false_path at top.sdc(90): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Info (332050): set_false_path -from [get_ports {hps_usb1_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Warning (332049): Ignored set_false_path at top.sdc(91): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Info (332050): set_false_path -from [get_ports {hps_usb1_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Warning (332049): Ignored set_false_path at top.sdc(92): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Info (332050): set_false_path -from [get_ports {hps_usb1_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Warning (332049): Ignored set_false_path at top.sdc(93): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Info (332050): set_false_path -from [get_ports {hps_usb1_D4}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Warning (332049): Ignored set_false_path at top.sdc(94): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Info (332050): set_false_path -from [get_ports {hps_usb1_D5}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Warning (332049): Ignored set_false_path at top.sdc(95): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Info (332050): set_false_path -from [get_ports {hps_usb1_D6}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Warning (332049): Ignored set_false_path at top.sdc(96): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Info (332050): set_false_path -from [get_ports {hps_usb1_D7}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Warning (332049): Ignored set_false_path at top.sdc(97): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Info (332050): set_false_path -from [get_ports {hps_i2c0_SDA}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Warning (332049): Ignored set_false_path at top.sdc(98): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Info (332050): set_false_path -from [get_ports {hps_i2c0_SCL}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Warning (332049): Ignored set_false_path at top.sdc(99): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO09}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Warning (332049): Ignored set_false_path at top.sdc(100): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO35}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Warning (332049): Ignored set_false_path at top.sdc(101): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO41}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Warning (332049): Ignored set_false_path at top.sdc(102): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO42}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Warning (332049): Ignored set_false_path at top.sdc(103): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO43}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Warning (332049): Ignored set_false_path at top.sdc(104): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO44}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Warning (332174): Ignored filter at top.sdc(106): hps_usb1_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332049): Ignored set_false_path at top.sdc(106): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Info (332050): set_false_path -from [get_ports {hps_usb1_CLK}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332174): Ignored filter at top.sdc(107): hps_usb1_DIR could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332049): Ignored set_false_path at top.sdc(107): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Info (332050): set_false_path -from [get_ports {hps_usb1_DIR}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332174): Ignored filter at top.sdc(108): hps_usb1_NXT could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332049): Ignored set_false_path at top.sdc(108): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Info (332050): set_false_path -from [get_ports {hps_usb1_NXT}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332174): Ignored filter at top.sdc(109): hps_spim0_MISO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332049): Ignored set_false_path at top.sdc(109): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Info (332050): set_false_path -from [get_ports {hps_spim0_MISO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332174): Ignored filter at top.sdc(110): hps_uart0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332049): Ignored set_false_path at top.sdc(110): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Info (332050): set_false_path -from [get_ports {hps_uart0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332174): Ignored filter at top.sdc(111): hps_can0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332049): Ignored set_false_path at top.sdc(111): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Info (332050): set_false_path -from [get_ports {hps_can0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332174): Ignored filter at top.sdc(158): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332049): Ignored set_false_path at top.sdc(158): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332174): Ignored filter at top.sdc(159): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Warning (332049): Ignored set_false_path at top.sdc(159): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin} -divide_by 512 -multiply_by 11479 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]} -divide_by 8 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|vco0ph[0]} -divide_by 4 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|vco0ph[0]} -divide_by 4 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|refclkin} -divide_by 2 -multiply_by 48 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 18 -phase 9.98 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 54 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -phase 270.00 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 2 -multiply_by 12 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/mem_org_mode.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/hps_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Warning (332174): Ignored filter at hps_sdram_p0.sdc(551): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(551): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Info (332050): set_false_path -from ${prefix}|*s0|* -to [get_clocks $local_pll_write_clk] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332174): Ignored filter at hps_sdram_p0.sdc(552): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(552): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info (332050): set_false_path -from [get_clocks $local_pll_write_clk] -to ${prefix}|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info: Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc' Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(1): hps_io_hps_io_emac0_inst_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(1): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(2): hps_io_hps_io_emac0_inst_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(2): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(3): hps_io_hps_io_emac0_inst_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(3): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(4): hps_io_hps_io_emac0_inst_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(4): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(5): hps_io_hps_io_emac0_inst_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(5): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(6): hps_io_hps_io_emac0_inst_RXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(7): hps_io_hps_io_emac0_inst_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_MDIO] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDIO] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(9): hps_io_hps_io_emac0_inst_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(9): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDC] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(10): hps_io_hps_io_emac0_inst_RX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(10): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CTL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(11): hps_io_hps_io_emac0_inst_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(11): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CTL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(12): hps_io_hps_io_emac0_inst_RX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(12): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CLK] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(13): hps_io_hps_io_emac0_inst_RXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(13): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(14): hps_io_hps_io_emac0_inst_RXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(15): hps_io_hps_io_emac0_inst_RXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(16): hps_io_hps_io_sdio_inst_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(18): hps_io_hps_io_sdio_inst_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(20): hps_io_hps_io_sdio_inst_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(22): hps_io_hps_io_sdio_inst_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(23): hps_io_hps_io_sdio_inst_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(24): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(25): hps_io_hps_io_sdio_inst_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(25): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(27): hps_io_hps_io_uart0_inst_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Info (332050): set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(28): hps_io_hps_io_uart0_inst_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(29): hps_io_hps_io_i2c0_inst_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(31): hps_io_hps_io_i2c0_inst_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(33): hps_io_hps_io_gpio_inst_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO41] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO41] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(35): hps_io_hps_io_gpio_inst_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO42] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO42] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(37): hps_io_hps_io_gpio_inst_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO43] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO43] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(39): hps_io_hps_io_gpio_inst_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO44] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO44] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info: Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks Info (332104): Reading SDC File: 'top_post.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'top_guaranteed_timing.sdc' Warning: Executing OpenCL guaranteed timing flow - this timing report assumes the kernel PLL will be reconfigured to run at 97.3199998338 MHz. Info: Found refclk for kernel clk: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info: Found source for kernel clk: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] Info: kernel clk has period: 7.136 Info: kernel clk has multby: 1 and divby: 8 Info: Using adjusted multby: 7136 and divby: 82208 Info: Re-created kernel clock with period 10.276 Warning (332060): Node: async_counter_30:AC30|count_a[14] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register async_counter_30:AC30|count_b[11] is being clocked by async_counter_30:AC30|count_a[14] Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[3] to: clkout Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_REFCLK_SELECT from: clkin[1] to: clkout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[0] to: lvdsclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|cmd_port_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_764 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_7 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_6 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_5 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_4 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_3 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_2 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_1 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_0 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga_light_weight|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2821 Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): From: the_system|acl_iface|hps|hps_io|border|i2c0_inst|i2c_clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|i2c0_inst~FF_3393 Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[3] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_ck (Rise) has uncertainty 0.226 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1103.093 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1103.093 -1103.093 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): -163.983 -347.807 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): -19.104 -522.448 fpga_clk_50 Info (332119): -4.760 -9.513 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): -4.374 -4.374 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): -1.495 -2689.875 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.303 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.510 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.730 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 2.405 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 4.476 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332146): Worst-case hold slack is -1872.466 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1872.466 -56130.000 fpga_clk_50 Info (332119): -3.023 -3.023 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.143 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.197 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.240 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.290 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.294 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 0.295 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.307 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 0.325 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.326 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case recovery slack is -2.334 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.334 -9047.593 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): -1.403 -9.703 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 2.733 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.375 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 4.115 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 4.788 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 11.447 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 13.626 0.000 fpga_clk_50 Info (332119): 19.453 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case removal slack is 0.382 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.382 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.549 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.568 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.594 0.000 fpga_clk_50 Info (332119): 0.707 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.708 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.724 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.156 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 2.170 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332146): Worst-case minimum pulse width slack is 0.394 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.394 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.416 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0] Info (332119): 0.446 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info (332119): 0.531 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.608 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk Info (332119): 0.623 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.636 0.000 the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.354 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 1.666 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.662 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.698 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 3.755 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 3.897 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 6.264 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.615 0.000 fpga_clk_50 Info (332119): 21.643 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 149.900 0.000 i2c_scl Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332114): Report Metastability: Found 304 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.730 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.143 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 3.375 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.382 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (removal)} Info: Core: hps_sdram_p0 - Instance: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info: setup hold Info: Address Command (Slow 1100mV 85C Model) | 0.485 0.481 Info: Bus Turnaround Time (Slow 1100mV 85C Model) | 2.765 -- Info: Core (Slow 1100mV 85C Model) | 1.73 0.143 Info: Core Recovery/Removal (Slow 1100mV 85C Model) | 3.375 0.382 Info: DQS vs CK (Slow 1100mV 85C Model) | 0.438 0.266 Info: Postamble (Slow 1100mV 85C Model) | 0.515 0.515 Info: Read Capture (Slow 1100mV 85C Model) | 0.241 0.194 Info: Write (Slow 1100mV 85C Model) | 0.254 0.254 Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.303 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.197 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.447 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.724 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (removal)} Info: Core: system_acl_iface_fpga_sdram_p0 - Instance: the_system|acl_iface|fpga_sdram Info: setup hold Info: Address Command (Slow 1100mV 85C Model) | 0.413 0.549 Info: Bus Turnaround Time (Slow 1100mV 85C Model) | 3.454 -- Info: Core (Slow 1100mV 85C Model) | 1.303 0.197 Info: Core Recovery/Removal (Slow 1100mV 85C Model) | 11.447 0.724 Info: DQS vs CK (Slow 1100mV 85C Model) | 0.494 0.433 Info: Postamble (Slow 1100mV 85C Model) | 0.565 0.565 Info: Read Capture (Slow 1100mV 85C Model) | 0.246 0.199 Info: Write (Slow 1100mV 85C Model) | 0.238 0.28 Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: async_counter_30:AC30|count_a[14] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register async_counter_30:AC30|count_b[11] is being clocked by async_counter_30:AC30|count_a[14] Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[3] to: clkout Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_REFCLK_SELECT from: clkin[1] to: clkout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[0] to: lvdsclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|cmd_port_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_764 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_7 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_6 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_5 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_4 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_3 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_2 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_1 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_0 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga_light_weight|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2821 Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): From: the_system|acl_iface|hps|hps_io|border|i2c0_inst|i2c_clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|i2c0_inst~FF_3393 Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[3] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_ck (Rise) has uncertainty 0.226 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1103.100 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1103.100 -1103.100 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): -163.936 -344.604 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): -18.144 -494.301 fpga_clk_50 Info (332119): -4.799 -9.593 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): -4.374 -4.374 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): -1.355 -2121.476 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.301 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.727 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 1.735 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 2.510 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 4.537 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332146): Worst-case hold slack is -1872.825 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1872.825 -56148.586 fpga_clk_50 Info (332119): -2.921 -2.921 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.162 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.212 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.230 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.246 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.278 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.282 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 0.290 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 0.300 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.306 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case recovery slack is -2.324 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.324 -8963.803 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): -1.347 -9.320 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 2.862 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.468 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 4.127 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 5.016 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 11.565 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 13.932 0.000 fpga_clk_50 Info (332119): 19.564 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case removal slack is 0.373 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.373 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.507 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.522 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.523 0.000 fpga_clk_50 Info (332119): 0.642 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.655 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.689 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.077 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 2.190 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332146): Worst-case minimum pulse width slack is 0.394 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.394 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.416 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0] Info (332119): 0.446 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info (332119): 0.472 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.613 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk Info (332119): 0.630 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.644 0.000 the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.336 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 1.666 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.643 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.678 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 3.736 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 3.875 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 6.245 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.591 0.000 fpga_clk_50 Info (332119): 21.650 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 149.927 0.000 i2c_scl Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332114): Report Metastability: Found 304 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.727 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.162 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 3.468 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.373 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (removal)} Info: Core: hps_sdram_p0 - Instance: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info: setup hold Info: Address Command (Slow 1100mV 0C Model) | 0.471 0.482 Info: Bus Turnaround Time (Slow 1100mV 0C Model) | 2.79 -- Info: Core (Slow 1100mV 0C Model) | 1.727 0.162 Info: Core Recovery/Removal (Slow 1100mV 0C Model) | 3.468 0.373 Info: DQS vs CK (Slow 1100mV 0C Model) | 0.446 0.301 Info: Postamble (Slow 1100mV 0C Model) | 0.5 0.5 Info: Read Capture (Slow 1100mV 0C Model) | 0.257 0.21 Info: Write (Slow 1100mV 0C Model) | 0.266 0.266 Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.301 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.230 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.565 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.689 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (removal)} Info: Core: system_acl_iface_fpga_sdram_p0 - Instance: the_system|acl_iface|fpga_sdram Info: setup hold Info: Address Command (Slow 1100mV 0C Model) | 0.403 0.548 Info: Bus Turnaround Time (Slow 1100mV 0C Model) | 3.492 -- Info: Core (Slow 1100mV 0C Model) | 1.301 0.23 Info: Core Recovery/Removal (Slow 1100mV 0C Model) | 11.565 0.689 Info: DQS vs CK (Slow 1100mV 0C Model) | 0.506 0.464 Info: Postamble (Slow 1100mV 0C Model) | 0.554 0.554 Info: Read Capture (Slow 1100mV 0C Model) | 0.262 0.214 Info: Write (Slow 1100mV 0C Model) | 0.257 0.291 Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Warning (332060): Node: async_counter_30:AC30|count_a[14] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register async_counter_30:AC30|count_b[11] is being clocked by async_counter_30:AC30|count_a[14] Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[3] to: clkout Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_REFCLK_SELECT from: clkin[1] to: clkout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[0] to: lvdsclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|cmd_port_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_764 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_7 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_6 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_5 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_4 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_3 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_2 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_1 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_0 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga_light_weight|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2821 Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): From: the_system|acl_iface|hps|hps_io|border|i2c0_inst|i2c_clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|i2c0_inst~FF_3393 Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[3] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_ck (Rise) has uncertainty 0.226 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1103.307 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1103.307 -1103.307 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): -163.878 -327.784 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): -12.201 -327.324 fpga_clk_50 Info (332119): -4.848 -9.687 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): -4.603 -4.603 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.345 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.813 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 2.110 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 4.249 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 4.691 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.824 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332146): Worst-case hold slack is -1875.291 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1875.291 -56269.810 fpga_clk_50 Info (332119): -1.687 -1.687 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.084 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.156 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.164 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.170 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 0.173 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.174 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.176 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 0.180 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.184 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case recovery slack is 0.281 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.281 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.520 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 3.727 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 5.597 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 6.390 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 6.563 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 12.528 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 15.441 0.000 fpga_clk_50 Info (332119): 20.562 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case removal slack is 0.245 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.245 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.286 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.296 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.336 0.000 fpga_clk_50 Info (332119): 0.382 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.420 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.455 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.737 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.296 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332146): Worst-case minimum pulse width slack is 0.394 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.394 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.416 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0] Info (332119): 0.446 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info (332119): 0.793 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.883 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk Info (332119): 0.885 0.000 the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.891 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 1.461 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 1.666 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.784 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.809 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 3.875 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 4.016 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 6.382 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.775 0.000 fpga_clk_50 Info (332119): 22.021 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 149.643 0.000 i2c_scl Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332114): Report Metastability: Found 304 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 2.110 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.084 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 3.727 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.455 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (removal)} Info: Core: hps_sdram_p0 - Instance: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info: setup hold Info: Address Command (Fast 1100mV 85C Model) | 0.515 0.528 Info: Bus Turnaround Time (Fast 1100mV 85C Model) | 2.898 -- Info: Core (Fast 1100mV 85C Model) | 2.11 0.084 Info: Core Recovery/Removal (Fast 1100mV 85C Model) | 3.727 0.455 Info: DQS vs CK (Fast 1100mV 85C Model) | 0.523 0.377 Info: Postamble (Fast 1100mV 85C Model) | 0.592 0.592 Info: Read Capture (Fast 1100mV 85C Model) | 0.378 0.331 Info: Write (Fast 1100mV 85C Model) | 0.323 0.323 Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.813 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.156 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 12.528 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.245 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (removal)} Info: Core: system_acl_iface_fpga_sdram_p0 - Instance: the_system|acl_iface|fpga_sdram Info: setup hold Info: Address Command (Fast 1100mV 85C Model) | 0.496 0.609 Info: Bus Turnaround Time (Fast 1100mV 85C Model) | 3.719 -- Info: Core (Fast 1100mV 85C Model) | 1.813 0.156 Info: Core Recovery/Removal (Fast 1100mV 85C Model) | 12.528 0.245 Info: DQS vs CK (Fast 1100mV 85C Model) | 0.584 0.558 Info: Postamble (Fast 1100mV 85C Model) | 0.625 0.625 Info: Read Capture (Fast 1100mV 85C Model) | 0.376 0.329 Info: Write (Fast 1100mV 85C Model) | 0.337 0.337 Info: Analyzing Fast 1100mV 0C Model Warning (332060): Node: async_counter_30:AC30|count_a[14] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register async_counter_30:AC30|count_b[11] is being clocked by async_counter_30:AC30|count_a[14] Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_reg_file:sequencer_reg_file_inst|altsyncram:altsyncram_component|altsyncram_c9v1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama0~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama10~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama11~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama12~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama13~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama14~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama15~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama16~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama17~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama18~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama19~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama1~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama20~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama21~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama22~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama23~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama24~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama25~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama26~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama27~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama28~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama29~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama2~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama30~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama31~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama32~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama33~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama34~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama35~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama36~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama37~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama3~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama4~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama5~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama6~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama7~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama8~MEMORYREGOUT Info (332098): From: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~CLKMUX_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_fpga_sdram:fpga_sdram|system_acl_iface_fpga_sdram_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|sequencer_scc_reg_file:sequencer_scc_reg_file_inst|altdpram:altdpram_component|dpram_k3s1:auto_generated|lutrama9~MEMORYREGOUT Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[3] to: clkout Info (332098): Cell: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_REFCLK_SELECT from: clkin[1] to: clkout Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[0] to: lvdsclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll2_phy~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_LVDS_OUTPUT from: ccout[1] to: loaden Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|cmd_port_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_764 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_7 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_6 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_5 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|rd_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_4 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_0 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_3 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_1 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_2 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_2 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_1 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|f2sdram|wr_clk_3 to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|f2sdram~FF_0 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga_light_weight|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425 Info (332098): From: the_system|acl_iface|hps|fpga_interfaces|hps2fpga|clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2821 Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain from: dqsin to: dqsbusout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_in_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_out_delay_1 from: datain to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|phase_align_os from: muxsel to: dataout Info (332098): Cell: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated|ddio_outa[0] from: muxsel to: dataout Info (332098): From: the_system|acl_iface|hps|hps_io|border|i2c0_inst|i2c_clk to: system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|i2c0_inst~FF_3393 Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[3] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[0]_IN (Rise) to memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[1]_IN (Rise) to memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[2]_IN (Rise) to memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[3]_IN (Rise) to memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from memory_mem_dqs[4]_IN (Rise) to memory_mem_dqs[4]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Rise) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Hold clock transfer from the_system|acl_iface|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock (Fall) to memory_mem_dqs[4]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.380 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Rise) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Hold clock transfer from system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk (Fall) to memory_mem_dqs_n[4]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.210 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_ck (Rise) has uncertainty 0.226 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[0]_IN (Rise) to fpga_memory_mem_dqs[0]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[1]_IN (Rise) to fpga_memory_mem_dqs[1]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[2]_IN (Rise) to fpga_memory_mem_dqs[2]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from fpga_memory_mem_dqs[3]_IN (Rise) to fpga_memory_mem_dqs[3]_IN (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.160 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[0]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[1]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[2]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.260 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.230 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Rise) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|system_acl_iface_fpga_sdram_p0_sampling_clock (Fall) to fpga_memory_mem_dqs[3]_OUT (Fall) has uncertainty 0.000 that is less than the recommended uncertainty 0.200 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[0]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[1]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[2]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Rise) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Info (332172): Setup clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.250 Info (332172): Hold clock transfer from the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk (Fall) to fpga_memory_mem_dqs_n[3]_OUT (Rise) has uncertainty 0.000 that is less than the recommended uncertainty 0.240 Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -1103.311 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1103.311 -1103.311 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): -163.780 -327.451 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): -10.316 -275.727 fpga_clk_50 Info (332119): -4.847 -9.686 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): -4.606 -4.606 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.603 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.847 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 2.110 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 4.511 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 5.268 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.351 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332146): Worst-case hold slack is -1875.821 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1875.821 -56303.925 fpga_clk_50 Info (332119): -1.643 -1.643 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.077 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.124 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.142 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.145 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.151 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.158 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 0.162 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.164 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 0.170 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case recovery slack is 0.335 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.335 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 1.600 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 3.825 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 5.810 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 6.833 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 6.894 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 12.823 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 16.014 0.000 fpga_clk_50 Info (332119): 20.757 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332146): Worst-case removal slack is 0.251 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.251 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.257 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 0.266 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 0.273 0.000 fpga_clk_50 Info (332119): 0.341 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.358 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.428 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 0.649 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 1.239 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332146): Worst-case minimum pulse width slack is 0.394 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.394 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk Info (332119): 0.416 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0] Info (332119): 0.446 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info (332119): 0.786 0.000 the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.883 0.000 the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk Info (332119): 0.887 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk Info (332119): 0.894 0.000 system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps:hps|system_acl_iface_hps_hps_io:hps_io|system_acl_iface_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_avl_clk_write_clk Info (332119): 1.462 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info (332119): 1.666 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 3.784 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk Info (332119): 3.806 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk Info (332119): 3.878 0.000 the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 4.020 0.000 the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info (332119): 6.382 0.000 the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.781 0.000 fpga_clk_50 Info (332119): 22.025 0.000 the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk Info (332119): 149.632 0.000 i2c_scl Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk and destination clock: fpga_clk_50 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Warning (332009): The launch and latch times for the relationship between source clock: fpga_clk_50 and destination clock: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. Info (332114): Report Metastability: Found 304 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 2.110 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.077 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 3.825 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.428 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*}] [get_registers {{*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Core Recovery/Removal (removal)} Info: Core: hps_sdram_p0 - Instance: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Info: setup hold Info: Address Command (Fast 1100mV 0C Model) | 0.479 0.556 Info: Bus Turnaround Time (Fast 1100mV 0C Model) | 2.91 -- Info: Core (Fast 1100mV 0C Model) | 2.11 0.077 Info: Core Recovery/Removal (Fast 1100mV 0C Model) | 3.825 0.428 Info: DQS vs CK (Fast 1100mV 0C Model) | 0.524 0.4 Info: Postamble (Fast 1100mV 0C Model) | 0.603 0.603 Info: Read Capture (Fast 1100mV 0C Model) | 0.379 0.331 Info: Write (Fast 1100mV 0C Model) | 0.337 0.337 Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info (332115): Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.847 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -setup Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (setup)} Info (332115): Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.142 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -hold Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core (hold)} Info (332115): Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 12.823 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -recovery Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (recovery)} Info (332115): Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.251 Info (332115): -to [remove_from_collection [get_registers {*:the_system|*:acl_iface|*:fpga_sdram|*}] [get_registers {{*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:the_system|*:acl_iface|*:fpga_sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}]] Info (332115): -removal Info (332115): -npaths 10 Info (332115): -detail full_path Info (332115): -panel_name {the_system|acl_iface|fpga_sdram Core Recovery/Removal (removal)} Info: Core: system_acl_iface_fpga_sdram_p0 - Instance: the_system|acl_iface|fpga_sdram Info: setup hold Info: Address Command (Fast 1100mV 0C Model) | 0.465 0.613 Info: Bus Turnaround Time (Fast 1100mV 0C Model) | 3.721 -- Info: Core (Fast 1100mV 0C Model) | 1.847 0.142 Info: Core Recovery/Removal (Fast 1100mV 0C Model) | 12.823 0.251 Info: DQS vs CK (Fast 1100mV 0C Model) | 0.569 0.575 Info: Postamble (Fast 1100mV 0C Model) | 0.642 0.642 Info: Read Capture (Fast 1100mV 0C Model) | 0.38 0.332 Info: Write (Fast 1100mV 0C Model) | 0.339 0.339 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 337 warnings Info: Peak virtual memory: 2916 megabytes Info: Processing ended: Wed Jun 2 21:20:04 2021 Info: Elapsed time: 00:02:19 Info: Total CPU time (on all processors): 00:05:08 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:20:09 2021 Info: Command: quartus_cdb -t scripts/post_module.tcl quartus_sta top top Info: Quartus(args): quartus_sta top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post_module.tcl script Info (23030): Evaluation of Tcl script scripts/post_module.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1284 megabytes Info: Processing ended: Wed Jun 2 21:20:09 2021 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:20:11 2021 Info: Command: quartus_cdb -t scripts/post_flow.tcl recompile top top Info: Quartus(args): recompile top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post-flow script Info: Project name: top Info: Running PLL adjustment script Info: Revision name: top Info: Calculating maximum fmax... Info: Clock the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Info: Period: 10.276 Info: Restricted Fmax from STA: 140.92 Info: Setup slack: -1103.311 Info: Recovery slack: 4.115 Info: Minimum Pulse Width slack: 3.875 Info: Adjusted period: 1113.587 (+1103.311, Setup) Info: Fmax: 0.89 Info: Clock the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk Info: Period: 5.138 Info: Restricted Fmax from STA: 277.47 Info: Setup slack: -163.983 Info: Recovery slack: -1.403 Info: Minimum Pulse Width slack: 1.336 Info: Adjusted period: 169.121 (+163.983, Setup) Info: Fmax: 5.91 Info: Kernel Fmax determined to be 0.89 Info: Kernel PLL reference clock is: 50.0 MHz Info: Computing pll settings for 0.89 Info: Solving post-div vco 300.82 MHz from reference clock 50.0 MHz Info: Solving post-div vco 302.6 MHz from reference clock 50.0 MHz Info: Solving post-div vco 304.38 MHz from reference clock 50.0 MHz Info: Solving post-div vco 306.16 MHz from reference clock 50.0 MHz Info: Solving post-div vco 307.94 MHz from reference clock 50.0 MHz Info: Solving post-div vco 309.72 MHz from reference clock 50.0 MHz Info: Solving post-div vco 311.5 MHz from reference clock 50.0 MHz Info: Solving post-div vco 313.28 MHz from reference clock 50.0 MHz Info: Solving post-div vco 315.06 MHz from reference clock 50.0 MHz Info: Solving post-div vco 316.84 MHz from reference clock 50.0 MHz Info: Solving post-div vco 318.62 MHz from reference clock 50.0 MHz Info: Solving post-div vco 320.4 MHz from reference clock 50.0 MHz Info: Solving post-div vco 322.18 MHz from reference clock 50.0 MHz Info: Solving post-div vco 323.96 MHz from reference clock 50.0 MHz Info: Solving post-div vco 325.74 MHz from reference clock 50.0 MHz Info: Solving post-div vco 327.52 MHz from reference clock 50.0 MHz Info: Solving post-div vco 329.3 MHz from reference clock 50.0 MHz Info: Solving post-div vco 331.08 MHz from reference clock 50.0 MHz Info: Solving post-div vco 332.86 MHz from reference clock 50.0 MHz Info: Solving post-div vco 334.64 MHz from reference clock 50.0 MHz Info: Solving post-div vco 336.42 MHz from reference clock 50.0 MHz Info: Solving post-div vco 338.2 MHz from reference clock 50.0 MHz Info: Solving post-div vco 339.98 MHz from reference clock 50.0 MHz Info: Solving post-div vco 341.76 MHz from reference clock 50.0 MHz Info: Solving post-div vco 343.54 MHz from reference clock 50.0 MHz Info: Solving post-div vco 345.32 MHz from reference clock 50.0 MHz Info: Solving post-div vco 347.1 MHz from reference clock 50.0 MHz Info: Solving post-div vco 348.88 MHz from reference clock 50.0 MHz Info: Solving post-div vco 350.66 MHz from reference clock 50.0 MHz Info: Solving post-div vco 352.44 MHz from reference clock 50.0 MHz Info: Solving post-div vco 354.22 MHz from reference clock 50.0 MHz Info: Solving post-div vco 356.0 MHz from reference clock 50.0 MHz Info: Solving post-div vco 357.78 MHz from reference clock 50.0 MHz Info: Solving post-div vco 359.56 MHz from reference clock 50.0 MHz Info: Solving post-div vco 361.34 MHz from reference clock 50.0 MHz Info: Solving post-div vco 363.12 MHz from reference clock 50.0 MHz Info: Solving post-div vco 364.9 MHz from reference clock 50.0 MHz Info: Solving post-div vco 366.68 MHz from reference clock 50.0 MHz Info: Solving post-div vco 368.46 MHz from reference clock 50.0 MHz Info: Solving post-div vco 370.24 MHz from reference clock 50.0 MHz Info: Solving post-div vco 372.02 MHz from reference clock 50.0 MHz Info: Solving post-div vco 373.8 MHz from reference clock 50.0 MHz Info: Solving post-div vco 375.58 MHz from reference clock 50.0 MHz Info: Solving post-div vco 377.36 MHz from reference clock 50.0 MHz Info: Solving post-div vco 379.14 MHz from reference clock 50.0 MHz Info: Solving post-div vco 380.92 MHz from reference clock 50.0 MHz Info: Solving post-div vco 382.7 MHz from reference clock 50.0 MHz Info: Solving post-div vco 384.48 MHz from reference clock 50.0 MHz Info: Solving post-div vco 386.26 MHz from reference clock 50.0 MHz Info: Solving post-div vco 388.04 MHz from reference clock 50.0 MHz Info: Solving post-div vco 389.82 MHz from reference clock 50.0 MHz Info: Solving post-div vco 391.6 MHz from reference clock 50.0 MHz Info: Solving post-div vco 393.38 MHz from reference clock 50.0 MHz Info: Solving post-div vco 395.16 MHz from reference clock 50.0 MHz Info: Solving post-div vco 396.94 MHz from reference clock 50.0 MHz Info: Solving post-div vco 398.72 MHz from reference clock 50.0 MHz Info: Solving post-div vco 400.5 MHz from reference clock 50.0 MHz Info: Solving post-div vco 402.28 MHz from reference clock 50.0 MHz Info: Solving post-div vco 404.06 MHz from reference clock 50.0 MHz Info: Solved VCO for C 454: 404.059997201 8 1 1362309 4000 20 2 (vco m n k r cp div) Info: Computed PLL settings: fmax m n k c0 c1 r cp div Info: Computed PLL values: 0.889999993835 8 1 1362309 454 227 4000 20 2 Info: finfpd 50.0 Info: post-div fvco 404.059997201 Info: true fvco 808.119994402 Info: kernel_fmax 0.889999993835 Info: kernel2x_fmax 1.77999998767 Info: Found kernel int_add Info: Found kernel int_mult Info: Found 2 kernels Info: Overwriting kernel_pll atoms with: 8 1 1362309 454 227 4000 20 2 Info: Found kernel_pll: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll Info: Derived C0 : system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter Info: Verifying C0 exists, node_id = 41156 Info: Derived C1: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[1].output_counter Info: Verifying C1 exists, node_id = 41157 Info: Found node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll Info: Setting BOOL_PLL_M_CNT_BYPASS_EN to 0 Info: Setting INT_PLL_M_CNT_HI_DIV to 4 Info: Setting INT_PLL_M_CNT_LO_DIV to 4 Info: Setting BOOL_PLL_M_CNT_ODD_DIV_DUTY_EN to 0 Info: Setting BOOL_PLL_N_CNT_BYPASS_EN to 1 Info: Setting INT_PLL_N_CNT_HI_DIV to 256 Info: Setting INT_PLL_N_CNT_LO_DIV to 256 Info: Setting BOOL_PLL_N_CNT_ODD_DIV_DUTY_EN to 0 Info: Setting INT_PLL_BWCTRL to 4000 Info: Setting INT_PLL_CP_CURRENT to 20 Info: Setting INT_PLL_VCO_DIV to 2 Info: Setting UINT_PLL_FRACTIONAL_DIVISION to 1362309 Info: Found node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter Info: Setting BOOL_DPRIO0_CNT_BYPASS_EN to 0 Info: Setting INT_DPRIO0_CNT_HI_DIV to 227 Info: Setting INT_DPRIO0_CNT_LO_DIV to 227 Info: Setting BOOL_DPRIO0_CNT_ODD_DIV_EVEN_DUTY_EN to 0 Info: Found node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[1].output_counter Info: Setting BOOL_DPRIO0_CNT_BYPASS_EN to 0 Info: Setting INT_DPRIO0_CNT_HI_DIV to 114 Info: Setting INT_DPRIO0_CNT_LO_DIV to 113 Info: Setting BOOL_DPRIO0_CNT_ODD_DIV_EVEN_DUTY_EN to 1 Info: Parameters for node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll Info: bool_pll_m_cnt_bypass_en: 0 Info: int_pll_m_cnt_hi_div: 4 Info: int_pll_m_cnt_lo_div: 4 Info: bool_pll_m_cnt_odd_div_duty_en: 0 Info: bool_pll_n_cnt_bypass_en: 1 Info: int_pll_n_cnt_hi_div: 256 Info: int_pll_n_cnt_lo_div: 256 Info: bool_pll_n_cnt_odd_div_duty_en: 0 Info: int_pll_bwctrl: 4000 Info: int_pll_cp_current: 20 Info: int_pll_vco_div: 2 Info: uint_pll_fractional_division: 1362309 Info: Parameters for node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter Info: bool_dprio0_cnt_bypass_en: 0 Info: int_dprio0_cnt_hi_div: 227 Info: int_dprio0_cnt_lo_div: 227 Info: bool_dprio0_cnt_odd_div_even_duty_en: 0 Info: Parameters for node: system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll:kernel_pll|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[1].output_counter Info: bool_dprio0_cnt_bypass_en: 0 Info: int_dprio0_cnt_hi_div: 114 Info: int_dprio0_cnt_lo_div: 113 Info: bool_dprio0_cnt_odd_div_even_duty_en: 1 Info: ******************************************************************* Info: Running Quartus Prime MIF/HEX Update Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:20:29 2021 Info: Command: quartus_cdb top -c top --update_mif Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Warning (39023): Can't find Memory Initialization File NONE -- skipped updates for this file Warning (39023): Can't find Memory Initialization File system_acl_iface_fpga_sdram_s0_sequencer_mem.hex -- skipped updates for this file Critical Warning (127005): Memory depth (512) in the design file differs from memory depth (25) in the Memory Initialization File "/home/ml6417/debug/int_add_mult/int_add_mult/sys_description.hex" -- setting initial value for remaining addresses to 0 Info (39024): Processed the following Memory Initialization File(s) Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/pll_rom.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/pll_rom.hex Line: 0 Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/sys_description.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/sys_description.hex Line: 0 Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_AC_ROM.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_AC_ROM.hex Line: 0 Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_inst_ROM.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_inst_ROM.hex Line: 0 Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_AC_ROM.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_AC_ROM.hex Line: 0 Info (39025): Processed Memory Initialization File /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_inst_ROM.hex File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_fpga_sdram_s0_inst_ROM.hex Line: 0 Info: Quartus Prime MIF/HEX Update was successful. 0 errors, 3 warnings Info: Peak virtual memory: 1806 megabytes Info: Processing ended: Wed Jun 2 21:21:14 2021 Info: Elapsed time: 00:00:45 Info: Total CPU time (on all processors): 00:00:44 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:21:16 2021 Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Warning (20013): Ignored 1 assignments for entity "altsyncram_00n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_00n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_0aj1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_0aj1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g3n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g3n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_k9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_k9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_s5j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_s5j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_u2n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_u2n1 -tag quartusii was ignored Info (115030): Assembler is generating device programming files Info (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not required Info: Quartus Prime Assembler was successful. 0 errors, 14 warnings Info: Peak virtual memory: 1462 megabytes Info: Processing ended: Wed Jun 2 21:21:54 2021 Info: Elapsed time: 00:00:38 Info: Total CPU time (on all processors): 00:00:36 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:21:55 2021 Info: Command: quartus_cdb -t scripts/post_module.tcl quartus_asm top top Info: Quartus(args): quartus_asm top top Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: Running post_module.tcl script Info (23030): Evaluation of Tcl script scripts/post_module.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1284 megabytes Info: Processing ended: Wed Jun 2 21:21:56 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 Info: Launching sta with report script /mnt/applications/altera/15.1/hld/ip/board/bsp/failing_clocks.tcl Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition Info: Processing started: Wed Jun 2 21:21:57 2021 Info: Command: quartus_sta top -c top --report_script=/mnt/applications/altera/15.1/hld/ip/board/bsp/failing_clocks.tcl Info: Using INI file /home/ml6417/debug/int_add_mult/int_add_mult/quartus.ini Info: qsta_default_script.tcl version: #2 Info (293032): Detected changes in source files. Info (293027): Source file: /home/ml6417/debug/int_add_mult/int_add_mult/top_guaranteed_timing.sdc has changed. Warning (20013): Ignored 1 assignments for entity "altsyncram_00n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_00n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_0aj1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_0aj1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g3n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g3n1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_g9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_g9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_k9j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_k9j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_s5j1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_s5j1 -tag quartusii was ignored Warning (20013): Ignored 1 assignments for entity "altsyncram_u2n1" -- entity does not exist in design Warning (20014): Assignment for entity set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL_COMPILATION -entity altsyncram_u2n1 -tag quartusii was ignored Info (20030): Parallel compilation is enabled and will use 16 of the 20 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity dcfifo_e8n1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* Info (332165): Entity dcfifo_img1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_uu8:dffpipe13|dffe14a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_tu8:dffpipe10|dffe11a* Info (332104): Reading SDC File: 'top.sdc' Warning (332174): Ignored filter at top.sdc(5): altera_reserved_tck could not be matched with a port or pin or register or keeper or net or combinational node or node File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332049): Ignored create_clock at top.sdc(5): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Info (332050): create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 5 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tdi could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(6): altera_reserved_tck could not be matched with a clock File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332049): Ignored set_input_delay at top.sdc(6): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 6 Warning (332174): Ignored filter at top.sdc(7): altera_reserved_tms could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332049): Ignored set_input_delay at top.sdc(7): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 7 Warning (332174): Ignored filter at top.sdc(8): altera_reserved_tdo could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Info (332050): set_output_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdo] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332049): Ignored set_output_delay at top.sdc(8): Argument -clock is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 8 Warning (332174): Ignored filter at top.sdc(14): fpga_button_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332049): Ignored set_false_path at top.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Info (332050): set_false_path -from [get_ports {fpga_button_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 14 Warning (332174): Ignored filter at top.sdc(15): fpga_button_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332049): Ignored set_false_path at top.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Info (332050): set_false_path -from [get_ports {fpga_button_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 15 Warning (332174): Ignored filter at top.sdc(16): fpga_dipsw_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332049): Ignored set_false_path at top.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 16 Warning (332174): Ignored filter at top.sdc(17): fpga_dipsw_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332049): Ignored set_false_path at top.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 17 Warning (332174): Ignored filter at top.sdc(18): fpga_dipsw_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332049): Ignored set_false_path at top.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 18 Warning (332174): Ignored filter at top.sdc(19): fpga_dipsw_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332049): Ignored set_false_path at top.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Info (332050): set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 19 Warning (332174): Ignored filter at top.sdc(20): fpga_led_pio[0] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332049): Ignored set_false_path at top.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[0]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 20 Warning (332174): Ignored filter at top.sdc(21): fpga_led_pio[1] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332049): Ignored set_false_path at top.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[1]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 21 Warning (332174): Ignored filter at top.sdc(22): fpga_led_pio[2] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332049): Ignored set_false_path at top.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[2]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 22 Warning (332174): Ignored filter at top.sdc(23): fpga_led_pio[3] could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332049): Ignored set_false_path at top.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Info (332050): set_false_path -from * -to [get_ports {fpga_led_pio[3]}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 23 Warning (332174): Ignored filter at top.sdc(26): hps_emac1_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332049): Ignored set_false_path at top.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 26 Warning (332174): Ignored filter at top.sdc(27): hps_emac1_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332049): Ignored set_false_path at top.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 27 Warning (332174): Ignored filter at top.sdc(28): hps_emac1_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332049): Ignored set_false_path at top.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 28 Warning (332174): Ignored filter at top.sdc(29): hps_emac1_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332049): Ignored set_false_path at top.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 29 Warning (332174): Ignored filter at top.sdc(30): hps_emac1_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332049): Ignored set_false_path at top.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TXD3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 30 Warning (332174): Ignored filter at top.sdc(31): hps_emac1_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332049): Ignored set_false_path at top.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDC}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 31 Warning (332174): Ignored filter at top.sdc(32): hps_emac1_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332049): Ignored set_false_path at top.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_TX_CTL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 32 Warning (332174): Ignored filter at top.sdc(33): hps_qspi_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332049): Ignored set_false_path at top.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 33 Warning (332174): Ignored filter at top.sdc(34): hps_qspi_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332049): Ignored set_false_path at top.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 34 Warning (332174): Ignored filter at top.sdc(35): hps_sdio_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332049): Ignored set_false_path at top.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 35 Warning (332174): Ignored filter at top.sdc(36): hps_usb1_STP could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332049): Ignored set_false_path at top.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_STP}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 36 Warning (332174): Ignored filter at top.sdc(37): hps_spim0_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332049): Ignored set_false_path at top.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 37 Warning (332174): Ignored filter at top.sdc(38): hps_spim0_MOSI could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332049): Ignored set_false_path at top.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_MOSI}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 38 Warning (332174): Ignored filter at top.sdc(39): hps_spim0_SS0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332049): Ignored set_false_path at top.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Info (332050): set_false_path -from * -to [get_ports {hps_spim0_SS0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 39 Warning (332174): Ignored filter at top.sdc(40): hps_uart0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332049): Ignored set_false_path at top.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports {hps_uart0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 40 Warning (332174): Ignored filter at top.sdc(41): hps_can0_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332049): Ignored set_false_path at top.sdc(41): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Info (332050): set_false_path -from * -to [get_ports {hps_can0_TX}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 41 Warning (332174): Ignored filter at top.sdc(42): hps_trace_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332049): Ignored set_false_path at top.sdc(42): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Info (332050): set_false_path -from * -to [get_ports {hps_trace_CLK}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 42 Warning (332174): Ignored filter at top.sdc(43): hps_trace_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332049): Ignored set_false_path at top.sdc(43): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 43 Warning (332174): Ignored filter at top.sdc(44): hps_trace_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332049): Ignored set_false_path at top.sdc(44): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 44 Warning (332174): Ignored filter at top.sdc(45): hps_trace_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332049): Ignored set_false_path at top.sdc(45): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 45 Warning (332174): Ignored filter at top.sdc(46): hps_trace_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332049): Ignored set_false_path at top.sdc(46): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 46 Warning (332174): Ignored filter at top.sdc(47): hps_trace_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332049): Ignored set_false_path at top.sdc(47): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 47 Warning (332174): Ignored filter at top.sdc(48): hps_trace_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332049): Ignored set_false_path at top.sdc(48): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 48 Warning (332174): Ignored filter at top.sdc(49): hps_trace_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332049): Ignored set_false_path at top.sdc(49): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 49 Warning (332174): Ignored filter at top.sdc(50): hps_trace_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332049): Ignored set_false_path at top.sdc(50): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Info (332050): set_false_path -from * -to [get_ports {hps_trace_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 50 Warning (332174): Ignored filter at top.sdc(52): hps_emac1_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332049): Ignored set_false_path at top.sdc(52): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Info (332050): set_false_path -from * -to [get_ports {hps_emac1_MDIO}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 52 Warning (332174): Ignored filter at top.sdc(53): hps_qspi_IO0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332049): Ignored set_false_path at top.sdc(53): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 53 Warning (332174): Ignored filter at top.sdc(54): hps_qspi_IO1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332049): Ignored set_false_path at top.sdc(54): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 54 Warning (332174): Ignored filter at top.sdc(55): hps_qspi_IO2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332049): Ignored set_false_path at top.sdc(55): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 55 Warning (332174): Ignored filter at top.sdc(56): hps_qspi_IO3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332049): Ignored set_false_path at top.sdc(56): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Info (332050): set_false_path -from * -to [get_ports {hps_qspi_IO3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 56 Warning (332174): Ignored filter at top.sdc(57): hps_sdio_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332049): Ignored set_false_path at top.sdc(57): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_CMD}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 57 Warning (332174): Ignored filter at top.sdc(58): hps_sdio_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332049): Ignored set_false_path at top.sdc(58): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 58 Warning (332174): Ignored filter at top.sdc(59): hps_sdio_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332049): Ignored set_false_path at top.sdc(59): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 59 Warning (332174): Ignored filter at top.sdc(60): hps_sdio_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332049): Ignored set_false_path at top.sdc(60): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 60 Warning (332174): Ignored filter at top.sdc(61): hps_sdio_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332049): Ignored set_false_path at top.sdc(61): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Info (332050): set_false_path -from * -to [get_ports {hps_sdio_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 61 Warning (332174): Ignored filter at top.sdc(62): hps_usb1_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332049): Ignored set_false_path at top.sdc(62): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D0}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 62 Warning (332174): Ignored filter at top.sdc(63): hps_usb1_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332049): Ignored set_false_path at top.sdc(63): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D1}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 63 Warning (332174): Ignored filter at top.sdc(64): hps_usb1_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332049): Ignored set_false_path at top.sdc(64): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D2}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 64 Warning (332174): Ignored filter at top.sdc(65): hps_usb1_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332049): Ignored set_false_path at top.sdc(65): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D3}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 65 Warning (332174): Ignored filter at top.sdc(66): hps_usb1_D4 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332049): Ignored set_false_path at top.sdc(66): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D4}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 66 Warning (332174): Ignored filter at top.sdc(67): hps_usb1_D5 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332049): Ignored set_false_path at top.sdc(67): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D5}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 67 Warning (332174): Ignored filter at top.sdc(68): hps_usb1_D6 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332049): Ignored set_false_path at top.sdc(68): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D6}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 68 Warning (332174): Ignored filter at top.sdc(69): hps_usb1_D7 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332049): Ignored set_false_path at top.sdc(69): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Info (332050): set_false_path -from * -to [get_ports {hps_usb1_D7}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 69 Warning (332174): Ignored filter at top.sdc(70): hps_i2c0_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332049): Ignored set_false_path at top.sdc(70): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SDA}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 70 Warning (332174): Ignored filter at top.sdc(71): hps_i2c0_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332049): Ignored set_false_path at top.sdc(71): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Info (332050): set_false_path -from * -to [get_ports {hps_i2c0_SCL}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 71 Warning (332174): Ignored filter at top.sdc(72): hps_gpio_GPIO09 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332049): Ignored set_false_path at top.sdc(72): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO09}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 72 Warning (332174): Ignored filter at top.sdc(73): hps_gpio_GPIO35 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332049): Ignored set_false_path at top.sdc(73): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO35}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 73 Warning (332174): Ignored filter at top.sdc(74): hps_gpio_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332049): Ignored set_false_path at top.sdc(74): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO41}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 74 Warning (332174): Ignored filter at top.sdc(75): hps_gpio_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332049): Ignored set_false_path at top.sdc(75): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO42}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 75 Warning (332174): Ignored filter at top.sdc(76): hps_gpio_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332049): Ignored set_false_path at top.sdc(76): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO43}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 76 Warning (332174): Ignored filter at top.sdc(77): hps_gpio_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(77): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Info (332050): set_false_path -from * -to [get_ports {hps_gpio_GPIO44}] File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 77 Warning (332049): Ignored set_false_path at top.sdc(79): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Info (332050): set_false_path -from [get_ports {hps_emac1_MDIO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 79 Warning (332049): Ignored set_false_path at top.sdc(80): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Info (332050): set_false_path -from [get_ports {hps_qspi_IO0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 80 Warning (332049): Ignored set_false_path at top.sdc(81): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Info (332050): set_false_path -from [get_ports {hps_qspi_IO1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 81 Warning (332049): Ignored set_false_path at top.sdc(82): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Info (332050): set_false_path -from [get_ports {hps_qspi_IO2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 82 Warning (332049): Ignored set_false_path at top.sdc(83): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Info (332050): set_false_path -from [get_ports {hps_qspi_IO3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 83 Warning (332049): Ignored set_false_path at top.sdc(84): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Info (332050): set_false_path -from [get_ports {hps_sdio_CMD}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 84 Warning (332049): Ignored set_false_path at top.sdc(85): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Info (332050): set_false_path -from [get_ports {hps_sdio_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 85 Warning (332049): Ignored set_false_path at top.sdc(86): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Info (332050): set_false_path -from [get_ports {hps_sdio_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 86 Warning (332049): Ignored set_false_path at top.sdc(87): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Info (332050): set_false_path -from [get_ports {hps_sdio_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 87 Warning (332049): Ignored set_false_path at top.sdc(88): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Info (332050): set_false_path -from [get_ports {hps_sdio_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 88 Warning (332049): Ignored set_false_path at top.sdc(89): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Info (332050): set_false_path -from [get_ports {hps_usb1_D0}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 89 Warning (332049): Ignored set_false_path at top.sdc(90): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Info (332050): set_false_path -from [get_ports {hps_usb1_D1}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 90 Warning (332049): Ignored set_false_path at top.sdc(91): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Info (332050): set_false_path -from [get_ports {hps_usb1_D2}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 91 Warning (332049): Ignored set_false_path at top.sdc(92): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Info (332050): set_false_path -from [get_ports {hps_usb1_D3}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 92 Warning (332049): Ignored set_false_path at top.sdc(93): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Info (332050): set_false_path -from [get_ports {hps_usb1_D4}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 93 Warning (332049): Ignored set_false_path at top.sdc(94): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Info (332050): set_false_path -from [get_ports {hps_usb1_D5}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 94 Warning (332049): Ignored set_false_path at top.sdc(95): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Info (332050): set_false_path -from [get_ports {hps_usb1_D6}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 95 Warning (332049): Ignored set_false_path at top.sdc(96): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Info (332050): set_false_path -from [get_ports {hps_usb1_D7}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 96 Warning (332049): Ignored set_false_path at top.sdc(97): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Info (332050): set_false_path -from [get_ports {hps_i2c0_SDA}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 97 Warning (332049): Ignored set_false_path at top.sdc(98): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Info (332050): set_false_path -from [get_ports {hps_i2c0_SCL}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 98 Warning (332049): Ignored set_false_path at top.sdc(99): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO09}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 99 Warning (332049): Ignored set_false_path at top.sdc(100): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO35}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 100 Warning (332049): Ignored set_false_path at top.sdc(101): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO41}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 101 Warning (332049): Ignored set_false_path at top.sdc(102): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO42}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 102 Warning (332049): Ignored set_false_path at top.sdc(103): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO43}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 103 Warning (332049): Ignored set_false_path at top.sdc(104): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Info (332050): set_false_path -from [get_ports {hps_gpio_GPIO44}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 104 Warning (332174): Ignored filter at top.sdc(106): hps_usb1_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332049): Ignored set_false_path at top.sdc(106): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Info (332050): set_false_path -from [get_ports {hps_usb1_CLK}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 106 Warning (332174): Ignored filter at top.sdc(107): hps_usb1_DIR could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332049): Ignored set_false_path at top.sdc(107): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Info (332050): set_false_path -from [get_ports {hps_usb1_DIR}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 107 Warning (332174): Ignored filter at top.sdc(108): hps_usb1_NXT could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332049): Ignored set_false_path at top.sdc(108): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Info (332050): set_false_path -from [get_ports {hps_usb1_NXT}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 108 Warning (332174): Ignored filter at top.sdc(109): hps_spim0_MISO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332049): Ignored set_false_path at top.sdc(109): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Info (332050): set_false_path -from [get_ports {hps_spim0_MISO}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 109 Warning (332174): Ignored filter at top.sdc(110): hps_uart0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332049): Ignored set_false_path at top.sdc(110): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Info (332050): set_false_path -from [get_ports {hps_uart0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 110 Warning (332174): Ignored filter at top.sdc(111): hps_can0_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332049): Ignored set_false_path at top.sdc(111): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Info (332050): set_false_path -from [get_ports {hps_can0_RX}] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 111 Warning (332174): Ignored filter at top.sdc(158): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332049): Ignored set_false_path at top.sdc(158): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter2x_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 158 Warning (332174): Ignored filter at top.sdc(159): system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Warning (332049): Ignored set_false_path at top.sdc(159): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Info (332050): set_false_path -from {system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|timer:counter|counter_a[15]} -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/top.sdc Line: 159 Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin} -divide_by 512 -multiply_by 11479 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]} -divide_by 454 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|vco0ph[0]} -divide_by 227 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[1].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[3].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|vco0ph[0]} -divide_by 11 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[4].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|vco0ph[0]} -divide_by 4 -duty_cycle 50.00 -name {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} {the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[2].output_counter|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|refclkin} -divide_by 2 -multiply_by 48 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|fpga_sdram|pll0|pll1~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 18 -phase 9.98 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 54 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -phase 270.00 -duty_cycle 50.00 -name {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|fpga_sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 2 -multiply_by 12 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 3 -duty_cycle 50.00 -name {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {the_system|acl_iface|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/mem_org_mode.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/hps_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: Initializing DDR database for CORE hps_sdram_p0 Info: Finding port-to-pin mapping for CORE: hps_sdram_p0 INSTANCE: the_system|acl_iface|hps|hps_io|border|hps_sdram_inst Warning (332174): Ignored filter at hps_sdram_p0.sdc(551): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(551): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Info (332050): set_false_path -from ${prefix}|*s0|* -to [get_clocks $local_pll_write_clk] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 551 Warning (332174): Ignored filter at hps_sdram_p0.sdc(552): *:the_system|*:acl_iface|*:hps|*:hps_io|*:border|*:hps_sdram_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Warning (332049): Ignored set_false_path at hps_sdram_p0.sdc(552): Argument is not an object ID File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info (332050): set_false_path -from [get_clocks $local_pll_write_clk] -to ${prefix}|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/hps_sdram_p0.sdc Line: 552 Info: Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc' Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(1): hps_io_hps_io_emac0_inst_TX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(1): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 1 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(2): hps_io_hps_io_emac0_inst_TXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(2): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 2 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(3): hps_io_hps_io_emac0_inst_TXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(3): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 3 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(4): hps_io_hps_io_emac0_inst_TXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(4): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 4 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(5): hps_io_hps_io_emac0_inst_TXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(5): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TXD3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 5 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(6): hps_io_hps_io_emac0_inst_RXD0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(6): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 6 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(7): hps_io_hps_io_emac0_inst_MDIO could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(7): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_MDIO] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 7 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(8): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDIO] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 8 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(9): hps_io_hps_io_emac0_inst_MDC could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(9): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_MDC] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 9 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(10): hps_io_hps_io_emac0_inst_RX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(10): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CTL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 10 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(11): hps_io_hps_io_emac0_inst_TX_CTL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(11): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac0_inst_TX_CTL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 11 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(12): hps_io_hps_io_emac0_inst_RX_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(12): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RX_CLK] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 12 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(13): hps_io_hps_io_emac0_inst_RXD1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(13): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 13 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(14): hps_io_hps_io_emac0_inst_RXD2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(14): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 14 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(15): hps_io_hps_io_emac0_inst_RXD3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(15): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Info (332050): set_false_path -from [get_ports hps_io_hps_io_emac0_inst_RXD3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 15 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(16): hps_io_hps_io_sdio_inst_CMD could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(16): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 16 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(17): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 17 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(18): hps_io_hps_io_sdio_inst_D0 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(18): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 18 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(19): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 19 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(20): hps_io_hps_io_sdio_inst_D1 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(20): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 20 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(21): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 21 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(22): hps_io_hps_io_sdio_inst_CLK could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(22): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 22 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(23): hps_io_hps_io_sdio_inst_D2 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(23): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 23 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(24): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 24 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(25): hps_io_hps_io_sdio_inst_D3 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(25): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Info (332050): set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 25 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(26): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 26 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(27): hps_io_hps_io_uart0_inst_RX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(27): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Info (332050): set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 27 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(28): hps_io_hps_io_uart0_inst_TX could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(28): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 28 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(29): hps_io_hps_io_i2c0_inst_SDA could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(29): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 29 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(30): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 30 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(31): hps_io_hps_io_i2c0_inst_SCL could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(31): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Info (332050): set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 31 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(32): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 32 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(33): hps_io_hps_io_gpio_inst_GPIO41 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(33): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO41] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 33 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(34): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO41] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 34 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(35): hps_io_hps_io_gpio_inst_GPIO42 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(35): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO42] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 35 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(36): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO42] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 36 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(37): hps_io_hps_io_gpio_inst_GPIO43 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(37): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO43] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 37 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(38): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO43] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 38 Warning (332174): Ignored filter at system_acl_iface_hps_hps_io_border.sdc(39): hps_io_hps_io_gpio_inst_GPIO44 could not be matched with a port File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(39): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Info (332050): set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO44] -to * File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 39 Warning (332049): Ignored set_false_path at system_acl_iface_hps_hps_io_border.sdc(40): Argument is an empty collection File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO44] File: /home/ml6417/debug/int_add_mult/int_add_mult/system/synthesis/submodules/system_acl_iface_hps_hps_io_border.sdc Line: 40 Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_hps_fpga_interfaces.sdc' Info (332104): Reading SDC File: 'system/synthesis/submodules/system_acl_iface_fpga_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: Initializing DDR database for CORE system_acl_iface_fpga_sdram_p0 Info: Finding port-to-pin mapping for CORE: system_acl_iface_fpga_sdram_p0 INSTANCE: the_system|acl_iface|fpga_sdram Info: Setting DQS clocks as inactive; use Report DDR to timing analyze DQS clocks Info (332104): Reading SDC File: 'top_post.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'top_guaranteed_timing.sdc' Warning: Executing OpenCL guaranteed timing flow - this timing report assumes the kernel PLL will be reconfigured to run at 0.889999993835 MHz. Info: Found refclk for kernel clk: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] Info: Found source for kernel clk: the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] Info: kernel clk has period: 404.996 Info: kernel clk has multby: 1 and divby: 454 Info: Using adjusted multby: 404996 and divby: 510112584 Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 2363 Integer overflow occured when trying to find the "multiply_by" or "divide_by" parameter of the generated clock the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Stack Trace: 0x3034eb: STA_CLOCK_MGR_IMPL::initialize_derived_clock(STA_CLOCK*) + 0xdab (tsm_sta) 0x305eb1: STA_CLOCK_MGR_IMPL::identify_ignored_clocks_recurse(STA_CLOCK*) + 0x51 (tsm_sta) 0x30620f: STA_CLOCK_MGR_IMPL::initialize_derived_clocks() + 0x7f (tsm_sta) 0x306b7a: STA_CLOCK_MGR_IMPL::STA_CLOCK_MGR_IMPL(TDB_NETLIST*, STA_REQUIREMENTS*, bool, bool) + 0x4ba (tsm_sta) 0x306e02: STA_CLOCK_MGR::create(TDB_NETLIST*, STA_REQUIREMENTS*, bool, bool) + 0x82 (tsm_sta) 0x28757b: STA_DB_MGR_IMPL::get_clock_mgr(bool) + 0xeb (tsm_sta) 0x33f833: sta_get_clock_info + 0x1293 (tsm_sta) 0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 0x536e7: TclEvalEx + 0x947 (tcl8.6) 0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6) 0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6) 0x36f598: sta_read_sdc_file(Tcl_Interp*, char const*, STA_REPORT_MGR*) + 0xc8 (tsm_sta) 0x36fdbc: sta_read_default_sdc_files(Tcl_Interp*, HDB_CMP_ACTION_PT_INSTANCE*, std::string const&, STA_REPORT_MGR*) + 0x4c (tsm_sta) 0x370e0b: sta_read_sdc + 0x1eb (tsm_sta) 0x4d671: TclInvokeStringCommand + 0x81 (tcl8.6) 0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 0x536e7: TclEvalEx + 0x947 (tcl8.6) 0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6) 0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6) 0x11c6f: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe) 0x18a50: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list > const&, bool, bool) + 0x594 (comp_qexe) 0x199fc: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list >*, bool) + 0x57e (comp_qexe) 0x3bfd4: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list >*, bool) + 0xde4 (comp_qcu) 0x1c226: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe) 0x19aaa: qsta_main(int, char const**) + 0xaa (quartus_sta) 0x3fe60: msg_main_thread(void*) + 0x10 (ccl_msg) 0x602c: thr_final_wrapper + 0xc (ccl_thr) 0x3ff1c: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg) 0x1e9c9: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (quartus_sta) 0x8def: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 0x63f2: thr_thread_wrapper + 0x15 (ccl_thr) 0x42122: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg) 0x22555: __libc_start_main + 0xf5 (c.so.6) End-trace Error: Error! ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error: Flow recompile (for project /home/ml6417/debug/int_add_mult/int_add_mult/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.