Info: Saving generation log to C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/SPRINT_OSI_S_generation.rpt
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\My_Designs\myproject_code\myproject\Source\Qsys_Systems\SPRINT_OSI_S.qsys --block-symbol-file --output-directory=C:\My_Designs\myproject_code\myproject\Source\Qsys_Systems\SPRINT_OSI_S --family="MAX 10" --part=10M40DAF484C7G
Progress: Loading Qsys_Systems/SPRINT_OSI_S.qsys
Progress: Reading input file
Progress: Adding CLK_132MHz [clock_source 18.1]
Progress: Parameterizing module CLK_132MHz
Progress: Adding CLK_33MHz [clock_source 18.1]
Progress: Parameterizing module CLK_33MHz
Progress: Adding DEBUG_REGISTERS_0 [DEBUG_REGISTERS 1.0]
Progress: Parameterizing module DEBUG_REGISTERS_0
Progress: Adding HOST_HSOT_Interface_0 [HOST_HSOT_Interface 1.0]
Progress: Parameterizing module HOST_HSOT_Interface_0
Progress: Adding JTAG_UART [altera_avalon_jtag_uart 18.1]
Progress: Parameterizing module JTAG_UART
Progress: Adding LINEARISE_DATA_CONTROL_0 [LINEARISE_DATA_CONTROL 2.0]
Progress: Parameterizing module LINEARISE_DATA_CONTROL_0
Progress: Adding NiosII [altera_nios2_gen2 18.1]
Progress: Parameterizing module NiosII
Progress: Adding PLL [altpll 18.1]
Progress: Parameterizing module PLL
Progress: Adding hsot_trace_fifo_0 [altera_avalon_fifo 18.1]
Progress: Parameterizing module hsot_trace_fifo_0
Progress: Adding hsot_trace_processor [altera_nios2_gen2 18.1]
Progress: Parameterizing module hsot_trace_processor
Progress: Adding mem_if_ddr2_emif_0 [altera_mem_if_ddr2_emif 18.1]
Progress: Parameterizing module mem_if_ddr2_emif_0
Progress: Adding nios_isr [altera_avalon_pio 18.1]
Progress: Parameterizing module nios_isr
Progress: Adding onchip_flash_0 [altera_onchip_flash 18.1]
Progress: Parameterizing module onchip_flash_0
Progress: Adding onchip_memory [altera_avalon_onchip_memory2 18.1]
Progress: Parameterizing module onchip_memory
Progress: Adding spi_0 [altera_avalon_spi 18.1]
Progress: Parameterizing module spi_0
Progress: Adding sprint_command_registers_0 [sprint_command_registers 1.0]
Progress: Parameterizing module sprint_command_registers_0
Progress: Adding sprint_config_registers_0 [sprint_config_registers 1.0]
Progress: Parameterizing module sprint_config_registers_0
Progress: Adding sprint_data_registers_0 [sprint_data_registers 1.0]
Progress: Parameterizing module sprint_data_registers_0
Progress: Adding sys_id [altera_avalon_sysid_qsys 18.1]
Progress: Parameterizing module sys_id
Progress: Adding system_debug_0 [altera_jtag_avalon_master 18.1]
Progress: Parameterizing module system_debug_0
Progress: Adding timer_ms [altera_avalon_timer 18.1]
Progress: Parameterizing module timer_ms
Progress: Adding trace_uart_0 [altera_avalon_uart 18.1]
Progress: Parameterizing module trace_uart_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: SPRINT_OSI_S.JTAG_UART: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Warning: SPRINT_OSI_S.mem_if_ddr2_emif_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Info: SPRINT_OSI_S.nios_isr: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: SPRINT_OSI_S.sys_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: SPRINT_OSI_S.sys_id: Time stamp will be automatically updated when this component is generated.
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0.trace_st_source: HOST_HSOT_Interface_0.trace_st_source must be connected to an Avalon-ST sink
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0: Interrupt sender HOST_HSOT_Interface_0.I1 is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.LINEARISE_DATA_CONTROL_0: Interrupt sender LINEARISE_DATA_CONTROL_0.irq0 is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.trace_uart_0: Interrupt sender trace_uart_0.irq is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0: HOST_HSOT_Interface_0.trace_mm_master_csr must be connected to an Avalon-MM slave
Warning: SPRINT_OSI_S.trace_uart_0: trace_uart_0.s1 must be connected to an Avalon-MM master
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\My_Designs\myproject_code\myproject\Source\Qsys_Systems\SPRINT_OSI_S.qsys --synthesis=VHDL --output-directory=C:\My_Designs\myproject_code\myproject\Source\Qsys_Systems\SPRINT_OSI_S\synthesis --family="MAX 10" --part=10M40DAF484C7G
Progress: Loading Qsys_Systems/SPRINT_OSI_S.qsys
Progress: Reading input file
Progress: Adding CLK_132MHz [clock_source 18.1]
Progress: Parameterizing module CLK_132MHz
Progress: Adding CLK_33MHz [clock_source 18.1]
Progress: Parameterizing module CLK_33MHz
Progress: Adding DEBUG_REGISTERS_0 [DEBUG_REGISTERS 1.0]
Progress: Parameterizing module DEBUG_REGISTERS_0
Progress: Adding HOST_HSOT_Interface_0 [HOST_HSOT_Interface 1.0]
Progress: Parameterizing module HOST_HSOT_Interface_0
Progress: Adding JTAG_UART [altera_avalon_jtag_uart 18.1]
Progress: Parameterizing module JTAG_UART
Progress: Adding LINEARISE_DATA_CONTROL_0 [LINEARISE_DATA_CONTROL 2.0]
Progress: Parameterizing module LINEARISE_DATA_CONTROL_0
Progress: Adding NiosII [altera_nios2_gen2 18.1]
Progress: Parameterizing module NiosII
Progress: Adding PLL [altpll 18.1]
Progress: Parameterizing module PLL
Progress: Adding hsot_trace_fifo_0 [altera_avalon_fifo 18.1]
Progress: Parameterizing module hsot_trace_fifo_0
Progress: Adding hsot_trace_processor [altera_nios2_gen2 18.1]
Progress: Parameterizing module hsot_trace_processor
Progress: Adding mem_if_ddr2_emif_0 [altera_mem_if_ddr2_emif 18.1]
Progress: Parameterizing module mem_if_ddr2_emif_0
Progress: Adding nios_isr [altera_avalon_pio 18.1]
Progress: Parameterizing module nios_isr
Progress: Adding onchip_flash_0 [altera_onchip_flash 18.1]
Progress: Parameterizing module onchip_flash_0
Progress: Adding onchip_memory [altera_avalon_onchip_memory2 18.1]
Progress: Parameterizing module onchip_memory
Progress: Adding spi_0 [altera_avalon_spi 18.1]
Progress: Parameterizing module spi_0
Progress: Adding sprint_command_registers_0 [sprint_command_registers 1.0]
Progress: Parameterizing module sprint_command_registers_0
Progress: Adding sprint_config_registers_0 [sprint_config_registers 1.0]
Progress: Parameterizing module sprint_config_registers_0
Progress: Adding sprint_data_registers_0 [sprint_data_registers 1.0]
Progress: Parameterizing module sprint_data_registers_0
Progress: Adding sys_id [altera_avalon_sysid_qsys 18.1]
Progress: Parameterizing module sys_id
Progress: Adding system_debug_0 [altera_jtag_avalon_master 18.1]
Progress: Parameterizing module system_debug_0
Progress: Adding timer_ms [altera_avalon_timer 18.1]
Progress: Parameterizing module timer_ms
Progress: Adding trace_uart_0 [altera_avalon_uart 18.1]
Progress: Parameterizing module trace_uart_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: SPRINT_OSI_S.JTAG_UART: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Warning: SPRINT_OSI_S.mem_if_ddr2_emif_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Info: SPRINT_OSI_S.nios_isr: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: SPRINT_OSI_S.sys_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: SPRINT_OSI_S.sys_id: Time stamp will be automatically updated when this component is generated.
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0.trace_st_source: HOST_HSOT_Interface_0.trace_st_source must be connected to an Avalon-ST sink
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0: Interrupt sender HOST_HSOT_Interface_0.I1 is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.LINEARISE_DATA_CONTROL_0: Interrupt sender LINEARISE_DATA_CONTROL_0.irq0 is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.trace_uart_0: Interrupt sender trace_uart_0.irq is not connected to an interrupt receiver
Warning: SPRINT_OSI_S.HOST_HSOT_Interface_0: HOST_HSOT_Interface_0.trace_mm_master_csr must be connected to an Avalon-MM slave
Warning: SPRINT_OSI_S.trace_uart_0: trace_uart_0.s1 must be connected to an Avalon-MM master
Info: SPRINT_OSI_S: Generating SPRINT_OSI_S "SPRINT_OSI_S" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src16 and cmd_mux_016.sink0
Info: Inserting clock-crossing logic between cmd_demux_001.src0 and cmd_mux_005.sink1
Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_005.src1 and rsp_mux_001.sink0
Info: Inserting clock-crossing logic between rsp_demux_016.src0 and rsp_mux.sink16
Info: DEBUG_REGISTERS_0: "SPRINT_OSI_S" instantiated DEBUG_REGISTERS "DEBUG_REGISTERS_0"
Info: HOST_HSOT_Interface_0: "SPRINT_OSI_S" instantiated HOST_HSOT_Interface "HOST_HSOT_Interface_0"
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_ADDRESS_MAP.vhd
Info: JTAG_UART: Starting RTL generation for module 'SPRINT_OSI_S_JTAG_UART'
Info: JTAG_UART:   Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=SPRINT_OSI_S_JTAG_UART --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0033_JTAG_UART_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0033_JTAG_UART_gen//SPRINT_OSI_S_JTAG_UART_component_configuration.pl  --do_build_sim=0  ]
Info: JTAG_UART: Done RTL generation for module 'SPRINT_OSI_S_JTAG_UART'
Info: JTAG_UART: "SPRINT_OSI_S" instantiated altera_avalon_jtag_uart "JTAG_UART"
Info: LINEARISE_DATA_CONTROL_0: "SPRINT_OSI_S" instantiated LINEARISE_DATA_CONTROL "LINEARISE_DATA_CONTROL_0"
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_ADDRESS_MAP.vhd
Info: NiosII: "SPRINT_OSI_S" instantiated altera_nios2_gen2 "NiosII"
Info: PLL: "SPRINT_OSI_S" instantiated altpll "PLL"
Info: mem_if_ddr2_emif_0: "SPRINT_OSI_S" instantiated altera_mem_if_ddr2_emif "mem_if_ddr2_emif_0"
Info: nios_isr: Starting RTL generation for module 'SPRINT_OSI_S_nios_isr'
Info: nios_isr:   Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=SPRINT_OSI_S_nios_isr --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0037_nios_isr_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0037_nios_isr_gen//SPRINT_OSI_S_nios_isr_component_configuration.pl  --do_build_sim=0  ]
Info: nios_isr: Done RTL generation for module 'SPRINT_OSI_S_nios_isr'
Info: nios_isr: "SPRINT_OSI_S" instantiated altera_avalon_pio "nios_isr"
Info: onchip_flash_0: Generating top-level entity altera_onchip_flash
Info: onchip_flash_0: "SPRINT_OSI_S" instantiated altera_onchip_flash "onchip_flash_0"
Info: onchip_memory: Starting RTL generation for module 'SPRINT_OSI_S_onchip_memory'
Info: onchip_memory:   Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=SPRINT_OSI_S_onchip_memory --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0039_onchip_memory_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0039_onchip_memory_gen//SPRINT_OSI_S_onchip_memory_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_memory: Done RTL generation for module 'SPRINT_OSI_S_onchip_memory'
Info: onchip_memory: "SPRINT_OSI_S" instantiated altera_avalon_onchip_memory2 "onchip_memory"
Info: spi_0: Starting RTL generation for module 'SPRINT_OSI_S_spi_0'
Info: spi_0:   Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=SPRINT_OSI_S_spi_0 --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0040_spi_0_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0040_spi_0_gen//SPRINT_OSI_S_spi_0_component_configuration.pl  --do_build_sim=0  ]
Info: spi_0: Done RTL generation for module 'SPRINT_OSI_S_spi_0'
Info: spi_0: "SPRINT_OSI_S" instantiated altera_avalon_spi "spi_0"
Info: sprint_command_registers_0: "SPRINT_OSI_S" instantiated sprint_command_registers "sprint_command_registers_0"
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_ADDRESS_MAP.vhd
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_HSOT_INTERFACE.vhd
Info: sprint_config_registers_0: "SPRINT_OSI_S" instantiated sprint_config_registers "sprint_config_registers_0"
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_INTERFACE_GLOBALS.vhd
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_REGISTERS_RECORDS.vhd
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_ADDRESS_MAP.vhd
Info: sprint_data_registers_0: "SPRINT_OSI_S" instantiated sprint_data_registers "sprint_data_registers_0"
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_ADDRESS_MAP.vhd
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_INTERFACE_GLOBALS.vhd
Info: Reusing file C:/My_Designs/myproject_code/myproject/Source/Qsys_Systems/SPRINT_OSI_S/synthesis/submodules/P_REGISTERS_RECORDS.vhd
Info: sys_id: "SPRINT_OSI_S" instantiated altera_avalon_sysid_qsys "sys_id"
Info: system_debug_0: "SPRINT_OSI_S" instantiated altera_jtag_avalon_master "system_debug_0"
Info: timer_ms: Starting RTL generation for module 'SPRINT_OSI_S_timer_ms'
Info: timer_ms:   Generation command is [exec C:/intelFPGA/18.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA/18.1/quartus/bin64//perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=SPRINT_OSI_S_timer_ms --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0045_timer_ms_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0045_timer_ms_gen//SPRINT_OSI_S_timer_ms_component_configuration.pl  --do_build_sim=0  ]
Info: timer_ms: Done RTL generation for module 'SPRINT_OSI_S_timer_ms'
Info: timer_ms: "SPRINT_OSI_S" instantiated altera_avalon_timer "timer_ms"
Info: trace_uart_0: Starting RTL generation for module 'SPRINT_OSI_S_trace_uart_0'
Info: trace_uart_0:   Generation command is [exec C:/intelfpga/18.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga/18.1/quartus/bin64/perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- C:/intelfpga/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=SPRINT_OSI_S_trace_uart_0 --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0046_trace_uart_0_gen/ --quartus_dir=C:/intelfpga/18.1/quartus --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0046_trace_uart_0_gen//SPRINT_OSI_S_trace_uart_0_component_configuration.pl  --do_build_sim=0  ]
Info: trace_uart_0: Done RTL generation for module 'SPRINT_OSI_S_trace_uart_0'
Info: trace_uart_0: "SPRINT_OSI_S" instantiated altera_avalon_uart "trace_uart_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "SPRINT_OSI_S" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "SPRINT_OSI_S" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "SPRINT_OSI_S" instantiated altera_irq_mapper "irq_mapper"
Info: irq_synchronizer: "SPRINT_OSI_S" instantiated altera_irq_clock_crosser "irq_synchronizer"
Info: rst_controller: "SPRINT_OSI_S" instantiated altera_reset_controller "rst_controller"
Info: cpu: Starting RTL generation for module 'SPRINT_OSI_S_NiosII_cpu'
Info: cpu:   Generation command is [exec C:/intelFPGA/18.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA/18.1/quartus/bin64//perl/lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga/18.1/quartus/sopc_builder/bin -I C:/intelfpga/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=SPRINT_OSI_S_NiosII_cpu --dir=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0050_cpu_gen/ --quartus_bindir=C:/intelFPGA/18.1/quartus/bin64/ --verilog --config=C:/Users/myuser/AppData/Local/Temp/alt8865_6179895469193550993.dir/0050_cpu_gen//SPRINT_OSI_S_NiosII_cpu_processor_configuration.pl  --do_build_sim=0  ]
Info: cpu: # 2021.08.26 14:48:55 (*) Starting Nios II generation
Info: cpu: # 2021.08.26 14:48:55 (*)   Checking for plaintext license.
Info: cpu: # 2021.08.26 14:48:56 (*)   Couldn't query license setup in Quartus directory C:/intelFPGA/18.1/quartus/bin64/
Info: cpu: # 2021.08.26 14:48:56 (*)   Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.08.26 14:48:58 (*)   Plaintext license not found.
Info: cpu: # 2021.08.26 14:48:58 (*)   Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.08.26 14:48:58 (*)   Couldn't query license setup in Quartus directory C:/intelFPGA/18.1/quartus/bin64/
Info: cpu: # 2021.08.26 14:48:58 (*)   Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.08.26 14:49:01 (*)   Encrypted license found.  SOF will not be time-limited.
Info: cpu: # 2021.08.26 14:49:01 (*)   Elaborating CPU configuration settings
Info: cpu: # 2021.08.26 14:49:01 (*)   Creating all objects for CPU
Info: cpu: # 2021.08.26 14:49:01 (*)     Testbench
Info: cpu: # 2021.08.26 14:49:01 (*)     Instruction decoding
Info: cpu: # 2021.08.26 14:49:01 (*)       Instruction fields
Info: cpu: # 2021.08.26 14:49:01 (*)       Instruction decodes
Info: cpu: # 2021.08.26 14:49:01 (*)       Signals for RTL simulation waveforms
Info: cpu: # 2021.08.26 14:49:01 (*)       Instruction controls
Info: cpu: # 2021.08.26 14:49:01 (*)     Pipeline frontend
Info: cpu: # 2021.08.26 14:49:01 (*)     Pipeline backend
Info: cpu: # 2021.08.26 14:49:03 (*)   Generating RTL from CPU objects
Info: cpu: # 2021.08.26 14:49:04 (*)   Creating encrypted RTL
Info: cpu: # 2021.08.26 14:49:05 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'SPRINT_OSI_S_NiosII_cpu'
Info: cpu: "NiosII" instantiated altera_nios2_gen2_unit "cpu"
Info: pll0: "mem_if_ddr2_emif_0" instantiated altera_mem_if_ddr2_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating altgpio
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: Remember to run the SPRINT_OSI_S_mem_if_ddr2_emif_0_p0_pin_assignments.tcl
Info: p0: script after running Synthesis and before Fitting.
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: "mem_if_ddr2_emif_0" instantiated altera_mem_if_ddr2_phy_core "p0"
Info: m0: "mem_if_ddr2_emif_0" instantiated altera_mem_if_ddr2_afi_mux "m0"
Error: s0: Error during execution of "{C:/intelfpga/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/intelfpga/18.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: Authorized application C:\intelFPGA\18.1\quartus\bin64\jtagserver.exe is enabled in the firewall.
Error: s0: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga/18.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../SPRINT_OSI_S_mem_if_ddr2_emif_0_s0_AC_ROM.hex -inst_rom ../SPRINT_OSI_S_mem_if_ddr2_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0010001110011 -DAC_ROM_MR0_CALIB=0010001110011 -DAC_ROM_MR0_DLL_RESET=0010101110011 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE=0001110000000 -DAC_ROM_MR2=0000010000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR= -DAC_ROM_MR0_DLL_RESET_MIRR= -DAC_ROM_MR1_MIRR= -DAC_ROM_MR2_MIRR= -DAC_ROM_MR3_MIRR= -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2018  Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../SPRINT_OSI_S_mem_if_ddr2_emif_0_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../SPRINT_OSI_S_mem_if_ddr2_emif_0_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: C:/intelfpga/18.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: Windows Subsystem for Linux has no installed distributions.
Error: s0:
Error: s0: Distributions can be installed by visiting the Microsoft Store:
Error: s0:
Error: s0: https://aka.ms/wslstore
Error: s0:
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if {[file exists $seq_file] == 0} {
		_error "Cannot find $seq_file"
	}"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
    invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
		set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
    (procedure "generate_qsys_sequencer_sw" line 924)
    invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."
    invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."
    ("if" else script line 2)
    invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
		set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
    invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir QUARTUS_SYNTH] {
		set file_name [file tail $genera..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth SPRINT_OSI_S_mem_if_ddr2_emif_0_s0"
Info: s0: "mem_if_ddr2_emif_0" instantiated altera_mem_if_ddr2_qseq "s0"
Error: Generation stopped, 191 or more modules remaining
Info: SPRINT_OSI_S: Done "SPRINT_OSI_S" with 78 modules, 112 files
Error: qsys-generate failed with exit code 1: 27 Errors, 7 Warnings
Info: Finished: Create HDL design files for synthesis