/* n bit shifter, with parallel and serial, input and output. George H. Barbehenn 10/3/2021 enable: Enable shifting, load is asynchronous. pin: "N" wide parallel input loaded at falling edge of nLoad. pol: Clock polarity, high = positive edge. sclk: Serial clock, rising edge sensitive. sdin: Serial input data. nload: Active low, parallel load enable. dir: Shift direction. If low SDO = LSb of pout, if high SDO = MSb of pout. POUT: "N" wide Parallel output. SDO: Serial output data. */ module shiftn (enable, pin, pol, sclk, sdin, nload, dir, POUT, SDO); parameter N = 8; input enable, pol, sclk, sdin, nload, dir; input [N-1:0] pin; output reg SDO; output reg [N-1:0] POUT; /* Why not include "enable*, in the Clock logic, and simplify the always block? Doing so, will cause enable to become an additional clock. So the shifter will shift on the rising edge of enable, as well as on the Clock edge selected by pol. */ wire Clock = sclk ^ ~pol; // Invert the Clock, used by the always block, according to pol. always @(posedge Clock, negedge nload) begin if (!nload) begin POUT <= pin; end else begin if (!dir && enable) begin {POUT, SDO} <= {sdin, POUT};// Shift right 1, with carry end else if (dir && enable) begin {SDO, POUT} <= {POUT, sdin};// Shift left 1, with carry end end end endmodule