module fx3_reg_ctrl_hw(
   input                       clk,
   input                       reset_n,
   
   input  wire                 avmm_write_en,
	input  wire                 avmm_read_en,
	input  wire  [15:0]         avmm_addr,
 	input  wire  [31:0]         avmm_datain,

	output  reg                 avmm_rddata_valid,
	output  reg  [31:0]         avmm_dataout,
	
   output reg fx3_adc_start, //registering fx3_adc_start, added by KD
	output fx3_dac_start,
	output [31:0]size,
	output softreset,
	output xcvr_mode

);
`define FX3_CNTROL_REG_ADDR  16'h4000
`define FX3_LEN_REG_ADDR  16'h4001

parameter IDLE = 2'd0;
parameter SEND_DATA = 2'd1;


reg n_avmm_rddata_valid;
reg [1:0] n_rd_state,rd_state;

reg [31:0] n_avmm_dataout;

reg [31:0] fx3ctrlreg;
reg [31:0] fx3size;
wire fx3_adc_start_w1; //added by KD to fix recovery violation

always @(*)
begin
   
	n_avmm_rddata_valid = 1'b0;
	n_avmm_dataout      = avmm_dataout;
	n_rd_state = rd_state;
	

  case(rd_state)
	IDLE:
	begin
		if(avmm_read_en)
		begin
	     		n_rd_state = SEND_DATA;
	    end
	end
	SEND_DATA:
	begin
		if(avmm_addr == `FX3_CNTROL_REG_ADDR)
		begin
		  		n_avmm_dataout = fx3ctrlreg; //control register
				n_avmm_rddata_valid = 1'b1;
				n_rd_state = IDLE;
		end
		else if(avmm_addr == `FX3_LEN_REG_ADDR)
		begin
		  		n_avmm_dataout = fx3size; //control register
				n_avmm_rddata_valid = 1'b1;
				n_rd_state = IDLE;
		end
		//n_rd_state = IDLE;
	end
    default:
	   n_rd_state = IDLE;
   endcase
end

always@(posedge clk or negedge reset_n)
	begin
		if(!reset_n)
			fx3ctrlreg<=32'd0;
		else if(avmm_write_en&&(avmm_addr == `FX3_CNTROL_REG_ADDR)) 
			fx3ctrlreg<=avmm_datain;
	end
	
		   
	
always@(posedge clk or negedge reset_n)
	begin
		if(!reset_n)
			fx3size<=32'd0;
		else if(avmm_write_en&&(avmm_addr == `FX3_LEN_REG_ADDR)) 
			fx3size<=avmm_datain;
	end		



reg	[3:0] adc_start_r;
	reg	[3:0] dac_start_r;
	reg	[3:0] softreset_r;
//	reg	[3:0] i2c_capture_start_r;
//	reg	[3:0]	i2c_tx_start_r;
//	reg	[3:0]	i2c_tx_stop_r;
//	reg			i2c_capture_done_r;

	always@(posedge clk or negedge reset_n)
	begin
		if(!reset_n)
		begin
			adc_start_r	<=	4'h0;
			dac_start_r <= 4'h0;
			softreset_r	<=	4'h0;
			avmm_dataout      <= 32'd0; 
			avmm_rddata_valid <=1'b0;
			rd_state <= 2'd0;			
//			i2c_capture_start_r<= 4'h0;
//			i2c_tx_start_r	<=	4'h0;
//			i2c_tx_stop_r	<=	4'h0;
//			i2c_capture_done_r <= 1'd0;
		end
		else 
		begin
			adc_start_r	<=	{adc_start_r[2:0],fx3ctrlreg[0]};
			dac_start_r <= {dac_start_r[2:0],fx3ctrlreg[1]};
			softreset_r 	<= {softreset_r[2:0],fx3ctrlreg[31]};
			avmm_dataout      <= n_avmm_dataout;  
			avmm_rddata_valid<=n_avmm_rddata_valid;
			rd_state = n_rd_state;
//			i2c_capture_start_r	<=	{i2c_capture_start_r[2:0],};
//			i2c_tx_start_r<=	{i2c_tx_start_r[2:0],};
//			i2c_tx_stop_r	<=	{i2c_tx_stop_r[2:0],};
//			i2c_capture_done_r <= i2c_capture_done;
		end
	end

	assign fx3_adc_start_w1	=	(!adc_start_r[1]) & adc_start_r[0];
	assign fx3_dac_start	=	(!dac_start_r[1]) & dac_start_r[0];
	assign softreset			=	(!softreset_r[1]) & softreset_r[0];
	assign xcvr_mode			= fx3ctrlreg[2];

	
	assign size	=	fx3size; // FPGA send size to FX3 <ADC>
	//assign dac_size 	=  {reg4, reg5};// FX3 send size to FPGA <DAC> ; added by prakash for Dac transfer length may not be needed one register may be enough

	//Register adc_start as it is the aclr signal given to fifo in ddr2fx3 module: added by KD
	always@(posedge clk or negedge reset_n)
	begin
		if(!reset_n)
		begin
			//fx3_adc_start_r1 <= 1'b0;
			fx3_adc_start <= 1'b0;
		end
		else
		begin
			//fx3_adc_start_r1 <= fx3_adc_start_w1;
			fx3_adc_start <= fx3_adc_start_w1;
		end
	end
endmodule