[Basic Functions|Clocks; PLLs and Resets|PLL]
Altera PLL v21.1= "%t" "%w/../common/lib/megawizard.pl" --wizard:altera_pll  --early_gen:on --wizard_file:"%w/source/top/pll_hw.tcl" --familyparameter:device_family %f %o %h
<INFO>
<QIP_FILE_ENABLED/>
<ACCEPT_OTHER_CNX VALUE="ON"/>
<DEVICE_FAMILY SUPPORTED="NONE | Stratix V | Arria V | Cyclone V | Arria V GZ" SUPPORT_CHECK="ON" /> 
<LANGUAGES   AHDL="OFF"/>
<PINPLAN SUPPORTED="ON"/>
<ALIAS>PLL Intel FPGA IP</ALIAS>
<ALIAS>PLL Intel FPGA IP v18.0</ALIAS>
<ALIAS>PLL Intel FPGA IP v18.1</ALIAS>
<ALIAS>PLL Intel FPGA IP v19.0</ALIAS>
<ALIAS>PLL Intel FPGA IP v19.1</ALIAS>
<ALIAS>PLL Intel FPGA IP v19.2</ALIAS>
<ALIAS>PLL Intel FPGA IP v19.3</ALIAS>
<ALIAS>PLL Intel FPGA IP v20.1</ALIAS>
<ALIAS>Altera PLL</ALIAS>
<ALIAS>Altera PLL v10.0</ALIAS>
<ALIAS>Altera PLL v10.1</ALIAS>
<ALIAS>Altera PLL v11.0</ALIAS>
<ALIAS>Altera PLL v11.1</ALIAS>
<ALIAS>Altera PLL v12.0</ALIAS>
<ALIAS>Altera PLL v12.1</ALIAS>
<ALIAS>Altera PLL v13.0</ALIAS>
<ALIAS>Altera PLL v13.1</ALIAS>
<ALIAS>Altera PLL v14.0</ALIAS>
<ALIAS>Altera PLL v14.1</ALIAS>
<ALIAS>Altera PLL v15.0</ALIAS>
<ALIAS>Altera PLL v15.1</ALIAS>
<ALIAS>Altera PLL v16.0</ALIAS>
<ALIAS>Altera PLL v16.1</ALIAS>
<ALIAS>Altera PLL v17.0</ALIAS>
<ALIAS>Altera PLL v17.1</ALIAS>
<ALIAS>Altera PLL v18.0</ALIAS>
<ALIAS>Altera PLL v18.1</ALIAS>
<ALIAS>Altera PLL v19.0</ALIAS>
<ALIAS>Altera PLL v19.1</ALIAS>
<ALIAS>Altera PLL v20.0</ALIAS>
<ALIAS>Altera PLL v20.1</ALIAS>
</INFO>