// Latch (flip-flop) signals for translating pipelined request
// mem_read and mem_write are directly connected to sdram_read and sdram_write
logic [31:0] result_readdata, store_writedata;
logic [24:0] store_address;
logic store_read, store_write;
always_ff @(posedge clock, posedge reset) begin
    if(reset) begin
        request_complete <= 1'b0;
        store_read <= 1'b0;
        store_write <= 1'b0;
        store_address <= 25'b0;
        result_readdata <= 32'b0;
    end else if(mem_read && mem_write) begin
        // Invalid state, reset to incomplete?
        request_complete <= 1'b0;
    end else if(mem_address != store_address
        || mem_writedata != store_writedata
        || mem_read != store_read
        || mem_write != store_write) begin
        // New request detected, update SDRAM signals and reset completion
        request_complete <= 1'b0;
        store_writedata <= mem_writedata;
        store_read <= mem_read;
        store_write <= mem_write;
        store_address <= mem_address;
    end else if(mem_read && sdram_readdatavalid) begin
        // Read request finished, update completion
        // Also snap up valid read data while possible
        request_complete <= 1'b1;
        result_readdata <= sdram_readdata;
    end else if(mem_write && ~sdram_waitrequest) begin
        // Write request finished, update completion
        request_complete <= 1'b1;
    end
end