MEMORY MANAGEMENT: using options 'debug' MEMORY MANAGEMENT: alignment_checking is ENABLED MEMORY MANAGEMENT: integrity_checking is ENABLED MEMORY MANAGEMENT: leak_checking is ENABLED MEMORY MANAGEMENT: new_handler is ENABLED MEMORY MANAGEMENT: observation is ENABLED MEMORY MANAGEMENT: pooling is DISABLED Prerelease License -- for engineering feedback and testing purposes only. Not for sale. >> cd(matlabroot);cd test/toolbox/comm >> cd unittests/hdl/HDLCRCGenerator >> edit tposHDLCRCGenSynthAria10 >> runtests("tposHDLCRCGenSynthAria10") *** Entering directory :: /mathworks/devel/bat/Bspchdl/.zfs/snapshot/Bspchdl.1892852.pass/build/matlab/test/toolbox/comm/unittests/hdl/HDLCRCGenerator at :: 02-Mar-2022 10:21:57 *** *** Session information :: HOSTNAME:testglnxa64-4 *** *** ATTRIBUTES_BEGIN *** device: scheduler: executor: harness: *** ATTRIBUTES_END *** MATLAB version 9.13.0.1879353 (R2022b) Prerelease, built on February 10, 2022 02-Mar-2022 10:21:57 :: Running test : test/toolbox/comm/unittests/hdl/HDLCRCGenerator/tposHDLCRCGenSynthAria10('lvlAll') 141 tester = HDLCoderTester.forDownstreamWorkflow(Tc, ... K>> assignin('base','NOHDLCHECKSUMS',1) K>> Tc.addTeardown(@() evalin('base','clear NOHDLCHECKSUMS')) K>> tester = HDLCoderTester.forDownstreamWorkflow(Tc, ... [Tc.TestModel,'/',subsystem],... hWC, ... 'TargetLanguage', TargetLanguage,... 'WorkflowOptions', workflowOptions, ... 'CodegenOptions', codegenOptions,... 'ModelRelativePath','.'); % run the workflow tester.runWorkflow; import matlab.unittest.constraints.IsGreaterThan Tc.verifyThat(tester, VerifyHardwareStatistics(ResourceValues,'TreatFmaxAsLowerBound',true)); ------------------------------ Running test point HDLTest_Synth Test run details: DUT - mhdltestcrcgenerator/DUT TargetLanguage - vhdl, Parameter 2 - sc1, Parameter 3 - idlecycle1, Parameter 4 - dt1, Parameter 5 - PVP1, Parameter 6 - dataW1, Parameter 7 - fr1, Parameter 8 - value1 ### Workflow begin. ### Loading settings from model. ### ++++++++++++++ Task Generate RTL Code and Testbench ++++++++++++++ ### Generate RTL Code and Testbench ### Generating HDL for 'mhdltestcrcgenerator/DUT'. ### Using the config set for model mhdltestcrcgenerator for HDL code generation parameters. ### Running HDL checks on the model 'mhdltestcrcgenerator'. ### Begin compilation of the model 'mhdltestcrcgenerator'... ### Applying HDL optimizations on the model 'mhdltestcrcgenerator'... ### 'AdaptivePipelining' is set to 'Off' for the model. 'AdaptivePipelining' can improve the achievable clock frequency and reduce the area usage on FPGA boards. To enable adaptive pipelining, please set the option to 'On'. When adaptive pipelining is enabled, it inserts pipeline registers to create patterns that efficiently map blocks to DSP units on the target FPGA device. ### 'LUTMapToRAM' is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'. ### Begin model generation. ### Model generation complete. ### Begin VHDL Code Generation for 'mhdltestcrcgenerator'. ### Working on mhdltestcrcgenerator/DUT/General CRC Generator HDL Optimized/CRCGenControl as hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenControl.vhd. ### Working on mhdltestcrcgenerator/DUT/General CRC Generator HDL Optimized/CRCGenCompute as hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenCompute.vhd. ### Working on mhdltestcrcgenerator/DUT/General CRC Generator HDL Optimized as hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd. ### Working on mhdltestcrcgenerator/DUT as hdl_prj/hdlsrc/mhdltestcrcgenerator/DUT.vhd. ### Code Generation for 'mhdltestcrcgenerator' completed. ### Creating HDL Code Generation Check Report DUT_report.html ### HDL check for 'mhdltestcrcgenerator' complete with 0 errors, 0 warnings, and 2 messages. ### HDL code generation complete. ### ++++++++++++++ Task Create Project ++++++++++++++ ### Create Project ### Generating Altera QUARTUS II 20.1.1 project: hdl_prj/quartus_prj/DUT_quartus.qpf ### Generated logfile: hdl_prj/hdlsrc/mhdltestcrcgenerator/workflow_task_CreateProject.log ### Task "Create Project" successful. ### Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Copyright (C) 2020 Intel Corporation. All rights reserved.  Info: Your use of Intel Corporation's design tools, logic functions  Info: and other software and tools, and any partner logic  Info: functions, and any output files from any of the foregoing  Info: (including device programming or simulation files), and any  Info: associated documentation or information are expressly subject  Info: to the terms and conditions of the Intel Program License  Info: Subscription Agreement, the Intel Quartus Prime License Agreement,  Info: the Intel FPGA IP License Agreement, or other applicable license  Info: agreement, including, without limitation, that your use is for  Info: the sole purpose of programming logic devices manufactured by  Info: Intel and sold by Intel or its authorized distributors. Please  Info: refer to the applicable agreement for further details, at  Info: https://fpgasoftware.intel.com/eula.  Info: Processing started: Wed Mar 2 10:27:08 2022 Info: Command: quartus_sta -t DUT_Altera_QUARTUS_II_run.tcl ### Create new Altera QUARTUS II 20.1.1 project hdl_prj/quartus_prj/DUT_quartus.qpf ### Set Altera QUARTUS II 20.1.1 project properties ### Update Altera QUARTUS II 20.1.1 project with HDL source files Info (125061): Changed top-level design entity name to "DUT" ### Close Altera QUARTUS II 20.1.1 project. Info (23030): Evaluation of Tcl script DUT_Altera_QUARTUS_II_run.tcl was successful Info: Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings  Info: Peak virtual memory: 320 megabytes  Info: Processing ended: Wed Mar 2 10:27:08 2022  Info: Elapsed time: 00:00:00  Info: Total CPU time (on all processors): 00:00:00  Elapsed time is 2.7257 seconds. ### ++++++++++++++ Task Perform Logic Synthesis ++++++++++++++ ### Perform Logic Synthesis ### Generated logfile: hdl_prj/hdlsrc/mhdltestcrcgenerator/workflow_task_PerformLogicSynthesis.log ### Task "Perform Logic Synthesis" successful. ### Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Copyright (C) 2020 Intel Corporation. All rights reserved.  Info: Your use of Intel Corporation's design tools, logic functions  Info: and other software and tools, and any partner logic  Info: functions, and any output files from any of the foregoing  Info: (including device programming or simulation files), and any  Info: associated documentation or information are expressly subject  Info: to the terms and conditions of the Intel Program License  Info: Subscription Agreement, the Intel Quartus Prime License Agreement,  Info: the Intel FPGA IP License Agreement, or other applicable license  Info: agreement, including, without limitation, that your use is for  Info: the sole purpose of programming logic devices manufactured by  Info: Intel and sold by Intel or its authorized distributors. Please  Info: refer to the applicable agreement for further details, at  Info: https://fpgasoftware.intel.com/eula.  Info: Processing started: Wed Mar 2 10:27:10 2022 Info: Command: quartus_sta -t DUT_Altera_QUARTUS_II_run.tcl ### Open existing Altera QUARTUS II 20.1.1 project hdl_prj/quartus_prj/DUT_quartus.qpf ### Running Synthesis in Altera QUARTUS II 20.1.1 ... Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Processing started: Wed Mar 2 10:27:11 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DUT_quartus -c DUT_quartus Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 2 design units, including 1 entities, in source file /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenControl.vhd  Info (12022): Found design unit 1: CRCGenControl-rtl File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenControl.vhd Line: 43  Info (12023): Found entity 1: CRCGenControl File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenControl.vhd Line: 24 Info (12021): Found 2 design units, including 1 entities, in source file /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenCompute.vhd  Info (12022): Found design unit 1: CRCGenCompute-rtl File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenCompute.vhd Line: 38  Info (12023): Found entity 1: CRCGenCompute File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/CRCGenCompute.vhd Line: 24 Info (12021): Found 2 design units, including 1 entities, in source file /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd  Info (12022): Found design unit 1: General_CRC_Generator_HDL_Optimized-rtl File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd Line: 40  Info (12023): Found entity 1: General_CRC_Generator_HDL_Optimized File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd Line: 24 Info (12021): Found 2 design units, including 1 entities, in source file /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/DUT.vhd  Info (12022): Found design unit 1: DUT-rtl File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/DUT.vhd Line: 61  Info (12023): Found entity 1: DUT File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/DUT.vhd Line: 44 Info (12127): Elaborating entity "DUT" for the top level hierarchy Info (12129): Elaborating entity "General_CRC_Generator_HDL_Optimized" using architecture "A:rtl" for hierarchy "General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized" File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/DUT.vhd Line: 86 Info (12129): Elaborating entity "CRCGenControl" using architecture "A:rtl" for hierarchy "General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenControl:u_Controlsignal_inst" File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd Line: 125 Info (12129): Elaborating entity "CRCGenCompute" using architecture "A:rtl" for hierarchy "General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst" File: /tmp/tpf8df8d76/hdl_prj/hdlsrc/mhdltestcrcgenerator/General_CRC_Generator_HDL_Optimized.vhd Line: 142 Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Info (286030): Timing-Driven Synthesis is running Info (21057): Implemented 177 device resources after synthesis - the final resource count might be different  Info (21058): Implemented 12 input pins  Info (21059): Implemented 10 output pins  Info (21061): Implemented 155 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings  Info: Peak virtual memory: 467 megabytes  Info: Processing ended: Wed Mar 2 10:27:24 2022  Info: Elapsed time: 00:00:13  Info: Total CPU time (on all processors): 00:00:21 ### Synthesis Complete. ### Close Altera QUARTUS II 20.1.1 project. Info (23030): Evaluation of Tcl script DUT_Altera_QUARTUS_II_run.tcl was successful Info: Quartus Prime Timing Analyzer was successful. 0 errors, 9 warnings  Info: Peak virtual memory: 320 megabytes  Info: Processing ended: Wed Mar 2 10:27:25 2022  Info: Elapsed time: 00:00:15  Info: Total CPU time (on all processors): 00:00:22  Elapsed time is 15.7141 seconds. ### ++++++++++++++ Task Perform Mapping ++++++++++++++ ### Perform Mapping ### Generated logfile: hdl_prj/hdlsrc/mhdltestcrcgenerator/workflow_task_PerformMapping.log ### Task "Perform Mapping" successful. ### Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Copyright (C) 2020 Intel Corporation. All rights reserved.  Info: Your use of Intel Corporation's design tools, logic functions  Info: and other software and tools, and any partner logic  Info: functions, and any output files from any of the foregoing  Info: (including device programming or simulation files), and any  Info: associated documentation or information are expressly subject  Info: to the terms and conditions of the Intel Program License  Info: Subscription Agreement, the Intel Quartus Prime License Agreement,  Info: the Intel FPGA IP License Agreement, or other applicable license  Info: agreement, including, without limitation, that your use is for  Info: the sole purpose of programming logic devices manufactured by  Info: Intel and sold by Intel or its authorized distributors. Please  Info: refer to the applicable agreement for further details, at  Info: https://fpgasoftware.intel.com/eula.  Info: Processing started: Wed Mar 2 10:27:26 2022 Info: Command: quartus_sta -t DUT_Altera_QUARTUS_II_run.tcl ### Open existing Altera QUARTUS II 20.1.1 project hdl_prj/quartus_prj/DUT_quartus.qpf ### Running PostMapTiming in Altera QUARTUS II 20.1.1 ... Info: ******************************************************************* Info: Running Quartus Prime Fitter  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Processing started: Wed Mar 2 10:27:26 2022 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off DUT_quartus -c DUT_quartus --plan Info: qfit2_default_script.tcl version: #1 Info: Project = DUT_quartus Info: Revision = DUT_quartus Info (12262): Starting Fitter periphery placement operations Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (119006): Selected device 10AS066H1F34E1HG for design "DUT_quartus" Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:27 Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AK13 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 22 pins of 22 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Info (16210): Plan updated with currently enabled project assignments. Critical Warning (17951): There are 24 unused RX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. Critical Warning (18655): There are 24 unused TX channels in the design. If you intend to use any of these channels in the future, you must add the assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' in your QSF file. This assignment will preserve the performance of specified channels over time. Note that unused channel preservation only works if the design uses or instantiates atleast 1 transceiver channel. Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00 Info (11191): Automatically promoted 1 clock (1 global)  Info (13173): clk~inputCLKENA0 (109 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I22 Info (176233): Starting register packing Info (332104): Reading SDC File: '../hdlsrc/mhdltestcrcgenerator/clock_constraint.sdc' Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 1 clocks  Info (332111): Period Clock Name  Info (332111): ======== ============  Info (332111): 2.857 clk Info (176235): Finished register packing  Extra Info (176219): No registers were packed into other blocks Info (12263): Fitter periphery placement operations ending: elapsed time is 00:00:53 Info: Quartus Prime Fitter was successful. 0 errors, 9 warnings  Info: Peak virtual memory: 4542 megabytes  Info: Processing ended: Wed Mar 2 10:28:20 2022  Info: Elapsed time: 00:00:54  Info: Total CPU time (on all processors): 00:01:03 Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer  Info: Version 20.1.1 Build 720 11/11/2020 SJ Standard Edition  Info: Processing started: Wed Mar 2 10:28:24 2022 Info: Command: quartus_sta DUT_quartus -c DUT_quartus --post_map Info: qsta_default_script.tcl version: #1 Info: Using post quartus_map netlist Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (332104): Reading SDC File: '../hdlsrc/mhdltestcrcgenerator/clock_constraint.sdc' Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 900mV 100C Model Info: Can't run Report Timing Closure Recommendations. Extra Fitter information is not available. To generate the report, compile the design with the current version of the Quartus Prime software. Info (332146): Worst-case setup slack is 1.956  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.956 0.000 clk Critical Warning (332148): Timing requirements not met  Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. Info (332146): Worst-case hold slack is -0.259  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): -0.259 -21.209 clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.307  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.307 0.000 clk Warning (18869): Performing metastability analysis with a pre-fit timing netlist. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate. Info: Analyzing Slow 900mV 0C Model Info (332146): Worst-case setup slack is 1.888  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.888 0.000 clk Info (332146): Worst-case hold slack is -0.300  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): -0.300 -25.240 clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.293  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.293 0.000 clk Warning (18869): Performing metastability analysis with a pre-fit timing netlist. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate. Info: Analyzing Fast 900mV 100C Model Info (332146): Worst-case setup slack is 1.937  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.937 0.000 clk Info (332146): Worst-case hold slack is -0.251  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): -0.251 -20.340 clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.301  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.301 0.000 clk Warning (18869): Performing metastability analysis with a pre-fit timing netlist. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate. Info: Analyzing Fast 900mV 0C Model Info (332146): Worst-case setup slack is 1.944  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.944 0.000 clk Info (332146): Worst-case hold slack is -0.244  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): -0.244 -19.640 clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 1.307  Info (332119): Slack End Point TNS Clock  Info (332119): ========= =================== =====================  Info (332119): 1.307 0.000 clk Warning (18869): Performing metastability analysis with a pre-fit timing netlist. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings  Info: Peak virtual memory: 3524 megabytes  Info: Processing ended: Wed Mar 2 10:29:03 2022  Info: Elapsed time: 00:00:39  Info: Total CPU time (on all processors): 00:01:03 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (332104): Reading SDC File: '../hdlsrc/mhdltestcrcgenerator/clock_constraint.sdc' Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "2.857143 ns" truncated to "2.857 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Warning (114001): Time value "1.428571 ns" truncated to "1.428 ns" Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332155): Fmax Summary  Info (332156): Restricted  Info (332156): Fmax Fmax Clock Note  Info (332156): ============ ============ ========== =====================  Info (332156): 1287.0 MHz 645.16 MHz clk limit due to minimum period restriction (tmin) Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.080  Info (332115): -setup  Info (332115): -npaths 1  Info (332115): -stdout Info (332115): Path #1: Setup slack is 2.080  Info (332115): ===================================================================  Info (332115): From Node : General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst|dvalidin  Info (332115): To Node : General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst|crcChecksum[21]  Info (332115): Launch Clock : clk  Info (332115): Latch Clock : clk  Info (332115): Data Arrival Path:  Info (332115): Total (ns) Incr (ns) Type HS/LP Element  Info (332115): ========== ========= == ==== ========== ===================================  Info (332115): 0.000 0.000 launch edge time  Info (332115): 1.132 1.132 R clock network delay  Info (332115): 1.132 0.000 General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst|dvalidin  Info (332115): 1.480 0.348 FF uTco u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|dvalidin|q  Info (332115): 1.480 0.000 FF IC u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|datacpt[18]~0|dataa  Info (332115): 1.726 0.246 FF CELL u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|datacpt[18]~0|combout  Info (332115): 1.726 0.000 FF IC u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|newChecksum_2~0|datab  Info (332115): 1.969 0.243 FF CELL u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|newChecksum_2~0|combout  Info (332115): 1.969 0.000 FF IC u_General_CRC_Generator_HDL_Optimized|u_ComputeCRC_inst|crcChecksum[21]|asdata  Info (332115): 1.969 0.000 FF CELL General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst|crcChecksum[21]  Info (332115): Data Required Path:  Info (332115): Total (ns) Incr (ns) Type HS/LP Element  Info (332115): ========== ========= == ==== ========== ===================================  Info (332115): 2.857 2.857 latch edge time  Info (332115): 3.898 1.041 R clock network delay  Info (332115): 3.989 0.091 clock pessimism removed  Info (332115): 3.959 -0.030 clock uncertainty  Info (332115): 4.049 0.090 uTsu General_CRC_Generator_HDL_Optimized:u_General_CRC_Generator_HDL_Optimized|CRCGenCompute:u_ComputeCRC_inst|crcChecksum[21]  Info (332115): Data Arrival Time : 1.969  Info (332115): Data Required Time : 4.049  Info (332115): Slack : 2.080  Info (332115): =================================================================== Info (332115): Report Timing: Found 3 setup paths (0 violated). Worst case slack is 2.080  Info (332115): -setup  Info (332115): -npaths 3  Info (332115): -file {DUT_preroute.tqr} ### PostMapTiming Complete. ### Close Altera QUARTUS II 20.1.1 project. Info (23030): Evaluation of Tcl script DUT_Altera_QUARTUS_II_run.tcl was successful Info: Quartus Prime Timing Analyzer was successful. 0 errors, 24 warnings  Info: Peak virtual memory: 1418 megabytes  Info: Processing ended: Wed Mar 2 10:29:09 2022  Info: Elapsed time: 00:01:43  Info: Total CPU time (on all processors): 00:02:14  Elapsed time is 104.9628 seconds. Parsed resource report file: DUT_quartus.map.rpt. Resource Usage Available Utilization (%) ______________________________________ _______ _________ _______________ {'Combinational ALUT usage for logic'} {'67' } {' '} {' '} {'Dedicated logic registers' } {'109'} {' '} {' '} {'DSP Blocks' } {'0' } {' '} {' '} Parsed timing report file: DUT_preroute.tqr. Timing Value ___________________ _______________ {'Requirement' } {'2.8571 ns' } {'Data Delay' } {'0.837 ns' } {'Slack' } {'2.08 ns' } {'Clock Frequency'} {'1286.76 MHz'} ### ++++++++++++++ Task Perform Place and Route ++++++++++++++ ### Perform Place and Route ### Generated logfile: hdl_prj/hdlsrc/mhdltestcrcgenerator/workflow_task_PerformPlaceAndRoute.log -- Workflow Run time: 355.25s Error using downstream.DownstreamIntegrationDriver/logDisplayToolResult Task "Perform Place and Route" unsuccessful. See log for details. Error in downstream.Engine/runStageCore Error in downstream.Engine/runStage Error in downstream.Engine/run Error in downstream.DownstreamIntegrationDriver/run Error in hwcli.runWorkflow Error in hdlcoder.runWorkflow (line 27) hwcli.runWorkflow( varargin{:} ); Error in hdlcodertest.workflowrunner.DownstreamWorkflowRunner/runWorkflow (line 36) hdlcoder.runWorkflow(h.DUT, h.WorkflowConfig, h.WorkflowOptions{:}); Error in hdlcodertest.HDLCoderTester/runDownstreamWorkflow (line 642) theWorkflowRunner.runWorkflow(); Error in hdlcodertest.HDLCoderTester/runWorkflow (line 502) h.runDownstreamWorkflow; K>> tester tester = HDLCoderTester with properties: DUT: 'mhdltestcrcgenerator/DUT' CodegenOptions: {1×10 cell} LoadedModels: {'mhdltestcrcgenerator'} TestCaseObject: [1×1 tposHDLCRCGenSynthAria10] Model: 'mhdltestcrcgenerator' Subsystem: 'DUT' ModelRelativePath: '.' WorkingDirectory: '/tmp/tpf8df8d76' CodegenDirectory: [] CodegenVerbosity: 0 TransientCodegenOptions: {} TargetLanguage: 'vhdl' ChecksumInfo: [1×1 struct] IsDPICTB: 0 SimulationTool: 'Mentor Graphics Modelsim' CheckSumMatches: 0 CheckSumObject: {} WFAChecksumMatches: 0 BaseWorkSpaceVars: {9×1 cell} DoChecksumAfter: 'never' TestDirectory: '/mathworks/devel/bat/Bspchdl/.zfs/snapshot/Bspchdl.1892852.pass/build/matlab/test/toolbox/comm/unittests/hdl/HDLCRCGenerator' WorkflowConfig: [1×1 hwcli.config.GenericConfig] WorkflowOptions: {'Verbosity' 'on'} PostModelgenCallback: '' ConstraintSpecification: [1×1 hdlcodertest.constraints.HDLConstraintsSpecification] PreModelLoadCallback: {} PostModelLoadCallback: {} MakehdlWarnings: {} MakehdlMessages: {} MakehdltbWarnings: {} MakehdltbMessages: {} IgnoreWarnings: 1 ModelsimVersion: 'default' VivadoVersion: 'default' UpdateBaseline: 0 tempDir: [] K>> a = tester.WorkingDirectory a = '/tmp/tpf8df8d76' K>> cd(a) K>> cd hdl_prj K>> cd hdlsrc K>> cd mhdltestcrcgenerator/ K>> qeMemoryInfo Peak physical memory used in this session is 3971.648840 MB K>> matlabroot ans = '/mathworks/devel/bat/Bspchdl/.zfs/snapshot/Bspchdl.1892852.pass/build/matlab' K>>