Messages report for PRU_FFT Fri Mar 03 17:28:12 2023 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Standard Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 18.1.1 Build 646 04/11/2019 SJ Standard Edition Info: Processing started: Fri Mar 03 15:40:03 2023 Info: Command: quartus_sta PRU_FFT -c PRU_FFT Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 100 degrees C Info (332104): Reading SDC File: 'FIFO_CAL_SIG/fifo_181/synth/FIFO_CAL_SIG_fifo_181_ntrg2bi.sdc' Info (332104): Reading SDC File: 'FIFO_CAL_REF/fifo_181/synth/FIFO_CAL_REF_fifo_181_jih2y4y.sdc' Info (332104): Reading SDC File: 'PRU_FFT.sdc' Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[2]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Info (332050): set_input_delay -clock { ADCCLK } -min 0.8 [get_ports {ADC_DATA[0] ADC_DATA[1] ADC_DATA[2] ADC_DATA[3] ADC_DATA[4] ADC_DATA[5] ADC_DATA[6] ADC_DATA[7] ADC_DATA[8] ADC_DATA[9] ADC_DATA[10] ADC_DATA[11] ADC_DATA[12] ADC_DATA[13]}] File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[6]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[0]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[4]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[8]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[12]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[10]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[3]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[7]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[1]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[5]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[9]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[13]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332054): Assignment set_input_delay is accepted but has some problems at PRU_FFT.sdc(11): Set_input_delay/set_output_delay has replaced one or more delays on port "ADC_DATA[11]". Please use -add_delay option if you meant to add additional constraints. File: C:/FPGA_Design/HDJ/PRU_FFT/PRU_FFT.sdc Line: 11 Warning (332070): Port "ADC_DATA[0]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[0]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[10]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[10]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[11]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[11]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[12]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[12]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[13]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[13]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[1]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[1]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[2]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[2]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[3]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[3]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[4]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[4]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[5]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[5]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[6]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[6]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[7]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[7]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[8]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[8]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Warning (332070): Port "ADC_DATA[9]" relative to the falling edge of clock "ADCCLK" does not specify a max-fall input delay Warning (332070): Port "ADC_DATA[9]" relative to the falling edge of clock "ADCCLK" does not specify a max-rise input delay Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 900mV 100C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. Info (332146): Worst-case setup slack is -0.519 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.519 -3.550 ADCCLK Info (332119): 0.815 0.000 USBCLK Info (332119): 40.371 0.000 SYSCLK Info (332146): Worst-case hold slack is 0.054 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.054 0.000 ADCCLK Info (332119): 0.054 0.000 SYSCLK Info (332119): 0.055 0.000 USBCLK Info (332146): Worst-case recovery slack is 47.933 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 47.933 0.000 SYSCLK Info (332146): Worst-case removal slack is 0.728 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.728 0.000 SYSCLK Info (332146): Worst-case minimum pulse width slack is 2.043 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.043 0.000 ADCCLK Info (332119): 4.587 0.000 USBCLK Info (332119): 24.900 0.000 SYSCLK Info (332119): 49.943 0.000 MCLK Info (332115): Worst-case slack is 3.352 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.396 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.239 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.282 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Slow 900mV 100C Model Net Delay Summary Info (332163): Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 3.158 4.000 0.842 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.246 4.000 0.754 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.283 4.000 0.717 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.321 4.000 0.679 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 6.998 8.000 1.002 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.058 8.000 0.942 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.381 8.000 0.619 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.389 8.000 0.611 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332114): Report Metastability: Found 75 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 75 Info (332114): Shortest Synchronizer Chain: 1 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.173 Info (332114): Worst Case Available Settling Time: 5.343 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Slow 900mV 0C Model Info (332146): Worst-case setup slack is -0.823 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.823 -7.591 ADCCLK Info (332119): 1.007 0.000 USBCLK Info (332119): 41.120 0.000 SYSCLK Info (332146): Worst-case hold slack is 0.047 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.047 0.000 ADCCLK Info (332119): 0.048 0.000 USBCLK Info (332119): 0.049 0.000 SYSCLK Info (332146): Worst-case recovery slack is 47.949 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 47.949 0.000 SYSCLK Info (332146): Worst-case removal slack is 0.769 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.769 0.000 SYSCLK Info (332146): Worst-case minimum pulse width slack is 2.006 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.006 0.000 ADCCLK Info (332119): 4.603 0.000 USBCLK Info (332119): 24.888 0.000 SYSCLK Info (332119): 49.889 0.000 MCLK Info (332115): Worst-case slack is 3.331 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.379 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.227 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.260 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Slow 900mV 0C Model Net Delay Summary Info (332163): Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 3.225 4.000 0.775 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.269 4.000 0.731 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.321 4.000 0.679 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.356 4.000 0.644 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.051 8.000 0.949 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.114 8.000 0.886 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.409 8.000 0.591 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.424 8.000 0.576 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332114): Report Metastability: Found 75 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 75 Info (332114): Shortest Synchronizer Chain: 1 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.173 Info (332114): Worst Case Available Settling Time: 5.586 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Fast 900mV 100C Model Info (332146): Worst-case setup slack is 0.077 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.077 0.000 ADCCLK Info (332119): 1.324 0.000 USBCLK Info (332119): 42.589 0.000 SYSCLK Info (332146): Worst-case hold slack is -0.094 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -0.094 -0.564 ADCCLK Info (332119): 0.021 0.000 SYSCLK Info (332119): 0.023 0.000 USBCLK Info (332146): Worst-case recovery slack is 48.642 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 48.642 0.000 SYSCLK Info (332146): Worst-case removal slack is 0.358 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.358 0.000 SYSCLK Info (332146): Worst-case minimum pulse width slack is 2.136 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.136 0.000 ADCCLK Info (332119): 4.585 0.000 USBCLK Info (332119): 24.917 0.000 SYSCLK Info (332119): 49.870 0.000 MCLK Info (332115): Worst-case slack is 3.619 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.642 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.534 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.568 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Fast 900mV 100C Model Net Delay Summary Info (332163): Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 3.450 4.000 0.550 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.505 4.000 0.495 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.535 4.000 0.465 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.554 4.000 0.446 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.262 8.000 0.738 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.338 8.000 0.662 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.603 8.000 0.397 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.622 8.000 0.378 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332114): Report Metastability: Found 75 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 75 Info (332114): Shortest Synchronizer Chain: 1 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.173 Info (332114): Worst Case Available Settling Time: 6.814 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Fast 900mV 0C Model Info (332146): Worst-case setup slack is 0.352 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.352 0.000 ADCCLK Info (332119): 1.570 0.000 USBCLK Info (332119): 43.855 0.000 SYSCLK Info (332146): Worst-case hold slack is 0.012 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.012 0.000 ADCCLK Info (332119): 0.017 0.000 SYSCLK Info (332119): 0.019 0.000 USBCLK Info (332146): Worst-case recovery slack is 48.796 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 48.796 0.000 SYSCLK Info (332146): Worst-case removal slack is 0.328 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.328 0.000 SYSCLK Info (332146): Worst-case minimum pulse width slack is 2.163 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.163 0.000 ADCCLK Info (332119): 4.472 0.000 USBCLK Info (332119): 24.957 0.000 SYSCLK Info (332119): 49.914 0.000 MCLK Info (332115): Worst-case slack is 3.671 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.695 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.601 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.608 for "set_max_skew -from [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Fast 900mV 0C Model Net Delay Summary Info (332163): Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 3.556 4.000 0.444 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.583 4.000 0.417 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.621 4.000 0.379 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 3.633 4.000 0.367 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.377 8.000 0.623 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.440 8.000 0.560 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.683 8.000 0.317 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_REF0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): Info (332163): set_net_delay 7.701 8.000 0.299 [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {CAL_FUNC0|CAL_FIFO0|FIFO_CAL_SIG0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332114): Report Metastability: Found 75 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 75 Info (332114): Shortest Synchronizer Chain: 1 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.173 Info (332114): Worst Case Available Settling Time: 7.293 ns Info (332114): Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 44 warnings Info: Peak virtual memory: 6364 megabytes Info: Processing ended: Fri Mar 03 15:40:40 2023 Info: Elapsed time: 00:00:37 Info: Total CPU time (on all processors): 00:00:58