Info: *******************************************************************
Info: Running Quartus Prime IP Generation Tool
	Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition
	Info: Processing started: Thu Apr 13 16:01:30 2023
Info: Command: quartus_ipgenerate emif_example -c emif_example --run_default_mode_op
Info: Found 24 IP file(s) in the project.
	Info: IP file D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3.ip was found in the project.
	Info: IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0.ip was found in the project.
	Info: IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_tg.ip was found in the project.
	Info: IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_global_reset_n_splitter.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_i2c_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_nios2_gen2_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_reset_in.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_nios2_gen2_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_iopll_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_onchip_memory2_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_1.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_jtag_uart_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_emif_c10_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_jtag_uart_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_1.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_1.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_clock_bridge_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_onchip_memory2_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_sysid_qsys_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_mm_clock_crossing_bridge_0.ip was found in the project.
	Info: IP file C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_mm_bridge_0.ip was found in the project.
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_i2c_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_i2c_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_i2c_0/nios_i2c_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_i2c_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_i2c_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_i2c_0.i2c_0: log2_fifo_depth = 2
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_i2c_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_i2c_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_i2c_0.i2c_0: log2_fifo_depth = 2
Info: nios_i2c_0: "Transforming system: nios_i2c_0"
Info: nios_i2c_0: "Naming system components in system: nios_i2c_0"
Info: nios_i2c_0: "Processing generation queue"
Info: nios_i2c_0: "Generating: nios_i2c_0"
Info: nios_i2c_0: "Generating: altera_avalon_i2c"
Info: nios_i2c_0: Done "nios_i2c_0" with 2 modules, 12 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_i2c_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_0/nios_pio_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_pio_0: "Transforming system: nios_pio_0"
Info: nios_pio_0: "Naming system components in system: nios_pio_0"
Info: nios_pio_0: "Processing generation queue"
Info: nios_pio_0: "Generating: nios_pio_0"
Info: nios_pio_0: "Generating: nios_pio_0_altera_avalon_pio_181_6w3cpzy"
Info: pio_0: Starting RTL generation for module 'nios_pio_0_altera_avalon_pio_181_6w3cpzy'
Info: pio_0:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_pio_0_altera_avalon_pio_181_6w3cpzy --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_8717603855777679888.dir/0002_pio_0_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_8717603855777679888.dir/0002_pio_0_gen//nios_pio_0_altera_avalon_pio_181_6w3cpzy_component_configuration.pl  --do_build_sim=0  ]
Info: pio_0: Done RTL generation for module 'nios_pio_0_altera_avalon_pio_181_6w3cpzy'
Info: nios_pio_0: Done "nios_pio_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_nios2_gen2_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_nios2_gen2_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_nios2_gen2_0/cpu_subsystem_nios2_gen2_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_nios2_gen2_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_nios2_gen2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_nios2_gen2_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_nios2_gen2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_nios2_gen2_0: "Transforming system: cpu_subsystem_nios2_gen2_0"
Info: cpu_subsystem_nios2_gen2_0: "Naming system components in system: cpu_subsystem_nios2_gen2_0"
Info: cpu_subsystem_nios2_gen2_0: "Processing generation queue"
Info: cpu_subsystem_nios2_gen2_0: "Generating: cpu_subsystem_nios2_gen2_0"
Info: cpu_subsystem_nios2_gen2_0: "Generating: cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_181_e6ezmda"
Info: cpu_subsystem_nios2_gen2_0: "Generating: cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_unit_181_y574vhq"
Info: cpu: Starting RTL generation for module 'cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_unit_181_y574vhq'
Info: cpu:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64//eperlcmd.exe -I D:/intelfpga_pro/18.1/quartus/bin64//perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_unit_181_y574vhq --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_2549443956746563021.dir/0002_cpu_gen/ --quartus_bindir=D:/intelfpga_pro/18.1/quartus/bin64/ --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_2549443956746563021.dir/0002_cpu_gen//cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_unit_181_y574vhq_processor_configuration.pl  --do_build_sim=0    --pro_version=1  ]
Info: cpu: Starting Nios II generation
Info: cpu: Checking for plaintext license.
Info: cpu: Couldn't query license setup in Quartus directory D:/intelfpga_pro/18.1/quartus/bin64/
Info: cpu: Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: LM_LICENSE_FILE environment variable is empty
Info: cpu: Plaintext license not found.
Info: cpu: Checking for encrypted license (non-evaluation).
Info: cpu: Couldn't query license setup in Quartus directory D:/intelfpga_pro/18.1/quartus/bin64/
Info: cpu: Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: LM_LICENSE_FILE environment variable is empty
Info: cpu: Encrypted license not found.  Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: Elaborating CPU configuration settings
Info: cpu: Creating all objects for CPU
Info: cpu: Testbench
Info: cpu: Instruction decoding
Info: cpu: Instruction fields
Info: cpu: Instruction decodes
Info: cpu: Signals for RTL simulation waveforms
Info: cpu: Instruction controls
Info: cpu: Pipeline frontend
Info: cpu: Pipeline backend
Info: cpu: Generating RTL from CPU objects
Info: cpu: Creating encrypted RTL
Info: cpu: Done Nios II generation
Info: cpu: Done RTL generation for module 'cpu_subsystem_nios2_gen2_0_altera_nios2_gen2_unit_181_y574vhq'
Info: cpu_subsystem_nios2_gen2_0: Done "cpu_subsystem_nios2_gen2_0" with 3 modules, 16 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_nios2_gen2_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_reset_in.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_reset_in.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_reset_in/nios_reset_in_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_reset_in.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_reset_in --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_reset_in.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_reset_in --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_reset_in: "Transforming system: nios_reset_in"
Info: nios_reset_in: "Naming system components in system: nios_reset_in"
Info: nios_reset_in: "Processing generation queue"
Info: nios_reset_in: "Generating: nios_reset_in"
Info: nios_reset_in: Done "nios_reset_in" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_reset_in.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_nios2_gen2_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_nios2_gen2_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_nios2_gen2_0/nios_nios2_gen2_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_nios2_gen2_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_nios2_gen2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_nios2_gen2_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_nios2_gen2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_nios2_gen2_0: "Transforming system: nios_nios2_gen2_0"
Info: nios_nios2_gen2_0: "Naming system components in system: nios_nios2_gen2_0"
Info: nios_nios2_gen2_0: "Processing generation queue"
Info: nios_nios2_gen2_0: "Generating: nios_nios2_gen2_0"
Info: nios_nios2_gen2_0: "Generating: nios_nios2_gen2_0_altera_nios2_gen2_181_7l3snzy"
Info: nios_nios2_gen2_0: "Generating: nios_nios2_gen2_0_altera_nios2_gen2_unit_181_a4t3jyi"
Info: cpu: Starting RTL generation for module 'nios_nios2_gen2_0_altera_nios2_gen2_unit_181_a4t3jyi'
Info: cpu:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64//eperlcmd.exe -I D:/intelfpga_pro/18.1/quartus/bin64//perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/intelfpga_pro/18.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=nios_nios2_gen2_0_altera_nios2_gen2_unit_181_a4t3jyi --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_5327660807507382307.dir/0002_cpu_gen/ --quartus_bindir=D:/intelfpga_pro/18.1/quartus/bin64/ --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_5327660807507382307.dir/0002_cpu_gen//nios_nios2_gen2_0_altera_nios2_gen2_unit_181_a4t3jyi_processor_configuration.pl  --do_build_sim=0    --pro_version=1  ]
Info: cpu: Starting Nios II generation
Info: cpu: Checking for plaintext license.
Info: cpu: Couldn't query license setup in Quartus directory D:/intelfpga_pro/18.1/quartus/bin64/
Info: cpu: Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: LM_LICENSE_FILE environment variable is empty
Info: cpu: Plaintext license not found.
Info: cpu: Checking for encrypted license (non-evaluation).
Info: cpu: Couldn't query license setup in Quartus directory D:/intelfpga_pro/18.1/quartus/bin64/
Info: cpu: Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: LM_LICENSE_FILE environment variable is empty
Info: cpu: Encrypted license not found.  Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: Elaborating CPU configuration settings
Info: cpu: Creating all objects for CPU
Info: cpu: Testbench
Info: cpu: Instruction decoding
Info: cpu: Instruction fields
Info: cpu: Instruction decodes
Info: cpu: Signals for RTL simulation waveforms
Info: cpu: Instruction controls
Info: cpu: Pipeline frontend
Info: cpu: Pipeline backend
Info: cpu: Generating RTL from CPU objects
Info: cpu: Creating encrypted RTL
Info: cpu: Done Nios II generation
Info: cpu: Done RTL generation for module 'nios_nios2_gen2_0_altera_nios2_gen2_unit_181_a4t3jyi'
Info: nios_nios2_gen2_0: Done "nios_nios2_gen2_0" with 3 modules, 16 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_nios2_gen2_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_iopll_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_iopll_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_iopll_0/nios_iopll_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_iopll_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_iopll_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_iopll_0.iopll_0: Able to implement PLL with user settings
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_iopll_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_iopll_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_iopll_0.iopll_0: Able to implement PLL with user settings
Info: nios_iopll_0: "Transforming system: nios_iopll_0"
Info: nios_iopll_0: "Naming system components in system: nios_iopll_0"
Info: nios_iopll_0: "Processing generation queue"
Info: nios_iopll_0: "Generating: nios_iopll_0"
Info: nios_iopll_0: "Generating: nios_iopll_0_altera_iopll_181_m6f5jfq"
Info: nios_iopll_0: Done "nios_iopll_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_iopll_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_onchip_memory2_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_onchip_memory2_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_onchip_memory2_0/nios_onchip_memory2_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_onchip_memory2_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_onchip_memory2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_onchip_memory2_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_onchip_memory2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_onchip_memory2_0: "Transforming system: nios_onchip_memory2_0"
Info: nios_onchip_memory2_0: "Naming system components in system: nios_onchip_memory2_0"
Info: nios_onchip_memory2_0: "Processing generation queue"
Info: nios_onchip_memory2_0: "Generating: nios_onchip_memory2_0"
Info: nios_onchip_memory2_0: "Generating: nios_onchip_memory2_0_altera_avalon_onchip_memory2_181_enfkagq"
Info: onchip_memory2_0: Starting RTL generation for module 'nios_onchip_memory2_0_altera_avalon_onchip_memory2_181_enfkagq'
Info: onchip_memory2_0:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_onchip_memory2_0_altera_avalon_onchip_memory2_181_enfkagq --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_1295475985374087410.dir/0002_onchip_memory2_0_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_1295475985374087410.dir/0002_onchip_memory2_0_gen//nios_onchip_memory2_0_altera_avalon_onchip_memory2_181_enfkagq_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_memory2_0: Done RTL generation for module 'nios_onchip_memory2_0_altera_avalon_onchip_memory2_181_enfkagq'
Info: nios_onchip_memory2_0: Done "nios_onchip_memory2_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_onchip_memory2_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_0/cpu_subsystem_clock_bridge_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_clock_bridge_0: "Transforming system: cpu_subsystem_clock_bridge_0"
Info: cpu_subsystem_clock_bridge_0: "Naming system components in system: cpu_subsystem_clock_bridge_0"
Info: cpu_subsystem_clock_bridge_0: "Processing generation queue"
Info: cpu_subsystem_clock_bridge_0: "Generating: cpu_subsystem_clock_bridge_0"
Info: cpu_subsystem_clock_bridge_0: Done "cpu_subsystem_clock_bridge_0" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_1.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_1.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_1/cpu_subsystem_clock_bridge_1_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_1.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_1.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_clock_bridge_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_clock_bridge_1: "Transforming system: cpu_subsystem_clock_bridge_1"
Info: cpu_subsystem_clock_bridge_1: "Naming system components in system: cpu_subsystem_clock_bridge_1"
Info: cpu_subsystem_clock_bridge_1: "Processing generation queue"
Info: cpu_subsystem_clock_bridge_1: "Generating: cpu_subsystem_clock_bridge_1"
Info: cpu_subsystem_clock_bridge_1: Done "cpu_subsystem_clock_bridge_1" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_clock_bridge_1.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_jtag_uart_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_jtag_uart_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_jtag_uart_0/cpu_subsystem_jtag_uart_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_jtag_uart_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_jtag_uart_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Warning: cpu_subsystem_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_jtag_uart_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_jtag_uart_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Warning: cpu_subsystem_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: cpu_subsystem_jtag_uart_0: "Transforming system: cpu_subsystem_jtag_uart_0"
Info: cpu_subsystem_jtag_uart_0: "Naming system components in system: cpu_subsystem_jtag_uart_0"
Info: cpu_subsystem_jtag_uart_0: "Processing generation queue"
Info: cpu_subsystem_jtag_uart_0: "Generating: cpu_subsystem_jtag_uart_0"
Info: cpu_subsystem_jtag_uart_0: "Generating: cpu_subsystem_jtag_uart_0_altera_avalon_jtag_uart_181_64sw7rq"
Info: jtag_uart_0: Starting RTL generation for module 'cpu_subsystem_jtag_uart_0_altera_avalon_jtag_uart_181_64sw7rq'
Info: jtag_uart_0:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=cpu_subsystem_jtag_uart_0_altera_avalon_jtag_uart_181_64sw7rq --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_591209060211273940.dir/0002_jtag_uart_0_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_591209060211273940.dir/0002_jtag_uart_0_gen//cpu_subsystem_jtag_uart_0_altera_avalon_jtag_uart_181_64sw7rq_component_configuration.pl  --do_build_sim=0  ]
Info: jtag_uart_0: Done RTL generation for module 'cpu_subsystem_jtag_uart_0_altera_avalon_jtag_uart_181_64sw7rq'
Info: cpu_subsystem_jtag_uart_0: Done "cpu_subsystem_jtag_uart_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_jtag_uart_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_emif_c10_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_emif_c10_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_emif_c10_0/nios_emif_c10_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_emif_c10_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_emif_c10_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_emif_c10_0.emif_c10_0: For accurate timing analysis, please simulate your board with selected termination values and update Board Timing information.
Info: nios_emif_c10_0.emif_c10_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency.
Info: nios_emif_c10_0.emif_c10_0.arch: Placement of address/command pins must follow "DDR3 Scheme 2: Component/UDIMM/SODIMM".
Info: nios_emif_c10_0.emif_c10_0.arch: Interface estimated to require 2 I/O Bank(s) and 2 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior.
Info: nios_emif_c10_0.emif_c10_0.arch: Valid memory frequencies for the current PLL reference clock and user clock rate, in MHz: 800.0
Info: nios_emif_c10_0.emif_c10_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_emif_c10_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_emif_c10_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_emif_c10_0.emif_c10_0: For accurate timing analysis, please simulate your board with selected termination values and update Board Timing information.
Info: nios_emif_c10_0.emif_c10_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency.
Info: nios_emif_c10_0.emif_c10_0.arch: Placement of address/command pins must follow "DDR3 Scheme 2: Component/UDIMM/SODIMM".
Info: nios_emif_c10_0.emif_c10_0.arch: Interface estimated to require 2 I/O Bank(s) and 2 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior.
Info: nios_emif_c10_0.emif_c10_0.arch: Valid memory frequencies for the current PLL reference clock and user clock rate, in MHz: 800.0
Info: nios_emif_c10_0.emif_c10_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation.
Info: nios_emif_c10_0: "Transforming system: nios_emif_c10_0"
Info: Interconnect is inserted between master col_if.to_ioaux and slave arch.cal_debug because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master col_if.to_ioaux and slave arch.cal_debug because the master has address signal 30 bit wide, but the slave is 24 bit wide.
Info: Interconnect is inserted between master col_if.to_ioaux and slave arch.cal_debug because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master colmaster.master and slave avl_bridge_out.s0 because the master has address signal 32 bit wide, but the slave is 30 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has burstcount signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has address signal 16 bit wide, but the slave is 12 bit wide.
Info: Interconnect is inserted between master ioaux_master_bridge.m0 and slave ioaux_soft_ram.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
Info: nios_emif_c10_0: "Naming system components in system: nios_emif_c10_0"
Info: nios_emif_c10_0: "Processing generation queue"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_emif_c10_181_jk7txni"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_emif_arch_nf_181_ivxomhi"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_ip_col_if_181_4xvd2vi"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_emif_cal_slave_nf_181_34trbdq"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_mm_interconnect_181_ocsjbri"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_avalon_mm_bridge_181_osihcfi"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_alt_mem_if_jtag_master_181_luwzn6i"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_mm_interconnect_181_ucgegiq"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_avalon_onchip_memory2_181_kt6usya"
Info: ioaux_soft_ram: Starting RTL generation for module 'nios_emif_c10_0_altera_avalon_onchip_memory2_181_kt6usya'
Info: ioaux_soft_ram:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_emif_c10_0_altera_avalon_onchip_memory2_181_kt6usya --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_874449325279295118.dir/0004_ioaux_soft_ram_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_874449325279295118.dir/0004_ioaux_soft_ram_gen//nios_emif_c10_0_altera_avalon_onchip_memory2_181_kt6usya_component_configuration.pl  --do_build_sim=0  ]
Info: ioaux_soft_ram: Done RTL generation for module 'nios_emif_c10_0_altera_avalon_onchip_memory2_181_kt6usya'
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_mm_interconnect_181_p7jgxoq"
Info: nios_emif_c10_0: "Generating: altera_reset_controller"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_merlin_master_translator_181_mhudjri"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_merlin_slave_translator_181_5aswt6a"
Info: nios_emif_c10_0: "Generating: altera_avalon_st_jtag_interface"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_timing_adapter_181_5bygnli"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_altera_avalon_sc_fifo_181_hseo73i"
Info: nios_emif_c10_0: "Generating: altera_avalon_st_bytes_to_packets"
Info: nios_emif_c10_0: "Generating: altera_avalon_st_packets_to_bytes"
Info: nios_emif_c10_0: "Generating: altera_avalon_packets_to_master"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_channel_adapter_181_brosi3y"
Info: nios_emif_c10_0: "Generating: nios_emif_c10_0_channel_adapter_181_imsynky"
Info: nios_emif_c10_0: Done "nios_emif_c10_0" with 22 modules, 85 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_emif_c10_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_jtag_uart_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_jtag_uart_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_jtag_uart_0/nios_jtag_uart_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_jtag_uart_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_jtag_uart_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_jtag_uart_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_jtag_uart_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: nios_jtag_uart_0: "Transforming system: nios_jtag_uart_0"
Info: nios_jtag_uart_0: "Naming system components in system: nios_jtag_uart_0"
Info: nios_jtag_uart_0: "Processing generation queue"
Info: nios_jtag_uart_0: "Generating: nios_jtag_uart_0"
Info: nios_jtag_uart_0: "Generating: nios_jtag_uart_0_altera_avalon_jtag_uart_181_mus246q"
Info: jtag_uart_0: Starting RTL generation for module 'nios_jtag_uart_0_altera_avalon_jtag_uart_181_mus246q'
Info: jtag_uart_0:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_jtag_uart_0_altera_avalon_jtag_uart_181_mus246q --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_3286748156211187969.dir/0002_jtag_uart_0_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_3286748156211187969.dir/0002_jtag_uart_0_gen//nios_jtag_uart_0_altera_avalon_jtag_uart_181_mus246q_component_configuration.pl  --do_build_sim=0  ]
Info: jtag_uart_0: Done RTL generation for module 'nios_jtag_uart_0_altera_avalon_jtag_uart_181_mus246q'
Info: nios_jtag_uart_0: Done "nios_jtag_uart_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_jtag_uart_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_1.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_1.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_1/nios_pio_1_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_1.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_pio_1.pio_1: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_1.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_pio_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_pio_1.pio_1: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: nios_pio_1: "Transforming system: nios_pio_1"
Info: nios_pio_1: "Naming system components in system: nios_pio_1"
Info: nios_pio_1: "Processing generation queue"
Info: nios_pio_1: "Generating: nios_pio_1"
Info: nios_pio_1: "Generating: nios_pio_1_altera_avalon_pio_181_vyckmwa"
Info: pio_1: Starting RTL generation for module 'nios_pio_1_altera_avalon_pio_181_vyckmwa'
Info: pio_1:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_pio_1_altera_avalon_pio_181_vyckmwa --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_5890707912647496951.dir/0002_pio_1_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_5890707912647496951.dir/0002_pio_1_gen//nios_pio_1_altera_avalon_pio_181_vyckmwa_component_configuration.pl  --do_build_sim=0  ]
Info: pio_1: Done RTL generation for module 'nios_pio_1_altera_avalon_pio_181_vyckmwa'
Info: nios_pio_1: Done "nios_pio_1" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_pio_1.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_1.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_1.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_1/cpu_subsystem_reset_bridge_1_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_1.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_1.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_1 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_reset_bridge_1: "Transforming system: cpu_subsystem_reset_bridge_1"
Info: cpu_subsystem_reset_bridge_1: "Naming system components in system: cpu_subsystem_reset_bridge_1"
Info: cpu_subsystem_reset_bridge_1: "Processing generation queue"
Info: cpu_subsystem_reset_bridge_1: "Generating: cpu_subsystem_reset_bridge_1"
Info: cpu_subsystem_reset_bridge_1: Done "cpu_subsystem_reset_bridge_1" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_1.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_clock_bridge_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_clock_bridge_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_clock_bridge_0/nios_clock_bridge_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_clock_bridge_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_clock_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_clock_bridge_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_clock_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_clock_bridge_0: "Transforming system: nios_clock_bridge_0"
Info: nios_clock_bridge_0: "Naming system components in system: nios_clock_bridge_0"
Info: nios_clock_bridge_0: "Processing generation queue"
Info: nios_clock_bridge_0: "Generating: nios_clock_bridge_0"
Info: nios_clock_bridge_0: Done "nios_clock_bridge_0" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_clock_bridge_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_0/cpu_subsystem_reset_bridge_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_reset_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_reset_bridge_0: "Transforming system: cpu_subsystem_reset_bridge_0"
Info: cpu_subsystem_reset_bridge_0: "Naming system components in system: cpu_subsystem_reset_bridge_0"
Info: cpu_subsystem_reset_bridge_0: "Processing generation queue"
Info: cpu_subsystem_reset_bridge_0: "Generating: cpu_subsystem_reset_bridge_0"
Info: cpu_subsystem_reset_bridge_0: Done "cpu_subsystem_reset_bridge_0" with 1 modules, 1 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_reset_bridge_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_onchip_memory2_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_onchip_memory2_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_onchip_memory2_0/cpu_subsystem_onchip_memory2_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_onchip_memory2_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_onchip_memory2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_onchip_memory2_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_onchip_memory2_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_onchip_memory2_0: "Transforming system: cpu_subsystem_onchip_memory2_0"
Info: cpu_subsystem_onchip_memory2_0: "Naming system components in system: cpu_subsystem_onchip_memory2_0"
Info: cpu_subsystem_onchip_memory2_0: "Processing generation queue"
Info: cpu_subsystem_onchip_memory2_0: "Generating: cpu_subsystem_onchip_memory2_0"
Info: cpu_subsystem_onchip_memory2_0: "Generating: cpu_subsystem_onchip_memory2_0_altera_avalon_onchip_memory2_181_52bkgsi"
Info: onchip_memory2_0: Starting RTL generation for module 'cpu_subsystem_onchip_memory2_0_altera_avalon_onchip_memory2_181_52bkgsi'
Info: onchip_memory2_0:   Generation command is [exec D:/intelfpga_pro/18.1/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga_pro/18.1/quartus/bin64/perl/lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/europa -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga_pro/18.1/quartus/sopc_builder/bin -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga_pro/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=cpu_subsystem_onchip_memory2_0_altera_avalon_onchip_memory2_181_52bkgsi --dir=C:/Users/jekim/AppData/Local/Temp/alt9460_6336558072399247060.dir/0002_onchip_memory2_0_gen/ --quartus_dir=D:/intelfpga_pro/18.1/quartus --verilog --config=C:/Users/jekim/AppData/Local/Temp/alt9460_6336558072399247060.dir/0002_onchip_memory2_0_gen//cpu_subsystem_onchip_memory2_0_altera_avalon_onchip_memory2_181_52bkgsi_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_memory2_0: Done RTL generation for module 'cpu_subsystem_onchip_memory2_0_altera_avalon_onchip_memory2_181_52bkgsi'
Info: cpu_subsystem_onchip_memory2_0: Done "cpu_subsystem_onchip_memory2_0" with 2 modules, 3 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_onchip_memory2_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_sysid_qsys_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_sysid_qsys_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_sysid_qsys_0/nios_sysid_qsys_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_sysid_qsys_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_sysid_qsys_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_sysid_qsys_0.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: nios_sysid_qsys_0.sysid_qsys_0: Time stamp will be automatically updated when this component is generated.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_sysid_qsys_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_sysid_qsys_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_sysid_qsys_0.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: nios_sysid_qsys_0.sysid_qsys_0: Time stamp will be automatically updated when this component is generated.
Info: nios_sysid_qsys_0: "Transforming system: nios_sysid_qsys_0"
Info: nios_sysid_qsys_0: "Naming system components in system: nios_sysid_qsys_0"
Info: nios_sysid_qsys_0: "Processing generation queue"
Info: nios_sysid_qsys_0: "Generating: nios_sysid_qsys_0"
Info: nios_sysid_qsys_0: "Generating: altera_avalon_sysid_qsys"
Info: nios_sysid_qsys_0: Done "nios_sysid_qsys_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_sysid_qsys_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_mm_clock_crossing_bridge_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_mm_clock_crossing_bridge_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_mm_clock_crossing_bridge_0/nios_mm_clock_crossing_bridge_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_mm_clock_crossing_bridge_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_mm_clock_crossing_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_mm_clock_crossing_bridge_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\nios\nios_mm_clock_crossing_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: nios_mm_clock_crossing_bridge_0: "Transforming system: nios_mm_clock_crossing_bridge_0"
Info: nios_mm_clock_crossing_bridge_0: "Naming system components in system: nios_mm_clock_crossing_bridge_0"
Info: nios_mm_clock_crossing_bridge_0: "Processing generation queue"
Info: nios_mm_clock_crossing_bridge_0: "Generating: nios_mm_clock_crossing_bridge_0"
Info: nios_mm_clock_crossing_bridge_0: "Generating: nios_mm_clock_crossing_bridge_0_altera_avalon_mm_clock_crossing_bridge_181_vjv6npq"
Info: nios_mm_clock_crossing_bridge_0: Done "nios_mm_clock_crossing_bridge_0" with 2 modules, 6 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios/nios_mm_clock_crossing_bridge_0.ip
Info: Elaborating Platform Designer IP entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_mm_bridge_0.ip.
Info: Only synthesis files will be generated.
Info: Performing IP Generation using the command line: d:/intelfpga_pro/18.1/quartus/../qsys/bin/qsys-generate.exe --top-level-generation=true {--family=Cyclone 10 GX} --synthesis=verilog --part=10CX105YF780E5G --block-symbol-file --pro --quartus-project=D:/intelFPGA_pro/18.1/example_design/emif_example --rev=emif_example C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_mm_bridge_0.ip
Info: Saving generation log to C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_mm_bridge_0/cpu_subsystem_mm_bridge_0_generation.rpt
Info: Generated by version: 18.1 build 222
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_mm_bridge_0.ip --block-symbol-file --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_mm_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_mm_bridge_0.ip --synthesis=VERILOG --output-directory=C:\designs\DB10CGX085\boardtests\Boardtest_ECC_800MHz\ip\cpu_subsystem\cpu_subsystem_mm_bridge_0 --family="Cyclone 10 GX" --part=10CX105YF780E5G
Info: cpu_subsystem_mm_bridge_0: "Transforming system: cpu_subsystem_mm_bridge_0"
Info: cpu_subsystem_mm_bridge_0: "Naming system components in system: cpu_subsystem_mm_bridge_0"
Info: cpu_subsystem_mm_bridge_0: "Processing generation queue"
Info: cpu_subsystem_mm_bridge_0: "Generating: cpu_subsystem_mm_bridge_0"
Info: cpu_subsystem_mm_bridge_0: "Generating: cpu_subsystem_mm_bridge_0_altera_avalon_mm_bridge_181_osihcfi"
Info: cpu_subsystem_mm_bridge_0: Done "cpu_subsystem_mm_bridge_0" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Finished elaborating Platform Designer system entity C:/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem/cpu_subsystem_mm_bridge_0.ip
Info: Finished generating IP file(s) in the project.
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_tg).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_tg.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
	Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_global_reset_n_splitter).
	Info: Skipped generation of synthesis files for the Platform Designer IP file D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_global_reset_n_splitter.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
Info: Quartus Prime IP Generation Tool was successful. 0 errors, 2 warnings
	Info: Peak virtual memory: 4734 megabytes
	Info: Processing ended: Thu Apr 13 16:04:08 2023
	Info: Elapsed time: 00:02:38
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_i2c_0/nios_i2c_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_i2c_0/nios_i2c_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_0/nios_pio_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_0/nios_pio_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_nios2_gen2_0/cpu_subsystem_nios2_gen2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_nios2_gen2_0/cpu_subsystem_nios2_gen2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_reset_in/nios_reset_in.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_reset_in/nios_reset_in.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_nios2_gen2_0/nios_nios2_gen2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_nios2_gen2_0/nios_nios2_gen2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_iopll_0/nios_iopll_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_iopll_0/nios_iopll_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_onchip_memory2_0/nios_onchip_memory2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_onchip_memory2_0/nios_onchip_memory2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_0/cpu_subsystem_clock_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_0/cpu_subsystem_clock_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_1/cpu_subsystem_clock_bridge_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_1/cpu_subsystem_clock_bridge_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_jtag_uart_0/cpu_subsystem_jtag_uart_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_jtag_uart_0/cpu_subsystem_jtag_uart_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_emif_c10_0/nios_emif_c10_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_emif_c10_0/nios_emif_c10_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_jtag_uart_0/nios_jtag_uart_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_jtag_uart_0/nios_jtag_uart_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_1/nios_pio_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_1/nios_pio_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_1/cpu_subsystem_reset_bridge_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_1/cpu_subsystem_reset_bridge_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_clock_bridge_0/nios_clock_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_clock_bridge_0/nios_clock_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_0/cpu_subsystem_reset_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_0/cpu_subsystem_reset_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_onchip_memory2_0/cpu_subsystem_onchip_memory2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_onchip_memory2_0/cpu_subsystem_onchip_memory2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_sysid_qsys_0/nios_sysid_qsys_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_sysid_qsys_0/nios_sysid_qsys_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_mm_clock_crossing_bridge_0/nios_mm_clock_crossing_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_mm_clock_crossing_bridge_0/nios_mm_clock_crossing_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_mm_bridge_0/cpu_subsystem_mm_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_mm_bridge_0/cpu_subsystem_mm_bridge_0.qip Line: 1
Info: *******************************************************************
Info: Running Quartus Prime Synthesis
	Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition
	Info: Processing started: Thu Apr 13 16:04:09 2023
Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off emif_example -c emif_example
Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis...
Info: Project = "emif_example"
Info: Revision = "emif_example"
Info: Analyzing source files
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_oct.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_oct.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_o.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_o.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_df.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_df.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_se.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_bdir_se.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_cp_i.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_cp_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_i.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_df_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_i.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_i.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_o.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_udir_se_o.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_core_clks_rsts.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_core_clks_rsts.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_abphy.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_abphy.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_encrypted_abphy.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_encrypted_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_bufs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_unused.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_buf_unused.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_cal_counter.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_cal_counter.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_fast_sim.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_fast_sim.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_extra_clks.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_pll_extra_clks.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hps_clks_rsts.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hps_clks_rsts.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_io_tiles_wrap.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_abphy_mux.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_abphy_mux.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_avl_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_avl_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_sideband_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_sideband_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_mmr_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_mmr_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_amm_data_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_amm_data_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_ast_data_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_hmc_ast_data_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_afi_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_afi_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_seq_if.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_regs.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_emif_arch_nf_regs.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_oct.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_oct.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_oct_um_fsm.sv" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_oct_um_fsm.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/altera_std_synchronizer_nocut.v" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_std_synchronizer_nocut.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_reset_controller_181/synth/altera_reset_controller.v" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_reset_controller_181/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_reset_controller_181/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_reset_controller_181/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Info (18237): File "D:/intelFPGA_pro/18.1/example_design/emif_c10_0_example_design/ip/ed_synth/ed_synth_emif_c10_0/altera_avalon_onchip_memory2_181/synth/seq_cal_soft_m20k.hex" is a duplicate of already analyzed file "D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_avalon_onchip_memory2_181/synth/seq_cal_soft_m20k.hex" (same filename, same library name and same md5 digest). Skipping analysis of this file.
Warning (13228): Verilog HDL or VHDL warning at altera_oct.sv(190): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/altera_emif_arch_nf_181/synth/altera_oct.sv Line: 190
Info: Elaborating from top-level entity "cyclone10_ddr3"
Info (18235): Library search order is as follows: "altera_emif_arch_nf_181; altera_avalon_mm_bridge_181; altera_avalon_onchip_memory2_181; altera_merlin_master_translator_181; altera_merlin_slave_translator_181; altera_mm_interconnect_181; altera_reset_controller_181; altera_emif_cal_slave_nf_181; altera_emif_c10_181; cyclone10_ddr3; altera_jtag_dc_streaming_181; timing_adapter_181; altera_avalon_sc_fifo_181; altera_avalon_st_bytes_to_packets_181; altera_avalon_st_packets_to_bytes_181; altera_avalon_packets_to_master_181; channel_adapter_181; alt_mem_if_jtag_master_181; altera_ip_col_if_181; ed_synth_emif_c10_0; altera_emif_tg_avl_181; ed_synth_tg; ed_synth_global_reset_n_splitter; ctp". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.
Info: Found 123 design entities
Info: There are 179 partitions after elaboration.
Info: Creating instance-specific data models and dissolving soft partitions
Info (18299): Expanding entity and wildcard assignments.
Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:00
Info: found pre-synthesis snapshots for 1 partition(s)
Info: Synthesizing partition "root_partition"
Info (286030): Timing-Driven Synthesis is running
Info (17049): 91 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 1050 device resources after synthesis - the final resource count might be different
	Info (21058): Implemented 397 input pins
	Info (21059): Implemented 358 output pins
	Info (21060): Implemented 50 bidirectional pins
	Info (21061): Implemented 192 logic cells
	Info (21064): Implemented 32 RAM segments
Info: Successfully synthesized partition
Info: Saving post-synthesis snapshots for 1 partition(s)
Info: Quartus Prime Synthesis was successful. 0 errors, 21 warnings
	Info: Peak virtual memory: 5236 megabytes
	Info: Processing ended: Thu Apr 13 16:04:29 2023
	Info: Elapsed time: 00:00:20
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_i2c_0/nios_i2c_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_i2c_0/nios_i2c_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_0/nios_pio_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_0/nios_pio_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_nios2_gen2_0/cpu_subsystem_nios2_gen2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_nios2_gen2_0/cpu_subsystem_nios2_gen2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_reset_in/nios_reset_in.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_reset_in/nios_reset_in.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_nios2_gen2_0/nios_nios2_gen2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_nios2_gen2_0/nios_nios2_gen2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_iopll_0/nios_iopll_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_iopll_0/nios_iopll_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_onchip_memory2_0/nios_onchip_memory2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_onchip_memory2_0/nios_onchip_memory2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_0/cpu_subsystem_clock_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_0/cpu_subsystem_clock_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_1/cpu_subsystem_clock_bridge_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_clock_bridge_1/cpu_subsystem_clock_bridge_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_jtag_uart_0/cpu_subsystem_jtag_uart_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_jtag_uart_0/cpu_subsystem_jtag_uart_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_emif_c10_0/nios_emif_c10_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_emif_c10_0/nios_emif_c10_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_jtag_uart_0/nios_jtag_uart_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_jtag_uart_0/nios_jtag_uart_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_1/nios_pio_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_pio_1/nios_pio_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_1/cpu_subsystem_reset_bridge_1.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_1/cpu_subsystem_reset_bridge_1.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_clock_bridge_0/nios_clock_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_clock_bridge_0/nios_clock_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_0/cpu_subsystem_reset_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_reset_bridge_0/cpu_subsystem_reset_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_onchip_memory2_0/cpu_subsystem_onchip_memory2_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_onchip_memory2_0/cpu_subsystem_onchip_memory2_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_sysid_qsys_0/nios_sysid_qsys_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_sysid_qsys_0/nios_sysid_qsys_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_mm_clock_crossing_bridge_0/nios_mm_clock_crossing_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/nios//nios_mm_clock_crossing_bridge_0/nios_mm_clock_crossing_bridge_0.qip Line: 1
Critical Warning (20243): QIP file "/designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_mm_bridge_0/cpu_subsystem_mm_bridge_0.qip" does not exist File: /designs/DB10CGX085/boardtests/Boardtest_ECC_800MHz/ip/cpu_subsystem//cpu_subsystem_mm_bridge_0/cpu_subsystem_mm_bridge_0.qip Line: 1
Info: *******************************************************************
Info: Running Quartus Prime Fitter
	Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition
	Info: Processing started: Thu Apr 13 16:04:30 2023
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off emif_example -c emif_example
Info: qfit2_default_script.tcl version: #1
Info: Project  = emif_example
Info: Revision = emif_example
Info (16677): Loading synthesized database
Info (16734): Loading "synthesized" snapshot for partition "root_partition".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:01
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (119006): Selected device 10CX105YF780E5G for design "emif_example"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (12262): Starting Fitter periphery placement operations
Info (12290): Loading the periphery placement data.
Info (12291): Periphery placement data loaded: elapsed time is 00:00:05
Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AE10
Info (12627): Pin ~ALTERA_CLKUSR~ is reserved at location Y15
Info (18163): Pin ~ALTERA_CLKUSR~ was reserved for calibration. This pin must be assigned a 100-125 MHz clock.
Info (11685): 1 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins
	Info (11684): Differential I/O pin "pll_ref_clk" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "pll_ref_clk(n)" File: D:/intelFPGA_pro/18.1/example_design/cyclone10_ddr3/synth/cyclone10_ddr3.v Line: 8
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (12677): No exact pin location assignment(s) for 799 pins of 799 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
Info (12785): Fitter finished merging On-chip termination (OCT) logic blocks
	Info (12786): Removing unused on-chip termination logic block "emif_c10_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst" from the netlist
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Error (179000): Design requires 806 user-specified I/O pins -- too many to fit in the 284 user I/O pin locations available in the selected device
	Info (179001): Current design requires 806 user-specified I/O pins -- 806 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations
	Info (179002): Targeted device has 284 I/O pin locations available for user I/O -- 240 general-purpose I/O pins and 44 dual-purpose I/O pins
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 3 errors, 22 warnings
	Error: Peak virtual memory: 6464 megabytes
	Error: Processing ended: Thu Apr 13 16:04:42 2023
	Error: Elapsed time: 00:00:12