Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition Info: Processing started: Wed May 3 17:37:22 2023 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off ed_synth -c ed_synth --plan Info: qfit2_default_script.tcl version: #1 Info: Project = ed_synth Info: Revision = ed_synth Info (16677): Loading synthesized database Info (16734): Loading "synthesized" snapshot for partition "root_partition". Info (16734): Loading "synthesized" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:02 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (119006): Selected device 10CX105YF780E5G for design "ed_synth" Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (12262): Starting Fitter periphery placement operations Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:05 Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AE10 Info (12627): Pin ~ALTERA_CLKUSR~ is reserved at location Y15 Info (18163): Pin ~ALTERA_CLKUSR~ was reserved for calibration. This pin must be assigned a 100-125 MHz clock. Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 74 pins of 74 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Info (12785): Fitter finished merging On-chip termination (OCT) logic blocks Info (12786): Removing unused on-chip termination logic block "emif_c10_0|emif_c10_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst" from the netlist Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (16210): Plan updated with currently enabled project assignments. Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:01 Critical Warning (17951): There are 12 unused RX channels in the design. Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. Critical Warning (18655): There are 12 unused TX channels in the design. Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. Info (11178): Promoted 2 clocks (2 global) Info (13173): emif_c10_0|emif_c10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (12815 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I20 Info (13173): emif_c10_0|emif_c10_0|arch|arch_inst|pll_inst|pll_c_counters[4]~CLKENA0 (417 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I21 Info (11191): Automatically promoted 3 clocks (3 global) Info (13173): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|core_tck~CLKENA0 (3592 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I29 Info (13173): emif_c10_0_pll_ref_clk_clk~inputCLKENA0 (63 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2A_G_I22 Info (13173): emif_c10_0|emif_c10_0|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (183 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2J_G_I18 Info (176233): Starting register packing Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00. Info (332104): Reading SDC File: 'ed_synth/altera_reset_controller_181/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'ip/ed_synth/ed_synth_emif_c10_0/altera_emif_arch_nf_181/synth/ed_synth_emif_c10_0_altera_emif_arch_nf_181_kjqvysi.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: 'ip/ed_synth/ed_synth_emif_c10_0/altera_jtag_dc_streaming_181/synth/altera_avalon_st_jtag_interface.sdc' Info (332104): Reading SDC File: 'ip/ed_synth/ed_synth_emif_c10_0/altera_reset_controller_181/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'ip/ed_synth/ed_synth_emif_c10_0/altera_avalon_st_handshake_clock_crosser_181/synth/altera_avalon_st_handshake_clock_crosser.sdc' Info (332104): Reading SDC File: 'jtag_example.sdc' Info (332104): Reading SDC File: 'd:/intelfpga_pro/18.1/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc' Info (19449): Reading SDC files elapsed 00:00:00. Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].b|no_oct.obuf_bar from: oe to: o Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].b|no_oct.obuf from: oe to: o Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o Info (332098): Cell: emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 24 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 30.000 altera_reserved_tck Info (332111): 1.250 emif_c10_0_mem_mem_ck[0] Info (332111): 1.250 emif_c10_0_mem_mem_ck_n[0] Info (332111): 1.250 emif_c10_0_mem_mem_dqs[0]_IN Info (332111): 1.250 emif_c10_0_mem_mem_dqs[1]_IN Info (332111): 1.250 emif_c10_0_mem_mem_dqs[2]_IN Info (332111): 1.250 emif_c10_0_mem_mem_dqs[3]_IN Info (332111): 6.250 emif_c10_0|emif_c10_0_core_cal_master_clk Info (332111): 6.250 emif_c10_0|emif_c10_0_core_cal_slave_clk Info (332111): 5.000 emif_c10_0|emif_c10_0_core_usr_clk Info (332111): 2.500 emif_c10_0|emif_c10_0_phy_clk_0 Info (332111): 2.500 emif_c10_0|emif_c10_0_phy_clk_1 Info (332111): 5.000 emif_c10_0|emif_c10_0_phy_clk_l_0 Info (332111): 5.000 emif_c10_0|emif_c10_0_phy_clk_l_1 Info (332111): 5.000 emif_c10_0|emif_c10_0_ref_clock Info (332111): 1.250 emif_c10_0|emif_c10_0_vco_clk Info (332111): 1.250 emif_c10_0|emif_c10_0_vco_clk_1 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_0 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_1 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_2 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_3 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_4 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_5 Info (332111): 1.250 emif_c10_0|emif_c10_0_wf_clk_6 Info (176235): Finished register packing Extra Info (176218): Packed 48 registers into blocks of type Block RAM Info (16237): Starting register placement and routing for periphery-core transfers Info (16239): Register placement and routing for periphery-core transfers ending: elapsed time is 00:00:00 Info (16240): Placed 1 of 1 core register(s) within 1 routing wire(s) from the periphery Info (16240): Placed 256 of 256 core register(s) within 1 routing wire(s) from the periphery Info (16238): Starting register placement and routing for core-periphery transfers Info (16246): Register placement and routing for core-periphery transfers ending: elapsed time is 00:00:01 Info (16240): Placed 288 of 288 core register(s) within 2 routing wire(s) from the periphery Info (16240): Placed 2 of 2 core register(s) within 1 routing wire(s) from the periphery Info (16240): Placed 32 of 32 core register(s) within 1 routing wire(s) from the periphery Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info (20274): Successfully committed planned database. Info (12517): Periphery placement operations ending: elapsed time is 00:00:40 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings Info: Peak virtual memory: 8233 megabytes Info: Processing ended: Wed May 3 17:38:08 2023 Info: Elapsed time: 00:00:46