library ieee;
library altera_lnsim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use altera_lnsim.altera_lnsim_components.all;

entity PLLS is
    port (
        clk_50MHz   : in std_logic;
        reset       : in std_logic;
        clk_sel     : in std_logic;
        out_clk_sel : out std_logic
    );
end PLLS;

architecture RTL of PLLS is

    component pllintel is
        port (
            refclk            : in  std_logic                     := '0';
            rst               : in  std_logic                     := '0';
            outclk_0          : out std_logic;
            locked            : out std_logic;
            reconfig_to_pll   : in  std_logic_vector(63 downto 0) := (others => '0');
            reconfig_from_pll : out std_logic_vector(63 downto 0)
        );
    end component pllintel;

    component pllreconfig is
        generic (
            ENABLE_BYTEENABLE   : boolean := false;
            BYTEENABLE_WIDTH    : integer := 4;
            RECONFIG_ADDR_WIDTH : integer := 6;
            RECONFIG_DATA_WIDTH : integer := 32;
            reconf_width        : integer := 64;
            WAIT_FOR_LOCK       : boolean := true
        );
        port (
            mgmt_clk          : in  std_logic                     := '0';
            mgmt_reset        : in  std_logic                     := '0';
            mgmt_waitrequest  : out std_logic;
            mgmt_read         : in  std_logic                     := '0';
            mgmt_write        : in  std_logic                     := '0';
            mgmt_readdata     : out std_logic_vector(31 downto 0);
            mgmt_address      : in  std_logic_vector(5 downto 0)  := (others => '0');
            mgmt_writedata    : in  std_logic_vector(31 downto 0) := (others => '0');
            reconfig_to_pll   : out std_logic_vector(63 downto 0);
            reconfig_from_pll : in  std_logic_vector(63 downto 0) := (others => '0')
        );
    end component pllreconfig;

    signal locked       : std_logic;
    signal outclk_0     : std_logic;
    signal reconfig_to_pll   : std_logic_vector(63 downto 0);
    signal reconfig_from_pll : std_logic_vector(63 downto 0);
    signal outclk_temp  : std_logic;
    signal mgmt_waitrequest_internal : std_logic;
    signal mgmt_readdata_internal : std_logic_vector(31 downto 0);
    signal mgmt_writedata_internal : std_logic_vector(31 downto 0);
    signal mgmt_waitrequest : std_logic;
    signal mgmt_readdata : std_logic_vector(31 downto 0); -- Agregamos la señal mgmt_readdata
    signal mgmt_writedata : std_logic_vector(31 downto 0); -- Agregamos la señal mgmt_writedata

begin

    U1 : pllintel
        port map (
            refclk            => clk_50MHz,
            rst               => reset,
            outclk_0          => outclk_0,
            locked            => locked,
            reconfig_to_pll   => reconfig_to_pll,
            reconfig_from_pll => reconfig_from_pll
        );

    outclk_temp <= outclk_0 when clk_sel = '1' else clk_50MHz;

    out_clk_sel <= outclk_temp;

    U2 : pllreconfig
        generic map (
            ENABLE_BYTEENABLE   => false,
            BYTEENABLE_WIDTH    => 4,
            RECONFIG_ADDR_WIDTH => 6,
            RECONFIG_DATA_WIDTH => 32,
            reconf_width        => 64,
            WAIT_FOR_LOCK       => true
        )
        port map (
            mgmt_clk          => clk_50MHz,
            mgmt_reset        => reset,
            mgmt_waitrequest  => mgmt_waitrequest_internal,
            mgmt_read         => '0',
            mgmt_write        => '0',
            mgmt_readdata     => mgmt_readdata_internal,
            mgmt_address      => (others => '0'),
            mgmt_writedata    => mgmt_writedata_internal,
            reconfig_to_pll   => reconfig_to_pll,
            reconfig_from_pll => reconfig_from_pll
        );

    -- Conecta señales internas a señales de salida correspondientes
    mgmt_waitrequest <= mgmt_waitrequest_internal;
    mgmt_readdata <= mgmt_readdata_internal;
    mgmt_writedata <= mgmt_writedata_internal;

end RTL;