Fitter report for PCS Tue Oct 17 20:12:42 2023 Quartus Prime Version 23.2.0 Build 94 06/14/2023 SC Pro Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation 5. Fitter Partition Summary 6. Congestion Summary 7. Global & Other Fast Signals Details 8. Fitter Netlist Optimizations 9. Fitter Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2023 Intel Corporation. All rights reserved. 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Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-------------------------+-------------------------------------------+ ; Fitter Status ; Failed - Tue Oct 17 20:12:42 2023 ; ; Quartus Prime Version ; 23.2.0 Build 94 06/14/2023 SC Pro Edition ; ; Revision Name ; PCS ; ; Top-level Entity Name ; top ; ; Family ; Cyclone 10 GX ; ; Device ; 10CX150YF780E5G ; ; Timing Models ; Final ; ; Power Models ; Final ; ; Device Status ; Final ; ; Total registers ; 57 ; ; Total pins ; 10 / 340 ( 3 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 0 / 9,728,000 ( 0 % ) ; ; Total RAM Blocks ; 0 / 475 ( 0 % ) ; ; Total DSP Blocks ; 0 / 156 ( 0 % ) ; ; Total HSSI RX channels ; 1 / 12 ( 8 % ) ; ; Total HSSI TX channels ; 1 / 12 ( 8 % ) ; ; Total PLLs ; 4 / 30 ( 13 % ) ; +-------------------------+-------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Settings ; +------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ ; Device ; 10CX150YF780E5G ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 100 ; ; ; Optimization Mode ; Superior Performance ; Balanced ; ; Allow RAM Retiming ; On ; Off ; ; Allow DSP Retiming ; On ; Off ; ; Router Timing Optimization Level ; MAXIMUM ; Normal ; ; Advanced Physical Synthesis ; On ; Off ; ; Fitter Effort ; Standard Fit ; Auto Fit ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Design Assistant include IP blocks ; Off ; Off ; ; High fanout net threshold for RAM inference ; 15 ; 15 ; ; Design Assistant limit on reported violations per rule ; 5000 ; 5000 ; ; Perform Simultaneous Multicorner Analysis ; On ; On ; ; Allow Register Merging ; On ; On ; ; Allow Register Duplication ; On ; On ; ; Allow Register Retiming ; On ; On ; ; Perform Clocking Topology Analysis During Routing ; Off ; Off ; ; Placement Effort Multiplier ; 1.0 ; 1.0 ; ; Enable unused RX clock workaround ; Off ; Off ; ; Preserve unused RX/TX channels ; Off ; Off ; ; Ignore the power supply of HSSI column when preserving unused RX/TX channels ; On ; On ; ; Automatically reserve CLKUSR pin for calibration purposes ; On ; On ; ; Configuration clock source ; INIT_INTOSC ; INIT_INTOSC ; ; Optimize Hold Timing ; All Paths ; All Paths ; ; Optimize Multi-Corner Timing ; On ; On ; ; Auto RAM to MLAB Conversion ; On ; On ; ; Report Packed DSP Register Names ; On ; On ; ; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; ; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; ; Programmable Power Technology Optimization ; Automatic ; Automatic ; ; Programmable Power Maximum High-Speed Fraction of Used LAB Tiles ; 1.0 ; 1.0 ; ; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; ; Optimize Timing ; Normal compilation ; Normal compilation ; ; Optimize IOC Register Placement for Timing ; Normal ; Normal ; ; Final Placement Optimizations ; Automatically ; Automatically ; ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; ; Fitter Initial Placement Seed ; 1 ; 1 ; ; Weak Pull-Up Resistor ; Off ; Off ; ; Enable Bus-Hold Circuitry ; Off ; Off ; ; Auto Packed Registers ; Auto ; Auto ; ; Auto Delay Chains ; On ; On ; ; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; ; Treat Bidirectional Pin as Output Pin ; Off ; Off ; ; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; ; Auto Register Duplication ; Auto ; Auto ; ; Auto Global Clock ; On ; On ; ; Auto Global Register Control Signals ; On ; On ; ; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; ; Synchronizer Identification ; Auto ; Auto ; ; Optimize Design for Metastability ; On ; On ; ; Analyze Auto-Detected Synchronizers for Metastability ; Off ; Off ; ; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; ; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ; Physical Placement Effort ; Normal ; Normal ; ; Number of Example Nodes Reported in Fitter Messages ; 50 ; 50 ; ; Enable Intermediate Fitter Snapshots ; Off ; Off ; ; The Maximum physical M20Ks reported in the physical RAM report ; 500 ; 500 ; +------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 12 ; ; Maximum allowed ; 12 ; +----------------------------+--------+ +--------------------------------------------------------------------------------------------+ ; Fitter Partition Summary ; +----------------+----------------+---------+--------------+-------+-------------------------+ ; Partition Name ; Hierarchy Path ; Type ; Preservation ; Empty ; Partition Database File ; +----------------+----------------+---------+--------------+-------+-------------------------+ ; root_partition ; | ; Default ; ; ; ; ; auto_fab_0 ; auto_fab_0 ; Default ; ; ; ; +----------------+----------------+---------+--------------+-------+-------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Congestion Summary ; +-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+-------------------------------------------------------+----------------------+ ; Congestion Type ; Link Source ; Source Location ; Link Destination ; Destination Location ; +-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+-------------------------------------------------------+----------------------+ ; Direct (Failing Signal) ; m_iopll_refclk|iopll_0|altera_iopll_i|c10gx_pll|outclk[0]~CLKENA0~CLKMUX_GROUP3 ; -- ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; ; Direct ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0~CLKMUX_GROUP2 ; CLKMUX_GROUP_1D_P2_I9 ; m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst ; FPLLREFCLKSELECT_1DB ; +-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+-------------------------------------------------------+----------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Global & Other Fast Signals Details ; +----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Name ; m_inbuf_644M_clk~FITTER_INSERTED ; ; -- Source Type ; HSSI REFCLK DIVIDER ; ; -- Source Location ; HSSIREFCLKDIVIDER_1DT ; ; -- Fan-Out ; 1 ; ; -- Promotion Type ; Required Promotion ; ; -- Global Buffer ; m_inbuf_644M_clk~FITTER_INSERTEDCLKENA0 ; ; -- Global Buffer Location ; Unassigned ; ; -- Global Signal Type ; Global (preferred), Regional, or Periphery ; ; ; ; ; Name ; m_iopll_refclk|iopll_0|altera_iopll_i|c10gx_pll|outclk[0] ; ; -- Source Type ; I/O PLL ; ; -- Source Location ; Unassigned ; ; -- Fan-Out ; 1 ; ; -- Promotion Type ; Required Promotion ; ; -- Global Buffer ; m_iopll_refclk|iopll_0|altera_iopll_i|c10gx_pll|outclk[0]~CLKENA0 ; ; -- Global Buffer Location ; Unassigned ; ; -- Global Signal Type ; Global (preferred), Regional, or Periphery ; ; ; ; ; Name ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out ; ; -- Source Type ; HSSI RX PLD PCS INTERFACE ; ; -- Source Location ; Unassigned ; ; -- Fan-Out ; 1 ; ; -- Promotion Type ; Required Promotion ; ; -- Global Buffer ; m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 ; ; -- Global Buffer Location ; Unassigned ; ; -- Global Signal Type ; Periphery (preferred), Regional, or Global ; ; ; ; ; Name ; OSC_50m ; ; -- Source Type ; I/O pad ; ; -- Source Location ; PIN_A24 ; ; -- Fan-Out ; 38 ; ; -- Promotion Type ; Automatic Promotion ; ; -- Global Buffer ; OSC_50m~inputCLKENA0 ; ; -- Global Buffer Location ; Unassigned ; ; -- Global Signal Type ; Global (preferred) or not promoted ; ; -- Constrained Region ; Global Clock Region ; ; -- Constrained Region Bounding Box ; (0, 0) to (102, 115) ; ; ; ; ; Name ; ~ALTERA_CLKUSR~ ; ; -- Source Type ; I/O pad ; ; -- Source Location ; PIN_Y15 ; ; -- Fan-Out ; 1 ; ; -- Promotion Type ; Automatic Promotion ; ; -- Global Buffer ; ~ALTERA_CLKUSR~~ibufCLKENA0 ; ; -- Global Buffer Location ; Unassigned ; ; -- Global Signal Type ; Global (preferred) or not promoted ; ; -- Constrained Region ; Global Clock Region ; ; -- Constrained Region Bounding Box ; (0, 0) to (102, 115) ; +----------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Netlist Optimizations ; +-------------------------------------------------------------------------------------+---------+-----------+------------------------+-----------+------------------+------------------+ ; Node ; Action ; Operation ; Reason ; Node Port ; Destination Node ; Destination Port ; +-------------------------------------------------------------------------------------+---------+-----------+------------------------+-----------+------------------+------------------+ ; auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|a10xcvrfabric|ALTERA_INSERTED_INTOSC_FOR_TRS ; Deleted ; Placement ; PLL Usage Optimization ; ; ; ; +-------------------------------------------------------------------------------------+---------+-----------+------------------------+-----------+------------------+------------------+ Note: Retiming optimizations are not included in this table. +-----------------+ ; Fitter Messages ; +-----------------+ Can't read Quartus Prime message file /home/gp/rtl/hft/ethernet/phy/tcl/qdb/_compiler/PCS/_flat/23.2.0/legacy/1/PCS.fit.plan.header.qmsgdb. Make sure the file exists and is up to date, and you have permission to read and write the file. Info (16677): Loading synthesized database. Info (16734): Loading "synthesized" snapshot for partition "root_partition". Info (16734): Loading "synthesized" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:02. Info (16303): Superior Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time Info (119006): Selected device 10CX150YF780E5G for design "PCS" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 100 degrees C Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (12262): Starting Fitter periphery placement operations Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:03 Info (12627): Pin ~ALTERA_DATA0~ is reserved at location AE10 Info (12627): Pin ~ALTERA_CLKUSR~ is reserved at location Y15 Info (18163): Pin ~ALTERA_CLKUSR~ was reserved for calibration. This pin must be assigned a 100-125 MHz clock. Info (16210): Plan updated with currently enabled project assignments. Error (14996): The Fitter failed to find a legal placement for all periphery components Info (14987): The following components had the most difficulty being legally placed: Info (175029): auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (50%) Info (175029): CMU_FPLL_MUX_CLUSTER m_phase_align|xcvr_fpll_a10_0|fpll_inst~CMU_FPLL_MUX_CLUSTER1 (50%) Error (14986): After placing as many components as possible, the following errors remain: Error (175001): The Fitter cannot place 1 auto-promoted clock driver, which is within IOPLL Intel FPGA IP iopll_altera_iopll_1931_qqycjhq. Info (14596): Information about the failing component(s): Info (175028): The auto-promoted clock driver name(s): m_iopll_refclk|iopll_0|altera_iopll_i|c10gx_pll|outclk[0]~CLKENA0 Error (16234): No legal location could be found out of 156 considered location(s). Reasons why each location could not be used are summarized below: Error (15123): The following auto-promoted clock driver locations cannot route to all the required CMU_FPLL_REFCLK_SELECTs Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175029): 120 locations affected Info (175029): CLKCTRL_1C_P3_I8 Info (175029): CLKCTRL_1C_P3_I9 Info (175029): CLKCTRL_1C_P3_I10 Info (175029): CLKCTRL_1C_P3_I11 Info (175029): CLKCTRL_1C_P3_I4 Info (175029): CLKCTRL_1C_P3_I5 Info (175029): CLKCTRL_1C_P3_I6 Info (175029): CLKCTRL_1C_P3_I7 Info (175029): CLKCTRL_1C_P3_I0 Info (175029): CLKCTRL_1C_P3_I1 Info (175029): CLKCTRL_1C_P3_I2 Info (175029): CLKCTRL_1C_P3_I3 Info (175029): and 108 more locations not displayed Error (11238): The following 2 clock driver locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters. Error (11239): Location CLKCTRL_1D_P2_I9 is already occupied by m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0. Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Error (11239): Location CLKCTRL_1D_G_I4 is already occupied by m_inbuf_644M_clk~FITTER_INSERTEDCLKENA0. Info (175013): The auto-promoted clock driver is constrained to the region (0, 32) to (0, 50) due to related logic Info (175015): The I/O pad GXB1D_644M is constrained to the location PIN_N24 due to: User Location Constraints (PIN_N24) File: /home/gp/rtl/hft/ethernet/phy/cy10gx/top.v Line: 19 Info (14709): The constrained I/O pad contains a HSSI_REFCLK_DIVIDER, which drives this auto-promoted clock driver Error (177034): Row clock network in the region bounded by (0,41) and (20,41) is congested due to limited connectivity Info (175030): Unroutable signal: Info (175026): Source: auto-promoted clock driver m_iopll_refclk|iopll_0|altera_iopll_i|c10gx_pll|outclk[0]~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (18497): 17 signals are using the routing resources that the unroutable signal can access (direct congestion): Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Info (175031): Competing signal: Info (175026): Source: auto-promoted clock driver m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (0, 5) to (102, 104) due to related logic Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Error (175006): There is no routing connectivity between the auto-promoted clock driver and destination CMU_FPLL_REFCLK_SELECT Info (175027): Destination: CMU_FPLL_REFCLK_SELECT m_phase_align|xcvr_fpll_a10_0|fpll_refclk_select_inst Info (175013): The CMU_FPLL_REFCLK_SELECT is constrained to the region (0, 7) to (0, 92) due to related logic Error (175022): The auto-promoted clock driver could not be placed in any location to satisfy its connectivity requirements Info (175021): The destination CMU_FPLL_REFCLK_SELECT was placed in location FPLLREFCLKSELECT_1DB Info (175029): 36 locations affected Info (175029): CLKCTRL_1C_NOT_USED_I0 Info (175029): CLKCTRL_1C_NOT_USED_I1 Info (175029): CLKCTRL_1C_NOT_USED_I2 Info (175029): CLKCTRL_1D_NOT_USED_I0 Info (175029): CLKCTRL_1D_NOT_USED_I1 Info (175029): CLKCTRL_1D_NOT_USED_I2 Info (175029): CLKCTRL_1E_NOT_USED_I0 Info (175029): CLKCTRL_1E_NOT_USED_I1 Info (175029): CLKCTRL_1E_NOT_USED_I2 Info (175029): CLKCTRL_1F_NOT_USED_I0 Info (175029): CLKCTRL_1F_NOT_USED_I1 Info (175029): CLKCTRL_1F_NOT_USED_I2 Info (175029): and 24 more locations not displayed Error (175001): The Fitter cannot place 1 CMU_FPLL_MUX_CLUSTER, which is within fPLL Intel Arria 10/Cyclone 10 FPGA IP altera_xcvr_fpll_a10. Info (14596): Information about the failing component(s): Info (175028): The CMU_FPLL_MUX_CLUSTER name(s): m_sfp1_tx_fpll|xcvr_fpll_a10_0|fpll_inst~CMU_FPLL_MUX_CLUSTER0 Error (16234): No legal location could be found out of 3 considered location(s). Reasons why each location could not be used are summarized below: Info (175013): The CMU_FPLL is constrained to the region (0, 7) to (0, 38) due to related logic Info (175015): The I/O pad GXB1D_644M is constrained to the location PIN_N24 due to: User Location Constraints (PIN_N24) File: /home/gp/rtl/hft/ethernet/phy/cy10gx/top.v Line: 19 Info (14709): The constrained I/O pad contains a HSSI_REFCLK_DIVIDER, which drives a HSSI_DUPLEX_CHANNEL_CLUSTER, which is driven by a CMU_FPLL, which is contained within this CMU_FPLL_MUX_CLUSTER Error (175006): There is no routing connectivity between the CMU_FPLL_MUX_CLUSTER and destination HSSI_PMA_TX_CGB Info (175027): Destination: HSSI_PMA_TX_CGB m_sfp1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb Info (175013): The HSSI_PMA_TX_CGB is constrained to the region (0, 7) to (0, 45) due to related logic Info (175015): The I/O pad GXB1D_644M is constrained to the location PIN_N24 due to: User Location Constraints (PIN_N24) File: /home/gp/rtl/hft/ethernet/phy/cy10gx/top.v Line: 19 Info (14709): The constrained I/O pad contains a HSSI_REFCLK_DIVIDER, which drives a HSSI_RX_CHANNEL_CLUSTER, which is driven by this HSSI_PMA_TX_CGB Error (175022): The CMU_FPLL_MUX_CLUSTER could not be placed in any location to satisfy its connectivity requirements Info (175021): The destination HSSI_PMA_TX_CGB was placed in location HSSIPMATXCGB_1D0 Info (175029): 2 locations affected Info (175029): CMU_FPLL_MUX_CLUSTER containing FPLL_1CB Info (175029): CMU_FPLL_MUX_CLUSTER containing FPLL_1CT Error (175007): Could not find uncongested path between source CMU_FPLL and the CMU_FPLL_MUX_CLUSTER Info (175026): Source: CMU_FPLL m_phase_align|xcvr_fpll_a10_0|fpll_inst Info (175013): The CMU_FPLL is constrained to the region (0, 7) to (0, 92) due to related logic Info (175021): The source CMU_FPLL was placed in location FPLL_1DB Error (175022): The CMU_FPLL_MUX_CLUSTER could not be placed in any location to satisfy its connectivity requirements Info (175029): 1 location affected Info (175029): CMU_FPLL_MUX_CLUSTER containing FPLL_1DT Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:04:26 Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info (20274): Successfully committed planned database. Error: ERROR: An error occurred during automatic periphery placement Error: Quartus Prime Fitter was unsuccessful. 18 errors, 0 warnings Error: Peak virtual memory: 2564 megabytes Error: Processing ended: Tue Oct 17 20:12:43 2023 Error: Elapsed time: 00:04:37 Error: System process ID: 25579