// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "03/04/2024 16:56:04"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    DECODEUR_3_x_8
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module DECODEUR_3_x_8_vlg_sample_tst(
	input,
	sampler_tx
);
input [2:0] input;
output sampler_tx;

reg sample;
time current_time;
always @(input)
                                                                                
begin                                                 
 if ($realtime > 0)                                   
 begin                                                
	if ($realtime == 0 || $realtime != current_time)  
	begin									          
		if (sample === 1'bx)                          
			sample = 0;                               
		else                                          
			sample = ~sample;                         
	end										          
	current_time = $realtime;					      
 end                                                  
end                                                   

assign sampler_tx = sample;
endmodule

module DECODEUR_3_x_8_vlg_check_tst (
	output_0,
	output_1,
	output_2,
	output_3,
	output_4,
	output_5,
	output_6,
	output_7,
	sampler_rx
);
input  output_0;
input  output_1;
input  output_2;
input  output_3;
input  output_4;
input  output_5;
input  output_6;
input  output_7;
input sampler_rx;

reg  output_0_expected;
reg  output_1_expected;
reg  output_2_expected;
reg  output_3_expected;
reg  output_4_expected;
reg  output_5_expected;
reg  output_6_expected;
reg  output_7_expected;

reg  output_0_prev;
reg  output_1_prev;
reg  output_2_prev;
reg  output_3_prev;
reg  output_4_prev;
reg  output_5_prev;
reg  output_6_prev;
reg  output_7_prev;

reg  output_0_expected_prev;
reg  output_1_expected_prev;
reg  output_2_expected_prev;
reg  output_3_expected_prev;
reg  output_4_expected_prev;
reg  output_5_expected_prev;
reg  output_6_expected_prev;
reg  output_7_expected_prev;

reg  last_output_0_exp;
reg  last_output_1_exp;
reg  last_output_2_exp;
reg  last_output_3_exp;
reg  last_output_4_exp;
reg  last_output_5_exp;
reg  last_output_6_exp;
reg  last_output_7_exp;

reg trigger;

integer i;
integer nummismatches;

reg [1:8] on_first_change ;


initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 8'b1;
end

// update real /o prevs

always @(trigger)
begin
	output_0_prev = output_0;
	output_1_prev = output_1;
	output_2_prev = output_2;
	output_3_prev = output_3;
	output_4_prev = output_4;
	output_5_prev = output_5;
	output_6_prev = output_6;
	output_7_prev = output_7;
end

// update expected /o prevs

always @(trigger)
begin
	output_0_expected_prev = output_0_expected;
	output_1_expected_prev = output_1_expected;
	output_2_expected_prev = output_2_expected;
	output_3_expected_prev = output_3_expected;
	output_4_expected_prev = output_4_expected;
	output_5_expected_prev = output_5_expected;
	output_6_expected_prev = output_6_expected;
	output_7_expected_prev = output_7_expected;
end



// expected output_0
initial
begin
	output_0_expected = 1'bX;
end 

// expected output_1
initial
begin
	output_1_expected = 1'bX;
end 

// expected output_2
initial
begin
	output_2_expected = 1'bX;
end 

// expected output_3
initial
begin
	output_3_expected = 1'bX;
end 

// expected output_4
initial
begin
	output_4_expected = 1'bX;
end 

// expected output_5
initial
begin
	output_5_expected = 1'bX;
end 

// expected output_6
initial
begin
	output_6_expected = 1'bX;
end 

// expected output_7
initial
begin
	output_7_expected = 1'bX;
end 
// generate trigger
always @(output_0_expected or output_0 or output_1_expected or output_1 or output_2_expected or output_2 or output_3_expected or output_3 or output_4_expected or output_4 or output_5_expected or output_5 or output_6_expected or output_6 or output_7_expected or output_7)
begin
	trigger <= ~trigger;
end

always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
	$display("Scanning pattern %d @time = %t",i,$realtime );
	i = i + 1;
	$display("| expected output_0 = %b | expected output_1 = %b | expected output_2 = %b | expected output_3 = %b | expected output_4 = %b | expected output_5 = %b | expected output_6 = %b | expected output_7 = %b | ",output_0_expected_prev,output_1_expected_prev,output_2_expected_prev,output_3_expected_prev,output_4_expected_prev,output_5_expected_prev,output_6_expected_prev,output_7_expected_prev);
	$display("| real output_0 = %b | real output_1 = %b | real output_2 = %b | real output_3 = %b | real output_4 = %b | real output_5 = %b | real output_6 = %b | real output_7 = %b | ",output_0_prev,output_1_prev,output_2_prev,output_3_prev,output_4_prev,output_5_prev,output_6_prev,output_7_prev);
`endif
	if (
		( output_0_expected_prev !== 1'bx ) && ( output_0_prev !== output_0_expected_prev )
		&& ((output_0_expected_prev !== last_output_0_exp) ||
			on_first_change[1])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_0 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_0_expected_prev);
		$display ("     Real value = %b", output_0_prev);
		nummismatches = nummismatches + 1;
		on_first_change[1] = 1'b0;
		last_output_0_exp = output_0_expected_prev;
	end
	if (
		( output_1_expected_prev !== 1'bx ) && ( output_1_prev !== output_1_expected_prev )
		&& ((output_1_expected_prev !== last_output_1_exp) ||
			on_first_change[2])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_1 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_1_expected_prev);
		$display ("     Real value = %b", output_1_prev);
		nummismatches = nummismatches + 1;
		on_first_change[2] = 1'b0;
		last_output_1_exp = output_1_expected_prev;
	end
	if (
		( output_2_expected_prev !== 1'bx ) && ( output_2_prev !== output_2_expected_prev )
		&& ((output_2_expected_prev !== last_output_2_exp) ||
			on_first_change[3])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_2 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_2_expected_prev);
		$display ("     Real value = %b", output_2_prev);
		nummismatches = nummismatches + 1;
		on_first_change[3] = 1'b0;
		last_output_2_exp = output_2_expected_prev;
	end
	if (
		( output_3_expected_prev !== 1'bx ) && ( output_3_prev !== output_3_expected_prev )
		&& ((output_3_expected_prev !== last_output_3_exp) ||
			on_first_change[4])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_3 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_3_expected_prev);
		$display ("     Real value = %b", output_3_prev);
		nummismatches = nummismatches + 1;
		on_first_change[4] = 1'b0;
		last_output_3_exp = output_3_expected_prev;
	end
	if (
		( output_4_expected_prev !== 1'bx ) && ( output_4_prev !== output_4_expected_prev )
		&& ((output_4_expected_prev !== last_output_4_exp) ||
			on_first_change[5])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_4 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_4_expected_prev);
		$display ("     Real value = %b", output_4_prev);
		nummismatches = nummismatches + 1;
		on_first_change[5] = 1'b0;
		last_output_4_exp = output_4_expected_prev;
	end
	if (
		( output_5_expected_prev !== 1'bx ) && ( output_5_prev !== output_5_expected_prev )
		&& ((output_5_expected_prev !== last_output_5_exp) ||
			on_first_change[6])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_5 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_5_expected_prev);
		$display ("     Real value = %b", output_5_prev);
		nummismatches = nummismatches + 1;
		on_first_change[6] = 1'b0;
		last_output_5_exp = output_5_expected_prev;
	end
	if (
		( output_6_expected_prev !== 1'bx ) && ( output_6_prev !== output_6_expected_prev )
		&& ((output_6_expected_prev !== last_output_6_exp) ||
			on_first_change[7])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_6 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_6_expected_prev);
		$display ("     Real value = %b", output_6_prev);
		nummismatches = nummismatches + 1;
		on_first_change[7] = 1'b0;
		last_output_6_exp = output_6_expected_prev;
	end
	if (
		( output_7_expected_prev !== 1'bx ) && ( output_7_prev !== output_7_expected_prev )
		&& ((output_7_expected_prev !== last_output_7_exp) ||
			on_first_change[8])
	)
	begin
		$display ("ERROR! Vector Mismatch for output port output_7 :: @time = %t",  $realtime);
		$display ("     Expected value = %b", output_7_expected_prev);
		$display ("     Real value = %b", output_7_prev);
		nummismatches = nummismatches + 1;
		on_first_change[8] = 1'b0;
		last_output_7_exp = output_7_expected_prev;
	end

	trigger <= ~trigger;
end
initial 

begin 
$timeformat(-12,3," ps",6);
#1000000;
if (nummismatches > 0)
	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
	$display ("Simulation passed !");
$finish;
end 
endmodule

module DECODEUR_3_x_8_vlg_vec_tst();
// constants                                           
// general purpose registers
reg [2:0] input;
// wires                                               
wire output_0;
wire output_1;
wire output_2;
wire output_3;
wire output_4;
wire output_5;
wire output_6;
wire output_7;

wire sampler;                             

// assign statements (if any)                          
DECODEUR_3_x_8 i1 (
// port map - connection between master ports and signals/registers   
	.\input (input),
	.output_0(output_0),
	.output_1(output_1),
	.output_2(output_2),
	.output_3(output_3),
	.output_4(output_4),
	.output_5(output_5),
	.output_6(output_6),
	.output_7(output_7)
);
// \input [ 2 ]
initial
begin
	input[2] = 1'b0;
end 
// \input [ 1 ]
initial
begin
	input[1] = 1'b0;
end 
// \input [ 0 ]
initial
begin
	input[0] = 1'b0;
end 

DECODEUR_3_x_8_vlg_sample_tst tb_sample (
	.input(input),
	.sampler_tx(sampler)
);

DECODEUR_3_x_8_vlg_check_tst tb_out(
	.output_0(output_0),
	.output_1(output_1),
	.output_2(output_2),
	.output_3(output_3),
	.output_4(output_4),
	.output_5(output_5),
	.output_6(output_6),
	.output_7(output_7),
	.sampler_rx(sampler)
);
endmodule