// Copyright (C) 2024  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition"

// DATE "11/07/2024 11:18:43"

// 
// Device: Altera EPM1270F256C5 Package FBGA256
// 

// 
// This Verilog file should be used for Questa Intel FPGA (Verilog) only
// 

`timescale 1 ps/ 1 ps

module light (
	A,
	B,
	C);
input 	A;
input 	B;
output 	C;

// Design Ports Information


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \A~combout ;
wire \B~combout ;
wire \C~0_combout ;


// Location: PIN_M9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \A~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\A~combout ),
	.padio(A));
// synopsys translate_off
defparam \A~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_R14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \B~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\B~combout ),
	.padio(B));
// synopsys translate_off
defparam \B~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X14_Y1_N7
maxii_lcell \C~0 (
// Equation(s):
// \C~0_combout  = (((\A~combout  & \B~combout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(\A~combout ),
	.datad(\B~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\C~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \C~0 .lut_mask = "f000";
defparam \C~0 .operation_mode = "normal";
defparam \C~0 .output_mode = "comb_only";
defparam \C~0 .register_cascade_mode = "off";
defparam \C~0 .sum_lutc_input = "datac";
defparam \C~0 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_T13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \C~I (
	.datain(\C~0_combout ),
	.oe(vcc),
	.combout(),
	.padio(C));
// synopsys translate_off
defparam \C~I .operation_mode = "output";
// synopsys translate_on

endmodule