POST Started: Mon Apr 19 11:54:18 2021
Time	Code
00:00.000	0x31	Memory installed
00:01.330	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
00:01.330	0xA3	Setup minimum path between SBSP and other sockets
00:01.330	0xA3	Setup minimum path between SBSP and other sockets
00:01.330	0xA7	Topology discovery and route calculation
00:01.330	0xA9	Program final IO SAD setting
00:01.380	0xAA	Protocol layer and other uncore settings
00:01.380	0xAB	Transition links to full speed operation
00:01.380	0xAF	KTI initialization done
00:01.390	0x32	CPU PEIM (CPU Init)
00:01.410	0xB0	Detect DIMM population
00:01.750	0xB0	Detect DIMM population
00:01.750	0xB0	Detect DIMM population
00:01.790	0xB0	Detect DIMM population
00:01.820	0xB0	Detect DIMM population
00:01.860	0xB0	Detect DIMM population
00:01.890	0xB0	Detect DIMM population
00:01.900	0xB0	Detect DIMM population
00:01.930	0xB0	Detect DIMM population
00:01.970	0xB0	Detect DIMM population
00:02.000	0xB0	Detect DIMM population
00:02.040	0xB0	Detect DIMM population
00:02.070	0xB0	Detect DIMM population
00:02.110	0xB0	Detect DIMM population
00:02.140	0xB0	Detect DIMM population
00:02.200	0xB1	Set DDR4 frequency
00:02.200	0xB1	Set DDR4 frequency
00:02.200	0xAF	KTI initialization done
00:08.770	0x03	CRAM initialization begin
00:08.830	0x04	PEI Cache When Disabled
00:08.830	0x05	SEC Core At Power On Begin
00:08.830	0x06	Early CPU initialization during SEC Phase
00:08.840	0x11	CPU PEIM
00:08.840	0x32	CPU PEIM (CPU Init)
00:09.860	0x15	Platform Type Init
00:09.910	0x19	Platform PEIM Init
00:10.200	0x31	Memory installed
00:11.470	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
00:11.470	0xA3	Setup minimum path between SBSP and other sockets
00:11.470	0xA3	Setup minimum path between SBSP and other sockets
00:11.470	0xA7	Topology discovery and route calculation
00:11.470	0xA9	Program final IO SAD setting
00:11.530	0xA7	Topology discovery and route calculation
00:11.530	0xA7	Topology discovery and route calculation
00:11.530	0xA7	Topology discovery and route calculation
00:11.530	0xA8	Program final route
00:11.530	0xA9	Program final IO SAD setting
00:11.530	0xAA	Protocol layer and other uncore settings
00:11.530	0xAE	Coherency settings
00:11.530	0xAF	KTI initialization done
00:11.550	0xE1	S3 Resume PEIM (S3 boot script)
00:11.550	0xE4	undefined
00:12.380	0xE3	S3 Resume PEIM (S3 OS wake)
00:12.380	0xE5	CPU mismatch error
00:12.380	0x32	CPU PEIM (CPU Init)
00:12.390	0xB0	Detect DIMM population
00:12.720	0xB0	Detect DIMM population
00:12.720	0xB0	Detect DIMM population
00:12.760	0xB0	Detect DIMM population
00:12.790	0xB0	Detect DIMM population
00:12.830	0xB0	Detect DIMM population
00:12.860	0xB0	Detect DIMM population
00:12.860	0xB0	Detect DIMM population
00:12.900	0xB0	Detect DIMM population
00:12.930	0xB0	Detect DIMM population
00:12.970	0xB0	Detect DIMM population
00:13.000	0xB0	Detect DIMM population
00:13.040	0xB0	Detect DIMM population
00:13.070	0xB0	Detect DIMM population
00:13.110	0xB0	Detect DIMM population
00:13.160	0xB1	Set DDR4 frequency
00:13.170	0xB1	Set DDR4 frequency
00:13.170	0xB1	Set DDR4 frequency
00:13.200	0xB1	Set DDR4 frequency
00:13.200	0xB4	Evaluate RAS modes and save rank information
00:13.200	0xB2	Gather remaining SPD data
00:13.210	0xB3	Program registers on the memory controller level
00:13.210	0xB3	Program registers on the memory controller level
00:13.210	0xB6	Perform the JEDEC defined initialization sequence
00:13.210	0xB6	Perform the JEDEC defined initialization sequence
00:13.220	0xB6	Perform the JEDEC defined initialization sequence
00:13.220	0xB6	Perform the JEDEC defined initialization sequence
00:13.220	0xB7	Train DDR4 ranks
00:13.240	0xB7	Train DDR4 ranks
00:13.340	0xB6	Perform the JEDEC defined initialization sequence
00:13.340	0xB7	Train DDR4 ranks
00:13.350	0xB6	Perform the JEDEC defined initialization sequence
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.350	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.440	0xB7	Train DDR4 ranks
00:13.450	0xB7	Train DDR4 ranks
00:13.450	0xB7	Train DDR4 ranks
00:13.450	0xB7	Train DDR4 ranks
00:13.450	0xB7	Train DDR4 ranks
00:13.450	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.460	0xB7	Train DDR4 ranks
00:13.470	0xB7	Train DDR4 ranks
00:13.470	0xB7	Train DDR4 ranks
00:13.470	0xBD	undefined
00:13.470	0xBD	undefined
00:13.480	0xB7	Train DDR4 ranks
00:13.480	0xBD	undefined
00:13.480	0xBD	undefined
00:13.490	0xB7	Train DDR4 ranks
00:13.490	0xB7	Train DDR4 ranks
00:13.490	0xBD	undefined
00:13.510	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xB7	Train DDR4 ranks
00:13.520	0xBD	undefined
00:13.530	0xBD	undefined
00:13.530	0xBD	undefined
00:13.540	0xBD	undefined
00:13.550	0xBD	undefined
00:13.550	0xBD	undefined
00:13.560	0xB7	Train DDR4 ranks
00:13.560	0xBD	undefined
00:13.560	0xBD	undefined
00:13.570	0xBD	undefined
00:13.580	0xBD	undefined
00:13.580	0xBD	undefined
00:13.590	0xBD	undefined
00:13.590	0xB7	Train DDR4 ranks
00:13.590	0xBD	undefined
00:13.600	0xBD	undefined
00:13.610	0xBD	undefined
00:13.620	0xBD	undefined
00:13.620	0xBD	undefined
00:13.630	0xBD	undefined
00:13.630	0xBD	undefined
00:13.640	0xBD	undefined
00:13.640	0xBD	undefined
00:13.650	0xBD	undefined
00:13.660	0xBD	undefined
00:13.660	0xBD	undefined
00:13.670	0xBD	undefined
00:13.680	0xBD	undefined
00:13.680	0xBD	undefined
00:13.690	0xBD	undefined
00:13.690	0xBD	undefined
00:13.700	0xBD	undefined
00:13.700	0xBD	undefined
00:13.710	0xBD	undefined
00:13.710	0xBD	undefined
00:13.720	0xBD	undefined
00:13.720	0xBD	undefined
00:13.730	0xBD	undefined
00:13.730	0xBD	undefined
00:13.730	0xBD	undefined
00:13.740	0xBD	undefined
00:13.740	0xBD	undefined
00:13.750	0xBD	undefined
00:13.750	0xBD	undefined
00:13.750	0xB7	Train DDR4 ranks
00:13.750	0xBD	undefined
00:13.760	0xBD	undefined
00:13.770	0xBD	undefined
00:13.780	0xBD	undefined
00:13.780	0xBD	undefined
00:13.790	0xBD	undefined
00:13.790	0xBD	undefined
00:13.800	0xBD	undefined
00:13.810	0xBD	undefined
00:13.820	0xBD	undefined
00:13.820	0xBD	undefined
00:13.830	0xBD	undefined
00:13.840	0xBD	undefined
00:13.850	0xBD	undefined
00:13.850	0xBD	undefined
00:13.860	0xBD	undefined
00:13.870	0xBD	undefined
00:13.880	0xBD	undefined
00:13.880	0xB7	Train DDR4 ranks
00:13.880	0xB7	Train DDR4 ranks
00:13.880	0xB7	Train DDR4 ranks
00:13.880	0xBD	undefined
00:13.890	0xBD	undefined
00:13.890	0xBD	undefined
00:13.900	0xB7	Train DDR4 ranks
00:13.900	0xBD	undefined
00:13.900	0xBD	undefined
00:13.910	0xBD	undefined
00:13.920	0xBD	undefined
00:13.940	0xB7	Train DDR4 ranks
00:13.940	0xBD	undefined
00:13.940	0xBD	undefined
00:13.950	0xBD	undefined
00:13.950	0xBD	undefined
00:13.960	0xB7	Train DDR4 ranks
00:13.960	0xBD	undefined
00:13.970	0xBD	undefined
00:14.070	0xBD	undefined
00:14.080	0xBD	undefined
00:14.080	0xBD	undefined
00:14.090	0xBD	undefined
00:14.100	0xBD	undefined
00:14.110	0xBD	undefined
00:14.110	0xBD	undefined
00:14.120	0xBD	undefined
00:14.120	0xBD	undefined
00:14.130	0xBD	undefined
00:14.130	0xBD	undefined
00:14.130	0xBD	undefined
00:14.140	0xBD	undefined
00:14.140	0xBD	undefined
00:14.140	0xBD	undefined
00:14.140	0xBD	undefined
00:14.140	0xBD	undefined
00:14.140	0xBD	undefined
00:14.150	0xBD	undefined
00:14.150	0xBD	undefined
00:14.160	0xBD	undefined
00:14.160	0xBD	undefined
00:14.160	0xBD	undefined
00:14.160	0xBD	undefined
00:14.160	0xBD	undefined
00:14.170	0xB7	Train DDR4 ranks
00:14.170	0xB7	Train DDR4 ranks
00:14.170	0xB7	Train DDR4 ranks
00:14.170	0xBD	undefined
00:14.170	0xBD	undefined
00:14.170	0xBD	undefined
00:14.180	0xB7	Train DDR4 ranks
00:14.190	0xB9	Hardware memory test and init
00:14.190	0xB1	Set DDR4 frequency
00:14.190	0xB9	Hardware memory test and init
00:16.080	0xB9	Hardware memory test and init
00:17.850	0xB9	Hardware memory test and init
00:17.850	0xB1	Set DDR4 frequency
00:17.860	0xB7	Train DDR4 ranks
00:17.860	0xB7	Train DDR4 ranks
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xB8	Initialize CLTT/OLTT
00:17.860	0xBA	Execute software memory init
00:17.860	0xB9	Hardware memory test and init
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xBB	Program memory map and interleaving
00:19.930	0xB9	Hardware memory test and init
00:19.930	0xB7	Train DDR4 ranks
00:19.930	0xBC	Program RAS configuration
00:19.930	0xBC	Program RAS configuration
00:19.930	0xBC	Program RAS configuration
00:19.930	0xBC	Program RAS configuration
00:19.930	0xBC	Program RAS configuration
00:19.930	0xBF	MRC is done
00:20.080	0xE7	undefined
00:20.080	0xE8	undefined
00:20.080	0xE9	undefined
00:20.080	0xEB	undefined
00:20.080	0xEC	undefined
00:20.080	0xED	undefined
00:20.080	0xEE	undefined
00:20.220	0x21	undefined
00:25.630	0x4F	DXE IPL Started
00:25.710	0x33	CPU PEIM (Cache Init)
00:26.290	0x36	CPU SMM Init
00:26.780	0x9A	DXE USB start
00:27.760	0xD1	undefined
00:27.820	0xD3	undefined
00:27.820	0xD4	undefined
00:33.470	0x90	DXE BDS Started
00:33.480	0x91	DXE BDS connect drivers
00:33.670	0x92	DXE PCI Bus begin
00:33.670	0x94	DXE PCI Bus enumeration
00:33.680	0x94	DXE PCI Bus enumeration
00:33.680	0x94	DXE PCI Bus enumeration
00:33.680	0x94	DXE PCI Bus enumeration
00:33.690	0x95	DXE PCI Bus resource requested
00:35.000	0xEF	undefined
00:35.070	0x96	DXE PCI Bus assign resource
00:35.080	0x96	DXE PCI Bus assign resource
00:35.080	0x96	DXE PCI Bus assign resource
00:35.080	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.110	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:35.120	0x96	DXE PCI Bus assign resource
00:36.860	0xD5	undefined
00:41.470	0xC0	End of DXE
00:58.840	0x9B	DXE USB reset
00:58.900	0x9C	DXE USB detect
00:58.990	0x9B	DXE USB reset
00:59.050	0x9C	DXE USB detect
00:59.110	0x9C	DXE USB detect
00:59.260	0x9B	DXE USB reset
00:59.480	0x9B	DXE USB reset
00:59.540	0x9C	DXE USB detect
00:59.620	0x9C	DXE USB detect
01:00.470	0x9D	DXE USB enable
01:29.750	0x92	DXE PCI Bus begin
01:29.750	0x96	DXE PCI Bus assign resource
01:29.750	0x96	DXE PCI Bus assign resource
01:29.750	0x96	DXE PCI Bus assign resource
01:29.750	0x96	DXE PCI Bus assign resource
01:29.750	0x96	DXE PCI Bus assign resource
01:29.760	0x96	DXE PCI Bus assign resource
01:29.760	0x96	DXE PCI Bus assign resource
01:29.760	0x96	DXE PCI Bus assign resource
01:29.960	0x96	DXE PCI Bus assign resource
01:29.960	0x96	DXE PCI Bus assign resource
01:29.990	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:30.000	0xA3	Setup minimum path between SBSP and other sockets
01:30.000	0xA5	DXE SCSI begin
01:30.000	0xA7	Topology discovery and route calculation
01:40.340	0x96	DXE PCI Bus assign resource
01:40.340	0x96	DXE PCI Bus assign resource
01:40.440	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:40.440	0xA3	Setup minimum path between SBSP and other sockets
01:40.440	0xA5	DXE SCSI begin
01:40.440	0xA7	Topology discovery and route calculation
01:40.510	0x99	DXE SIO Init
01:40.750	0x92	DXE PCI Bus begin
01:40.750	0x96	DXE PCI Bus assign resource
01:40.750	0x96	DXE PCI Bus assign resource
01:40.750	0x96	DXE PCI Bus assign resource
01:40.750	0x96	DXE PCI Bus assign resource
01:40.750	0x96	DXE PCI Bus assign resource
01:40.750	0x96	DXE PCI Bus assign resource
01:40.760	0x96	DXE PCI Bus assign resource
01:40.760	0x96	DXE PCI Bus assign resource
01:42.590	0x92	DXE PCI Bus begin
01:42.590	0x96	DXE PCI Bus assign resource
01:42.590	0x96	DXE PCI Bus assign resource
01:42.590	0x96	DXE PCI Bus assign resource
01:42.600	0x96	DXE PCI Bus assign resource
01:42.600	0x96	DXE PCI Bus assign resource
01:42.600	0x96	DXE PCI Bus assign resource
01:42.600	0x96	DXE PCI Bus assign resource
01:42.600	0x96	DXE PCI Bus assign resource
01:42.910	0x92	DXE PCI Bus begin
01:42.910	0x96	DXE PCI Bus assign resource
01:42.910	0x96	DXE PCI Bus assign resource
01:42.910	0x96	DXE PCI Bus assign resource
01:42.920	0x96	DXE PCI Bus assign resource
01:42.920	0x96	DXE PCI Bus assign resource
01:42.920	0x96	DXE PCI Bus assign resource
01:42.920	0x96	DXE PCI Bus assign resource
01:42.920	0x96	DXE PCI Bus assign resource
01:45.070	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:45.070	0xA3	Setup minimum path between SBSP and other sockets
01:45.070	0xA5	DXE SCSI begin
01:45.070	0xA7	Topology discovery and route calculation
01:45.230	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:45.230	0xA3	Setup minimum path between SBSP and other sockets
01:45.230	0xA5	DXE SCSI begin
01:45.240	0xA7	Topology discovery and route calculation
01:45.270	0x99	DXE SIO Init
01:49.010	0x92	DXE PCI Bus begin
01:49.010	0x96	DXE PCI Bus assign resource
01:49.010	0x96	DXE PCI Bus assign resource
01:49.010	0x96	DXE PCI Bus assign resource
01:49.010	0x96	DXE PCI Bus assign resource
01:49.010	0x96	DXE PCI Bus assign resource
01:49.020	0x96	DXE PCI Bus assign resource
01:49.020	0x96	DXE PCI Bus assign resource
01:49.020	0x96	DXE PCI Bus assign resource
01:49.200	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:49.200	0xA3	Setup minimum path between SBSP and other sockets
01:49.210	0xA5	DXE SCSI begin
01:49.210	0xA7	Topology discovery and route calculation
01:49.380	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:49.380	0xA3	Setup minimum path between SBSP and other sockets
01:49.380	0xA5	DXE SCSI begin
01:49.380	0xA7	Topology discovery and route calculation
01:49.420	0x99	DXE SIO Init
01:49.570	0x92	DXE PCI Bus begin
01:49.570	0x96	DXE PCI Bus assign resource
01:49.570	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:49.580	0x96	DXE PCI Bus assign resource
01:51.310	0x92	DXE PCI Bus begin
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.320	0x96	DXE PCI Bus assign resource
01:51.630	0x92	DXE PCI Bus begin
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.630	0x96	DXE PCI Bus assign resource
01:51.640	0x96	DXE PCI Bus assign resource
01:53.790	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:53.790	0xA3	Setup minimum path between SBSP and other sockets
01:53.790	0xA5	DXE SCSI begin
01:53.790	0xA7	Topology discovery and route calculation
01:53.950	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
01:53.950	0xA3	Setup minimum path between SBSP and other sockets
01:53.950	0xA5	DXE SCSI begin
01:53.950	0xA7	Topology discovery and route calculation
01:53.980	0x99	DXE SIO Init
02:08.770	0x92	DXE PCI Bus begin
02:08.770	0x96	DXE PCI Bus assign resource
02:08.770	0x96	DXE PCI Bus assign resource
02:08.770	0x96	DXE PCI Bus assign resource
02:08.770	0x96	DXE PCI Bus assign resource
02:08.770	0x96	DXE PCI Bus assign resource
02:08.780	0x96	DXE PCI Bus assign resource
02:08.780	0x96	DXE PCI Bus assign resource
02:08.780	0x96	DXE PCI Bus assign resource
02:08.820	0x92	DXE PCI Bus begin
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.820	0x96	DXE PCI Bus assign resource
02:08.860	0x92	DXE PCI Bus begin
02:08.860	0x96	DXE PCI Bus assign resource
02:08.860	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.870	0x96	DXE PCI Bus assign resource
02:08.910	0x92	DXE PCI Bus begin
02:08.910	0x96	DXE PCI Bus assign resource
02:08.910	0x96	DXE PCI Bus assign resource
02:08.910	0x96	DXE PCI Bus assign resource
02:08.910	0x96	DXE PCI Bus assign resource
02:08.910	0x96	DXE PCI Bus assign resource
02:08.920	0x96	DXE PCI Bus assign resource
02:08.920	0x96	DXE PCI Bus assign resource
02:08.920	0x96	DXE PCI Bus assign resource
02:10.060	0x9D	DXE USB enable
02:10.070	0x9D	DXE USB enable
02:17.050	0x9D	DXE USB enable
03:00.230	0x92	DXE PCI Bus begin
03:00.230	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.240	0x96	DXE PCI Bus assign resource
03:00.430	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
03:00.430	0xA3	Setup minimum path between SBSP and other sockets
03:00.440	0xA5	DXE SCSI begin
03:00.440	0xA7	Topology discovery and route calculation
03:00.610	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
03:00.610	0xA3	Setup minimum path between SBSP and other sockets
03:00.610	0xA5	DXE SCSI begin
03:00.610	0xA7	Topology discovery and route calculation
03:00.660	0x99	DXE SIO Init
03:00.800	0x92	DXE PCI Bus begin
03:00.800	0x96	DXE PCI Bus assign resource
03:00.800	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:00.810	0x96	DXE PCI Bus assign resource
03:02.570	0x92	DXE PCI Bus begin
03:02.570	0x96	DXE PCI Bus assign resource
03:02.570	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.580	0x96	DXE PCI Bus assign resource
03:02.880	0x92	DXE PCI Bus begin
03:02.880	0x96	DXE PCI Bus assign resource
03:02.880	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:02.890	0x96	DXE PCI Bus assign resource
03:05.040	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
03:05.040	0xA3	Setup minimum path between SBSP and other sockets
03:05.050	0xA5	DXE SCSI begin
03:05.050	0xA7	Topology discovery and route calculation
03:05.200	0xA1	Collect infor such as SBSP, boot mode, reset type, etc.
03:05.200	0xA3	Setup minimum path between SBSP and other sockets
03:05.200	0xA5	DXE SCSI begin
03:05.200	0xA7	Topology discovery and route calculation
03:05.240	0x99	DXE SIO Init
03:26.750	0xAC	DXE SETUP input wait