U-Boot SPL 2020.04-06630-g66b56bb5bf-dirty (Nov 26 2020 - 14:58:00 +0100) FPGA: Checking FPGA configuration setting ... FPGA: Start to program peripheral/full bitstream ... FPGA: Early Release Succeeded. U-Boot SPL 2020.04-06630-g66b56bb5bf-dirty (Nov 26 2020 - 14:58:00 +0100) DDRCAL: Success FPGA: Checking FPGA configuration setting ... FPGA: Start to program core bitstream ... Full Configuration Succeeded. FPGA: Enter user mode. WDT: Started with servicing (30s timeout) Trying to boot from MMC1 U-Boot 2020.04-06630-g66b56bb5bf-dirty (Jan 21 2021 - 10:33:47 +0100)socfpga_arria10 CPU: Altera SoCFPGA Arria 10 BOOT: SD/MMC External Transceiver (1.8V) Model: Altera SOCFPGA Arria 10 DRAM: 2 GiB WDT: Started with servicing (30s timeout) MMC: dwmmc0@ff808000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Arria 10 Net: l4_mp_clkclk_enable(clk=7bf7c2c0) noc_free_clk@64clk_enable(clk=7bf7c340) main_noc_base_clkclk_enable(clk=7bf7b640) main_pll@40clk_enable(clk=7bf7b740) osc1clk_enable(clk=7bf7b300) altera_arria10_hps_eosc1clk_enable(clk=7bf7b3c0) Warning: ethernet@ff802000 (eth0) using random MAC address - ca:14:ab:eb:93:20 eth0: ethernet@ff802000 Hit any key to stop autoboot: 2  0 => i2c bus Bus 0: i2c@ffc02300 50: eeprom@50, offset len 1, flags 0 => i2c dev 0 Setting bus to 0 l4_sp_clkclk_enable(clk=7bf7c790) noc_free_clk@64clk_enable(clk=7bf7b5c0) main_noc_base_clkclk_enable(clk=7bf7b640) main_pll@40clk_enable(clk=7bf7b740) osc1clk_enable(clk=7bf7b300) altera_arria10_hps_eosc1clk_enable(clk=7bf7b3c0) => i2c prob Valid chip addresses: 4C 50 68 => run bootcmd 16197608 bytes read in 853 ms (18.1 MiB/s) fpga - loadable FPGA image support Usage: fpga [operation type] [device number] [image address] [image size] fpga operations: dump [dev] [address] [size] Load device to memory buffer info [dev] list known device information load [dev] [address] [size] Load device from memory buffer loadb [dev] [address] [size] Load device from bitstream buffer (Xilinx only) loadmk [dev] [address] Load device generated with mkimage For loadmk operating on FIT format uImage address must include subimage unit name in the form of addr: switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... Found /extlinux/extlinux.conf Retrieving file: /extlinux/extlinux.conf 253 bytes read in 4 ms (61.5 KiB/s) 1: Arria10 SOCDK SDMMC Retrieving file: /extlinux/../zImage 4636312 bytes read in 250 ms (17.7 MiB/s) append: root=/dev/mmcblk0p3 rootwait rw earlycon console=ttyS0,115200 clk_ignore_unused mem=1024M memmap=1024M$0x40000000 Retrieving file: /extlinux/../c4brd_rev1_0.dtb 19604 bytes read in 6 ms (3.1 MiB/s) ## Flattened Device Tree blob at 02000000 Booting using the fdt blob at 0x2000000 usb@ffb00000 Loading Device Tree to 09ff8000, end 09fffc93 ... OK Starting kernel ... call dm_remove_devices_flags call dm_remove_devices_flags in root.c root_driver root_driver device active root_driver (1) root_driver (2) soc soc device active soc (1) soc (2) amba clkmgr@ffd04000 clkmgr@ffd04000 device active clkmgr@ffd04000 (1) clkmgr@ffd04000 (2) cb_intosc_hs_div2_clk cb_intosc_hs_div2_clk device active cb_intosc_hs_div2_clk (1) cb_intosc_hs_div2_clk (2) cb_intosc_hs_div2_clk (3) cb_intosc_hs_div2_clk (4) cb_intosc_hs_div2_clk (5) cb_intosc_hs_div2_clk (6) cb_intosc_hs_div2_clk done cb_intosc_ls_clk cb_intosc_ls_clk device active cb_intosc_ls_clk (1) cb_intosc_ls_clk (2) cb_intosc_ls_clk (3) cb_intosc_ls_clk (4) cb_intosc_ls_clk (5) cb_intosc_ls_clk (6) cb_intosc_ls_clk done f2s_free_clk f2s_free_clk device active f2s_free_clk (1) f2s_free_clk (2) f2s_free_clk (3) f2s_free_clk (4) f2s_free_clk (5) f2s_free_clk (6) f2s_free_clk done osc1 osc1 device active osc1 (1) osc1 (2) osc1 (3) osc1 (4) osc1 (5) osc1 (6) osc1 done main_pll@40 main_pll@40 device active main_pll@40 (1) main_pll@40 (2) main_mpu_base_clk main_mpu_base_clk device active main_mpu_base_clk (1) main_mpu_base_clk (2) main_mpu_base_clk (3) main_mpu_base_clk (4) main_mpu_base_clk (5) main_mpu_base_clk (6) main_mpu_base_clk done main_noc_base_clk main_noc_base_clk device active main_noc_base_clk (1) main_noc_base_clk (2) main_noc_base_clk (3) main_noc_base_clk (4) main_noc_base_clk (5) main_noc_base_clk (6) main_noc_base_clk done main_emaca_clk@68 main_emacb_clk@6c main_emac_ptp_clk@70 main_gpio_db_clk@74 main_sdmmc_clk@78 main_sdmmc_clk@78 device active main_sdmmc_clk@78 (1) main_sdmmc_clk@78 (2) main_sdmmc_clk@78 (3) main_sdmmc_clk@78 (4) main_sdmmc_clk@78 (5) main_sdmmc_clk@78 (6) main_sdmmc_clk@78 done main_s2f_usr0_clk@7c main_s2f_usr1_clk@80 main_hmc_pll_ref_clk@84 main_periph_ref_clk@9c main_periph_ref_clk@9c device active main_periph_ref_clk@9c (1) main_periph_ref_clk@9c (2) main_periph_ref_clk@9c (3) main_periph_ref_clk@9c (4) main_periph_ref_clk@9c (5) main_periph_ref_clk@9c (6) main_periph_ref_clk@9c done main_pll@40 (3) main_pll@40 (4) main_pll@40 (5) main_pll@40 (6) main_pll@40 done periph_pll@c0 periph_pll@c0 device active periph_pll@c0 (1) periph_pll@c0 (2) peri_mpu_base_clk peri_noc_base_clk peri_noc_base_clk device active peri_noc_base_clk (1) peri_noc_base_clk (2) peri_noc_base_clk (3) peri_noc_base_clk (4) peri_noc_base_clk (5) peri_noc_base_clk (6) peri_noc_base_clk done peri_emaca_clk@e8 peri_emacb_clk@ec peri_emac_ptp_clk@f0 peri_gpio_db_clk@f4 peri_sdmmc_clk@f8 peri_sdmmc_clk@f8 device active peri_sdmmc_clk@f8 (1) peri_sdmmc_clk@f8 (2) peri_sdmmc_clk@f8 (3) peri_sdmmc_clk@f8 (4) peri_sdmmc_clk@f8 (5) peri_sdmmc_clk@f8 (6) peri_sdmmc_clk@f8 done peri_s2f_usr0_clk@fc peri_s2f_usr1_clk@100 peri_hmc_pll_ref_clk@104 periph_pll@c0 (3) periph_pll@c0 (4) periph_pll@c0 (5) periph_pll@c0 (6) periph_pll@c0 done mpu_free_clk@60 noc_free_clk@64 noc_free_clk@64 device active noc_free_clk@64 (1) noc_free_clk@64 (2) noc_free_clk@64 (3) noc_free_clk@64 (4) noc_free_clk@64 (5) noc_free_clk@64 (6) noc_free_clk@64 done s2f_user1_free_clk@104 sdmmc_free_clk@f8 sdmmc_free_clk@f8 device active sdmmc_free_clk@f8 (1) sdmmc_free_clk@f8 (2) sdmmc_free_clk@f8 (3) sdmmc_free_clk@f8 (4) sdmmc_free_clk@f8 (5) sdmmc_free_clk@f8 (6) sdmmc_free_clk@f8 done l4_sys_free_clk l4_sys_free_clk device active l4_sys_free_clk (1) l4_sys_free_clk (2) l4_sys_free_clk (3) l4_sys_free_clk (4) l4_sys_free_clk (5) l4_sys_free_clk (6) l4_sys_free_clk done l4_main_clk l4_mp_clk l4_mp_clk device active l4_mp_clk (1) l4_mp_clk (2) l4_mp_clk (3) l4_mp_clk (4) l4_mp_clk (5) l4_mp_clk (6) l4_mp_clk done l4_sp_clk l4_sp_clk device active l4_sp_clk (1) l4_sp_clk (2) l4_sp_clk (3) l4_sp_clk (4) l4_sp_clk (5) l4_sp_clk (6) l4_sp_clk done mpu_periph_clk sdmmc_clk sdmmc_clk device active sdmmc_clk (1) sdmmc_clk (2) sdmmc_clk (3) sdmmc_clk (4) sdmmc_clk (5) sdmmc_clk (6) sdmmc_clk done qspi_clk nand_x_clk nand_ecc_clk nand_clk spi_m_clk usb_clk s2f_usr1_clk clkmgr@ffd04000 (3) clkmgr@ffd04000 (4) clkmgr@ffd04000 (5) clkmgr@ffd04000 (6) clkmgr@ffd04000 done ethernet@ff802000 ethernet@ff802000 device active ethernet@ff802000 (1) ethernet@ff802000 (2) ethernet@ff802000 (3) ethernet@ff802000 (4) ethernet@ff802000 (5) ethernet@ff802000 (6) ethernet@ff802000 done i2c@ffc02300 i2c@ffc02300 device active i2c@ffc02300 (1) i2c@ffc02300 (2) eeprom@50 eeprom@50 device active eeprom@50 (1) eeprom@50 (2) eeprom@50 (3) eeprom@50 (4) eeprom@50 (5) eeprom@50 (6) eeprom@50 done generic_4c generic_4c device active generic_4c (1) generic_4c (2) generic_4c (3) generic_4c (4) generic_4c (5) generic_4c (6) generic_4c done generic_68 generic_68 device active generic_68 (1) generic_68 (2) generic_68 (3) generic_68 (4) generic_68 (5) generic_68 (6) generic_68 done i2c@ffc02300 (3) call drv->remove call designware_i2c_remove disable clock l4_sp_clkclk_disable(clk=7bf7c790)