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    <title>topic Re:Top level-design in Edge Software Catalog</title>
    <link>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1435919#M1133</link>
    <description>&lt;P&gt;If you need any additional information, please submit a new question as this thread will no longer be monitored.&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Mon, 05 Dec 2022 20:22:59 GMT</pubDate>
    <dc:creator>JesusE_Intel</dc:creator>
    <dc:date>2022-12-05T20:22:59Z</dc:date>
    <item>
      <title>Top level-design</title>
      <link>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1432229#M1131</link>
      <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ShashwatS_0-1669137582075.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/35386i1E5A8DBBAD78E340/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="ShashwatS_0-1669137582075.png" alt="ShashwatS_0-1669137582075.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I have Top level-design error on this Verilog code which is for a c-element.&lt;/P&gt;
&lt;P&gt;C-element output= OR( AND(A,B), AND(B, output), AND(A, output)). So basically a feedback is used.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Can you please respond to this issue as soon as possible?&lt;/P&gt;</description>
      <pubDate>Tue, 22 Nov 2022 17:26:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1432229#M1131</guid>
      <dc:creator>ShashwatS</dc:creator>
      <dc:date>2022-11-22T17:26:23Z</dc:date>
    </item>
    <item>
      <title>Re:Top level-design</title>
      <link>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1432247#M1132</link>
      <description>&lt;P&gt;Hi ShashwatS,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;This question does not seem to be related to Intel® Edge Software Device Qualification (ESDQ) package. Could you please confirm which Intel product you are using so I can route your question to the correct team?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jesus&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 22 Nov 2022 18:03:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1432247#M1132</guid>
      <dc:creator>JesusE_Intel</dc:creator>
      <dc:date>2022-11-22T18:03:15Z</dc:date>
    </item>
    <item>
      <title>Re:Top level-design</title>
      <link>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1435919#M1133</link>
      <description>&lt;P&gt;If you need any additional information, please submit a new question as this thread will no longer be monitored.&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 05 Dec 2022 20:22:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Edge-Software-Catalog/Top-level-design/m-p/1435919#M1133</guid>
      <dc:creator>JesusE_Intel</dc:creator>
      <dc:date>2022-12-05T20:22:59Z</dc:date>
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