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    <title>topic Re:Layout documentation for TALIVERDE in Intel® QuickAssist Technology (Intel® QAT)</title>
    <link>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1697597#M643</link>
    <description>&lt;P&gt;Hi Jungsoo,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Let me do some investigation and I will get back to you as soon as possible.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Ronny G&lt;/P&gt;&lt;BR /&gt;</description>
    <pubDate>Mon, 16 Jun 2025 20:25:45 GMT</pubDate>
    <dc:creator>Ronny_G_Intel</dc:creator>
    <dc:date>2025-06-16T20:25:45Z</dc:date>
    <item>
      <title>Layout documentation for TALIVERDE</title>
      <link>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1696354#M638</link>
      <description>&lt;P&gt;We have found the &lt;STRONG&gt;TALIVERDE schematics&lt;/STRONG&gt; as below:&lt;/P&gt;&lt;P&gt;Lewisburg PCH in Endpoint Only (EPO) Mode – Reference Schematics&lt;BR /&gt;ID: 560351&lt;/P&gt;&lt;P&gt;Additionally, could we please get the&lt;STRONG&gt; layout&lt;/STRONG&gt; documentation for TALIVERDE as well?&lt;/P&gt;</description>
      <pubDate>Wed, 11 Jun 2025 06:32:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1696354#M638</guid>
      <dc:creator>jungsoolim</dc:creator>
      <dc:date>2025-06-11T06:32:29Z</dc:date>
    </item>
    <item>
      <title>Re:Layout documentation for TALIVERDE</title>
      <link>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1697597#M643</link>
      <description>&lt;P&gt;Hi Jungsoo,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Let me do some investigation and I will get back to you as soon as possible.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Ronny G&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 16 Jun 2025 20:25:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1697597#M643</guid>
      <dc:creator>Ronny_G_Intel</dc:creator>
      <dc:date>2025-06-16T20:25:45Z</dc:date>
    </item>
    <item>
      <title>Re:Layout documentation for TALIVERDE</title>
      <link>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1699245#M654</link>
      <description>&lt;P&gt;Hi Jungsoo,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please find below the link to schematics for:&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;TALIVERDE&lt;/P&gt;&lt;P&gt;TECHNOLOGY AND INTEGRATED 10 GBE / 1 GBE&lt;/P&gt;&lt;P&gt;LEWISBURG CHIPSET: ENDPOINT ONLY (EPO) MODE&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/www/us/en/secure/content-details/560351/lewisburg-pch-in-endpoint-only-epo-mode-reference-schematics.html?wapkw=taliverde&amp;amp;DocID=560351" target="_blank"&gt;https://www.intel.com/content/www/us/en/secure/content-details/560351/lewisburg-pch-in-endpoint-only-epo-mode-reference-schematics.html?wapkw=taliverde&amp;amp;DocID=560351&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please note that this information is classified as Intel Confidential, requiring the appropriate level of permissions for access.&lt;/P&gt;&lt;P&gt;I also created an IPS ticket to address this issue, so I am closing this community post. Please use the IPS ticket to follow up on this issue.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Ronny G&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 23 Jun 2025 19:55:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-QuickAssist-Technology/Layout-documentation-for-TALIVERDE/m-p/1699245#M654</guid>
      <dc:creator>Ronny_G_Intel</dc:creator>
      <dc:date>2025-06-23T19:55:36Z</dc:date>
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