<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Dear Peter, in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981734#M10099</link>
    <description>&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Dear Peter,&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thanks a lot. That is exactly what I need.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Peter Wang (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;The doc you referenced is for general description of structural event list for Intel(R) Core(TM) processors.&lt;/P&gt;
&lt;P&gt;Some events name&amp;nbsp;are "basic" or some are "unique" for different processors. You'd better check supported&amp;nbsp;events&amp;nbsp;in your system, by using:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;amplxe-runss -event-list&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 27 Mar 2013 16:14:53 GMT</pubDate>
    <dc:creator>Hanqing_H_</dc:creator>
    <dc:date>2013-03-27T16:14:53Z</dc:date>
    <item>
      <title>Hardware event construction</title>
      <link>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981732#M10097</link>
      <description>&lt;P&gt;Sorry to ask a stupid question. We have a 4P Intel Xeon E5-4620 CPU (Sandy Bridge), and we want to use vtune to moniter some hardware events in the packege. &amp;nbsp;Our motherboard is Dell R720. So, where can we get the events that can be sampled with vtune-update5? I have seen a list in the last section of&amp;nbsp;&lt;A href="http://software.intel.com/sites/products/documentation/doclib/stdxe/2013/amplifierxe/lin/ug_docs/index.htm"&gt;http://software.intel.com/sites/products/documentation/doclib/stdxe/2013...&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;But a lot of events that claimed to be supported in Xeon processors cannot be sampled. For example, when run&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;amplxe-cl&amp;nbsp;-collect-with runsa -knob event-config="SNOOP_RESPONSE.HIT" ls -alrt&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;I get&lt;/P&gt;
&lt;P&gt;amplxe: Error: Invalid Event SNOOP_RESPONSE.HIT discarded.&lt;/P&gt;
&lt;P&gt;However, I succeeded once with "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE_0" event. But I&amp;nbsp;have tried several others and get the same "invaild event" response, like&amp;nbsp;OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_MISS_LOCAL_DRAM,&amp;nbsp;MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS &amp;nbsp;etc.&lt;/P&gt;
&lt;P&gt;The purpose of my test is to using "OFFCORE_RESPONSE_0" with snoop filter to moniter the snoop traffic between CPUs.&amp;nbsp;The method to sample OFFCORE_RESPONSE_0 event is as section 18.8.5 in&amp;nbsp;&lt;A href="http://download.intel.com/products/processor/manual/325462.pdf"&gt;http://download.intel.com/products/processor/manual/325462.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;But what is way to utilize this method in vtune?&lt;/P&gt;
&lt;P&gt;I also made sure that there was only one instance of vtune running in the system. So where can we get the valid event list or how can we construct the righ event for moniter?&lt;/P&gt;
&lt;P&gt;Thanks a lot!&lt;/P&gt;</description>
      <pubDate>Tue, 26 Mar 2013 16:37:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981732#M10097</guid>
      <dc:creator>Hanqing_H_</dc:creator>
      <dc:date>2013-03-26T16:37:24Z</dc:date>
    </item>
    <item>
      <title>The doc you referenced is for</title>
      <link>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981733#M10098</link>
      <description>&lt;P&gt;The doc you referenced is for general description of structural event list for Intel(R) Core(TM) processors.&lt;/P&gt;
&lt;P&gt;Some events name&amp;nbsp;are "basic" or some are "unique" for different processors. You'd better check supported&amp;nbsp;events&amp;nbsp;in your system, by using:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;amplxe-runss -event-list&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Mar 2013 01:26:02 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981733#M10098</guid>
      <dc:creator>Peter_W_Intel</dc:creator>
      <dc:date>2013-03-27T01:26:02Z</dc:date>
    </item>
    <item>
      <title>Dear Peter,</title>
      <link>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981734#M10099</link>
      <description>&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Dear Peter,&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;Thanks a lot. That is exactly what I need.&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Peter Wang (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;
&lt;P&gt;The doc you referenced is for general description of structural event list for Intel(R) Core(TM) processors.&lt;/P&gt;
&lt;P&gt;Some events name&amp;nbsp;are "basic" or some are "unique" for different processors. You'd better check supported&amp;nbsp;events&amp;nbsp;in your system, by using:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;amplxe-runss -event-list&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Mar 2013 16:14:53 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981734#M10099</guid>
      <dc:creator>Hanqing_H_</dc:creator>
      <dc:date>2013-03-27T16:14:53Z</dc:date>
    </item>
    <item>
      <title>Additionally, probably the</title>
      <link>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981735#M10100</link>
      <description>&lt;P&gt;Additionally, probably the best events to use for monitoring traffic between sockets are:&lt;/P&gt;
&lt;P&gt;OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD_0/1, OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM_0/1.&lt;/P&gt;
&lt;P&gt;These include true demand reads, as well as L1 hardware prefetches.&amp;nbsp; Unfortunately there are no OFFCORE_RESPONSE events that do not also get triggered by L1 hardware prefetches, so these are the best choice.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 27 Mar 2013 16:31:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Hardware-event-construction/m-p/981735#M10100</guid>
      <dc:creator>Shannon_C_Intel</dc:creator>
      <dc:date>2013-03-27T16:31:17Z</dc:date>
    </item>
  </channel>
</rss>

