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    <title>topic Quote:Alexandra S. (Intel) in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108346#M16091</link>
    <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Alexandra S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Yes, events are tied to the CPU architecture. This is because events are generated by the hardware itself. VTune just receives that information and does neat things with the numbers.&lt;/P&gt;

&lt;P&gt;As for "i7," be careful. Not all Core(TM) i7s are the same! There are several generations of them, which use different microarchitectures. &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors&lt;/A&gt;&lt;BR /&gt;
	Yours is a 6700, so it is a Skylake: &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Because the events are generated by the hardware, you cannot use an event that is not supported by your CPU - there is physically nothing to count/generate that event. That's why that event reference I linked you to earlier is so helpful; it tells you all the events for a given microarchitecture.&lt;BR /&gt;
	However, if an event &lt;EM&gt;is&lt;/EM&gt; supported by your CPU, but is not "in the list" for a &lt;EM&gt;particular&lt;/EM&gt; analysis type, you should be able to create a custom analysis that tracks that event. Please note that this is not the same thing as when the event is not "in the list" of events for that CPU!&lt;/P&gt;

&lt;P&gt;As far as I know, every version of VTune is capable of using all the events of microarchitectures that existed at the time - but it can only work with what the CPU actually gives it. If a CPU is not capable of generating a particular event, VTune can't tell you anything about that event, since it's not getting any information about it from the hardware.&lt;BR /&gt;
	For the record, I &lt;EM&gt;don't&lt;/EM&gt; think it's true the other way around. That is, I don't think &lt;EM&gt;older&lt;/EM&gt; versions of VTune can understand &lt;EM&gt;new&lt;/EM&gt; events that were added in later microarchitectures. So technically, different versions of VTune would have different event lists - but only because &lt;EM&gt;more &lt;/EM&gt;events were added, not because any were removed.&lt;/P&gt;

&lt;P&gt;Does that answer your question?&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;HI Alexandra,&lt;/P&gt;

&lt;P&gt;Thank you so much for this, I think it is very helpful.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 11 Oct 2016 21:55:23 GMT</pubDate>
    <dc:creator>liu__kevin</dc:creator>
    <dc:date>2016-10-11T21:55:23Z</dc:date>
    <item>
      <title>Does new Vtune include “LOAD_DISPATCH.ANY” event?</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108342#M16087</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;Does anyone knows the new vtune 2016 have the event “LOAD_DISPATCH.ANY”? I have not found it in the event list while I wanted to add it. I think my cpu support that, and I attached the cpu infomation also.&lt;/P&gt;

&lt;P&gt;bogomips&amp;nbsp;&amp;nbsp; &amp;nbsp;: 6815.88&lt;BR /&gt;
	clflush size&amp;nbsp;&amp;nbsp; &amp;nbsp;: 64&lt;BR /&gt;
	cache_alignment&amp;nbsp;&amp;nbsp; &amp;nbsp;: 64&lt;BR /&gt;
	address sizes&amp;nbsp;&amp;nbsp; &amp;nbsp;: 39 bits physical, 48 bits virtual&lt;BR /&gt;
	power management:&lt;/P&gt;

&lt;P&gt;processor&amp;nbsp;&amp;nbsp; &amp;nbsp;: 7&lt;BR /&gt;
	vendor_id&amp;nbsp;&amp;nbsp; &amp;nbsp;: GenuineIntel&lt;BR /&gt;
	cpu family&amp;nbsp;&amp;nbsp; &amp;nbsp;: 6&lt;BR /&gt;
	model&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: 94&lt;BR /&gt;
	model name&amp;nbsp;&amp;nbsp; &amp;nbsp;: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz&lt;BR /&gt;
	stepping&amp;nbsp;&amp;nbsp; &amp;nbsp;: 3&lt;BR /&gt;
	microcode&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0x8a&lt;BR /&gt;
	cpu MHz&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: 899.937&lt;BR /&gt;
	cache size&amp;nbsp;&amp;nbsp; &amp;nbsp;: 8192 KB&lt;BR /&gt;
	physical id&amp;nbsp;&amp;nbsp; &amp;nbsp;: 0&lt;BR /&gt;
	siblings&amp;nbsp;&amp;nbsp; &amp;nbsp;: 8&lt;BR /&gt;
	core id&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: 3&lt;BR /&gt;
	cpu cores&amp;nbsp;&amp;nbsp; &amp;nbsp;: 4&lt;BR /&gt;
	apicid&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: 7&lt;BR /&gt;
	initial apicid&amp;nbsp;&amp;nbsp; &amp;nbsp;: 7&lt;BR /&gt;
	fpu&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: yes&lt;BR /&gt;
	fpu_exception&amp;nbsp;&amp;nbsp; &amp;nbsp;: yes&lt;BR /&gt;
	cpuid level&amp;nbsp;&amp;nbsp; &amp;nbsp;: 22&lt;BR /&gt;
	wp&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: yes&lt;BR /&gt;
	flags&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx rdseed adx smap clflushopt xsaveopt xsavec xgetbv1 dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp&lt;BR /&gt;
	bugs&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;:&lt;BR /&gt;
	bogomips&amp;nbsp;&amp;nbsp; &amp;nbsp;: 6815.88&lt;BR /&gt;
	clflush size&amp;nbsp;&amp;nbsp; &amp;nbsp;: 64&lt;BR /&gt;
	cache_alignment&amp;nbsp;&amp;nbsp; &amp;nbsp;: 64&lt;BR /&gt;
	address sizes&amp;nbsp;&amp;nbsp; &amp;nbsp;: 39 bits physical, 48 bits virtual&lt;BR /&gt;
	power management:&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Thank you.&lt;/P&gt;</description>
      <pubDate>Mon, 10 Oct 2016 19:14:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108342#M16087</guid>
      <dc:creator>liu__kevin</dc:creator>
      <dc:date>2016-10-10T19:14:27Z</dc:date>
    </item>
    <item>
      <title>Hi, Kevin,</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108343#M16088</link>
      <description>&lt;P&gt;Hi, Kevin,&lt;/P&gt;

&lt;P&gt;It looks like your CPU is a Skylake, which does not have the LOAD_DISPATCH.ANY event. You can find a list of events for Skylake here: &lt;A href="https://software.intel.com/en-us/node/589938"&gt;https://software.intel.com/en-us/node/589938&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 10 Oct 2016 23:20:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108343#M16088</guid>
      <dc:creator>Alexandra_S_Intel</dc:creator>
      <dc:date>2016-10-10T23:20:00Z</dc:date>
    </item>
    <item>
      <title>Quote:Alexandra S. (Intel)</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108344#M16089</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Alexandra S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Hi, Kevin,&lt;/P&gt;

&lt;P&gt;It looks like your CPU is a Skylake, which does not have the LOAD_DISPATCH.ANY event. You can find a list of events for Skylake here: &lt;A href="https://software.intel.com/en-us/node/589938"&gt;https://software.intel.com/en-us/node/589938&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Hi Alexandra,&lt;/P&gt;

&lt;P&gt;Thank you so much for your reply, so the events depend on the cpu not vtune? but I see the manual of i7, it has that event, I am not clear about this. And I did not find another event counter, which I found it in vtune 2011, but in 2017 it do not have, certainly, machines are different. So, can I still use the event even though it do not have in the list? does there have a method like I can write something or use command to call/use the event which is not in list but I saw in vtune 2011.&lt;/P&gt;

&lt;P&gt;Another question, does vtune 2017 and 2011 have same event list? does the list shows different depending on different machine?&lt;/P&gt;

&lt;P&gt;Thank you.&lt;/P&gt;</description>
      <pubDate>Tue, 11 Oct 2016 20:59:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108344#M16089</guid>
      <dc:creator>liu__kevin</dc:creator>
      <dc:date>2016-10-11T20:59:05Z</dc:date>
    </item>
    <item>
      <title>Yes, events are tied to the</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108345#M16090</link>
      <description>&lt;P&gt;Yes, events are tied to the CPU architecture. This is because events are generated by the hardware itself. VTune just receives that information and does neat things with the numbers.&lt;/P&gt;

&lt;P&gt;As for "i7," be careful. Not all Core(TM) i7s are the same! There are several generations of them, which use different microarchitectures. &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors&lt;/A&gt;&lt;BR /&gt;
	Yours is a 6700, so it is a Skylake: &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Because the events are generated by the hardware, you cannot use an event that is not supported by your CPU - there is physically nothing to count/generate that event. That's why that event reference I linked you to earlier is so helpful; it tells you all the events for a given microarchitecture.&lt;BR /&gt;
	However, if an event &lt;EM&gt;is&lt;/EM&gt; supported by your CPU, but is not "in the list" for a &lt;EM&gt;particular&lt;/EM&gt; analysis type, you should be able to create a custom analysis that tracks that event. Please note that this is not the same thing as when the event is not "in the list" of events for that CPU!&lt;/P&gt;

&lt;P&gt;As far as I know, every version of VTune is capable of using all the events of microarchitectures that existed at the time - but it can only work with what the CPU actually gives it. If a CPU is not capable of generating a particular event, VTune can't tell you anything about that event, since it's not getting any information about it from the hardware.&lt;BR /&gt;
	For the record, I &lt;EM&gt;don't&lt;/EM&gt; think it's true the other way around. That is, I don't think &lt;EM&gt;older&lt;/EM&gt; versions of VTune can understand &lt;EM&gt;new&lt;/EM&gt; events that were added in later microarchitectures. So technically, different versions of VTune would have different event lists - but only because &lt;EM&gt;more &lt;/EM&gt;events were added, not because any were removed.&lt;/P&gt;

&lt;P&gt;Does that answer your question?&lt;/P&gt;</description>
      <pubDate>Tue, 11 Oct 2016 21:30:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108345#M16090</guid>
      <dc:creator>Alexandra_S_Intel</dc:creator>
      <dc:date>2016-10-11T21:30:28Z</dc:date>
    </item>
    <item>
      <title>Quote:Alexandra S. (Intel)</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108346#M16091</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Alexandra S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Yes, events are tied to the CPU architecture. This is because events are generated by the hardware itself. VTune just receives that information and does neat things with the numbers.&lt;/P&gt;

&lt;P&gt;As for "i7," be careful. Not all Core(TM) i7s are the same! There are several generations of them, which use different microarchitectures. &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors&lt;/A&gt;&lt;BR /&gt;
	Yours is a 6700, so it is a Skylake: &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Because the events are generated by the hardware, you cannot use an event that is not supported by your CPU - there is physically nothing to count/generate that event. That's why that event reference I linked you to earlier is so helpful; it tells you all the events for a given microarchitecture.&lt;BR /&gt;
	However, if an event &lt;EM&gt;is&lt;/EM&gt; supported by your CPU, but is not "in the list" for a &lt;EM&gt;particular&lt;/EM&gt; analysis type, you should be able to create a custom analysis that tracks that event. Please note that this is not the same thing as when the event is not "in the list" of events for that CPU!&lt;/P&gt;

&lt;P&gt;As far as I know, every version of VTune is capable of using all the events of microarchitectures that existed at the time - but it can only work with what the CPU actually gives it. If a CPU is not capable of generating a particular event, VTune can't tell you anything about that event, since it's not getting any information about it from the hardware.&lt;BR /&gt;
	For the record, I &lt;EM&gt;don't&lt;/EM&gt; think it's true the other way around. That is, I don't think &lt;EM&gt;older&lt;/EM&gt; versions of VTune can understand &lt;EM&gt;new&lt;/EM&gt; events that were added in later microarchitectures. So technically, different versions of VTune would have different event lists - but only because &lt;EM&gt;more &lt;/EM&gt;events were added, not because any were removed.&lt;/P&gt;

&lt;P&gt;Does that answer your question?&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;HI Alexandra,&lt;/P&gt;

&lt;P&gt;Thank you so much for this, I think it is very helpful.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 11 Oct 2016 21:55:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108346#M16091</guid>
      <dc:creator>liu__kevin</dc:creator>
      <dc:date>2016-10-11T21:55:23Z</dc:date>
    </item>
    <item>
      <title>Quote:Alexandra S. (Intel)</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108347#M16092</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Alexandra S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Yes, events are tied to the CPU architecture. This is because events are generated by the hardware itself. VTune just receives that information and does neat things with the numbers.&lt;/P&gt;

&lt;P&gt;As for "i7," be careful. Not all Core(TM) i7s are the same! There are several generations of them, which use different microarchitectures. &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors&lt;/A&gt;&lt;BR /&gt;
	Yours is a 6700, so it is a Skylake: &lt;A href="https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29" rel="nofollow"&gt;https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_microprocessors#Skylake_microarchitecture_.286th_generation.29&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Because the events are generated by the hardware, you cannot use an event that is not supported by your CPU - there is physically nothing to count/generate that event. That's why that event reference I linked you to earlier is so helpful; it tells you all the events for a given microarchitecture.&lt;BR /&gt;
	However, if an event &lt;EM&gt;is&lt;/EM&gt; supported by your CPU, but is not "in the list" for a &lt;EM&gt;particular&lt;/EM&gt; analysis type, you should be able to create a custom analysis that tracks that event. Please note that this is not the same thing as when the event is not "in the list" of events for that CPU!&lt;/P&gt;

&lt;P&gt;As far as I know, every version of VTune is capable of using all the events of microarchitectures that existed at the time - but it can only work with what the CPU actually gives it. If a CPU is not capable of generating a particular event, VTune can't tell you anything about that event, since it's not getting any information about it from the hardware.&lt;BR /&gt;
	For the record, I &lt;EM&gt;don't&lt;/EM&gt; think it's true the other way around. That is, I don't think &lt;EM&gt;older&lt;/EM&gt; versions of VTune can understand &lt;EM&gt;new&lt;/EM&gt; events that were added in later microarchitectures. So technically, different versions of VTune would have different event lists - but only because &lt;EM&gt;more &lt;/EM&gt;events were added, not because any were removed.&lt;/P&gt;

&lt;P&gt;Does that answer your question?&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;Hi Alexandra,&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;I am testing i7-6700 with Vtune 2016 with SPEC 2006. From the definitions, I believe the following should satisfy:&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;MEM_INST_RETIRED.ALL_LOADS = MEM_LOAD_RETIRED.L1_HIT + MEM_LOAD_RETIRED.L1_MISS&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;MEM_INST_RETIRED.ALL_LOADS&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;All retired load instructions.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;MEM_LOAD_RETIRED.L1_HIT&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;Retired load instructions with L1 cache hits as data sources.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;MEM_LOAD_RETIRED.L1_MISS&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;Retired load instructions missed L1 cache as data sources&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;However, for some programs (LIBQUANTUM and MCF) where L1D cache miss rate is high, the three numbers are listed as follows.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;(&lt;SPAN lang="en-US"&gt;&lt;SPAN style="background-color:#C6EFCE;"&gt;&lt;FONT size="3" face="Times New Roman,serif"&gt;&lt;SPAN style="font-size:12pt;"&gt;&lt;FONT size="2" face="Arial,sans-serif"&gt;&lt;SPAN style="font-size:10pt;"&gt;MEM_INST_RETIRED.ALL_LOADS,MEM_LOAD_RETIRED.L1_HIT,MEM_LOAD_RETIRED.L1_MISS &lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;)&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;SPAN style="background-color:#C6EFCE;"&gt;&lt;FONT size="3" face="Times New Roman,serif"&gt;&lt;SPAN style="font-size:12pt;"&gt;&lt;FONT size="2" color="#006100" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;LIBQUANTUM : 2.47E+10, 1.40E+10, 2.67E+09, respectively.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;SPAN style="background-color:#C6EFCE;"&gt;&lt;FONT size="3" face="Times New Roman,serif"&gt;&lt;SPAN style="font-size:12pt;"&gt;&lt;FONT size="2" color="#006100" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;MCF &amp;nbsp;1.15E+11, 7.57E+10, 2.43E+10, respectively.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;&amp;nbsp;&lt;/DIV&gt;

&lt;DIV style="margin:0;"&gt;
	&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;You see there are gaps for these programs. Can you please explain?&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

	&lt;DIV style="margin:0;"&gt;&amp;nbsp;&lt;/DIV&gt;

	&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;Thank you.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
	&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;

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&lt;/TABLE&gt;

&lt;P&gt;&amp;nbsp;
	&lt;/P&gt;&lt;DIV style="margin:0;"&gt;&lt;SPAN lang="en-US"&gt;&lt;FONT size="2" face="Calibri,sans-serif"&gt;&lt;SPAN style="font-size:11pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 11 Oct 2016 22:27:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108347#M16092</guid>
      <dc:creator>liu__kevin</dc:creator>
      <dc:date>2016-10-11T22:27:00Z</dc:date>
    </item>
    <item>
      <title>Hello, Kevin,</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108348#M16093</link>
      <description>&lt;P&gt;Hello, Kevin,&lt;/P&gt;

&lt;P&gt;I apologize for the delay; I've been busy.&lt;/P&gt;

&lt;P&gt;It seems likely that the missing factor here is MEM_LOAD_RETIRED.FB_HIT.&lt;BR /&gt;
	Sometimes loads miss L1 but hit FB due to a preceding miss in the same cache line. As I understand it, these are not counted in the MEM_LOAD_RETIRED.L1_MISS event counter. Instead they are recorded in MEM_LOAD_RETIRED.FB_HIT.&lt;/P&gt;

&lt;P&gt;So your equation should look like so, approximately:&lt;BR /&gt;
	MEM_INST_RETIRED.ALL_LOADS = MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.L1_HIT + MEM_LOAD_RETIRED.FB_HIT&lt;/P&gt;

&lt;P&gt;That said, this will still not be exact. You can expect a small, statistically insignificant difference in results, due to the way event counting works.&lt;BR /&gt;
	Multiplexing and sampling, among other things, can cause you to miss a few events. It's a complicated topic but basically, if we just took note of every event that occurred, it would slow everything down to the point that collecting useful data would be impossible. Instead we have a few hardware counters that count a certain number of events, and every once in a while we take note of how many events occurred in that time block. Making things even more complicated, there are only a few hardware counters, so we have to have them switch out between different events to count. You can get more information here: &lt;A href="https://software.intel.com/en-us/articles/understanding-how-general-exploration-works-in-intel-vtune-amplifier-xe"&gt;https://software.intel.com/en-us/articles/understanding-how-general-exploration-works-in-intel-vtune-amplifier-xe&lt;/A&gt;&lt;BR /&gt;
	There are numerous other things that can cause very small differences, and I won't list them all - I don't even claim to know them all, because there are a lot of them, and as I said, they produce such small, insignificant mismatches that they can be more or less ignored.&lt;/P&gt;

&lt;P&gt;Does this answer your question?&lt;/P&gt;</description>
      <pubDate>Fri, 14 Oct 2016 17:42:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108348#M16093</guid>
      <dc:creator>Alexandra_S_Intel</dc:creator>
      <dc:date>2016-10-14T17:42:52Z</dc:date>
    </item>
    <item>
      <title>Quote:Alexandra S. (Intel)</title>
      <link>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108349#M16094</link>
      <description>&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;Alexandra S. (Intel) wrote:&lt;BR /&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;Hello, Kevin,&lt;/P&gt;

&lt;P&gt;I apologize for the delay; I've been busy.&lt;/P&gt;

&lt;P&gt;It seems likely that the missing factor here is MEM_LOAD_RETIRED.FB_HIT.&lt;BR /&gt;
	Sometimes loads miss L1 but hit FB due to a preceding miss in the same cache line. As I understand it, these are not counted in the MEM_LOAD_RETIRED.L1_MISS event counter. Instead they are recorded in MEM_LOAD_RETIRED.FB_HIT.&lt;/P&gt;

&lt;P&gt;So your equation should look like so, approximately:&lt;BR /&gt;
	MEM_INST_RETIRED.ALL_LOADS = MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.L1_HIT + MEM_LOAD_RETIRED.FB_HIT&lt;/P&gt;

&lt;P&gt;That said, this will still not be exact. You can expect a small, statistically insignificant difference in results, due to the way event counting works.&lt;BR /&gt;
	Multiplexing and sampling, among other things, can cause you to miss a few events. It's a complicated topic but basically, if we just took note of every event that occurred, it would slow everything down to the point that collecting useful data would be impossible. Instead we have a few hardware counters that count a certain number of events, and every once in a while we take note of how many events occurred in that time block. Making things even more complicated, there are only a few hardware counters, so we have to have them switch out between different events to count. You can get more information here: &lt;A href="https://software.intel.com/en-us/articles/understanding-how-general-exploration-works-in-intel-vtune-amplifier-xe"&gt;https://software.intel.com/en-us/articles/understanding-how-general-exploration-works-in-intel-vtune-amplifier-xe&lt;/A&gt;&lt;BR /&gt;
	There are numerous other things that can cause very small differences, and I won't list them all - I don't even claim to know them all, because there are a lot of them, and as I said, they produce such small, insignificant mismatches that they can be more or less ignored.&lt;/P&gt;

&lt;P&gt;Does this answer your question?&lt;/P&gt;

&lt;P&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;Hi Alexandra,&lt;/P&gt;

&lt;P&gt;Thank you so much for your reply, it helps so much.&lt;/P&gt;

&lt;P&gt;I will change the configuration to see the result.&lt;/P&gt;

&lt;P&gt;Thank you for your time.&lt;/P&gt;

&lt;P&gt;Have a nice day.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 16 Oct 2016 19:36:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Does-new-Vtune-include-LOAD-DISPATCH-ANY-event/m-p/1108349#M16094</guid>
      <dc:creator>liu__kevin</dc:creator>
      <dc:date>2016-10-16T19:36:24Z</dc:date>
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