topic Both the vectorized and in Analyzers

Packed non-vectorized FP operations

psing51 — Tue, 14 Apr 2020 10:54:19 GMT

I am using vtune 2020u0 on intel 8280 platform. I carried out an HPC characterization analysis and was looking at the Heading of Vectorization Section which has

Vectorization:	77.7% of Packed FP Operations
    Instruction Mix:	
    SP FLOPs:	15.4%
    Packed:	79.8%
    128-bit:	0.0%
    256-bit:	0.1%
    512-bit:	79.8%
    Scalar:	20.2%
    DP FLOPs:	0.4%
    x87 FLOPs:	0.0%
    Non-FP:	84.2%
    FP Arith/Mem Rd Instr. Ratio:	0.462
    FP Arith/Mem Wr Instr. Ratio:	1.369

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checked for a detailed explanation here , but was unable to gain clarity so asking my queries here.
From report it seems code issued packed + non packed instructions and, out of all the packed FP instructions issued during code execution, only 77.7% were vectorized - Which (AFAIK) means these instructions resulted in use of AVX/AVX2/AVX512 bit registers.

Could you please explain / refer me to an article which explains the (general) reasons for non-vectorization of (in my case - 22.3% of packed instructions) packed instructions? and how these packed instructions would execute (using scalar registers?)?

For example - mm256_add_ps is a packed instruction, so could you help me in understanding that how the add operation could be non-vectorized in following context -

float f[8]={1.0,2.0,1.2,2.1, 5.2,5.3,10.1,11.0};
__m256 v=_mm256_load_ps(&f[0]);
v=_mm256_add_ps(v,v);

The aforementioned code is not related to the code which i have profiled.

Both the vectorized and

McCalpinJohn — Tue, 14 Apr 2020 15:24:26 GMT

Both the vectorized and scalar instructions use the same registers, but the "scalar" versions of the instructions only use one "lane" of data (and only one "lane" of the corresponding arithmetic functional unit(s)).

Vectorization can be inhibited by a number of issues. You should start by adding "-qopt-report=3 -qopt-report-phase=vec" to the compile flags and reviewing the resulting ".optrpt" file(s). You will probably want to try several different report levels (1-5, I picked 3 to start) -- they provide increasing information with increasing level.

Operations that can't be vectorized are sometimes easy to fix (e.g., possible aliasing), sometimes hard to fix (e.g., related to data structure layout), and sometimes impossible to fix (e.g., data dependence as an essential characteristic of the algorithm in use).

Hello,

Dmitry_P_Intel1 — Tue, 14 Apr 2020 15:26:11 GMT

Hello,

Just to avoid confusions - 77.7% of packed instructions of all precision types are vector instructions.

The metrics hierarchy supposed to be:

Vectorization: 77.7% of Packed FP Operations
       Instruction Mix:
          SP FLOPs:   15.4%
                Packed: 79.8%
                     128-bit:    0.0%
                     256-bit:    0.1%
                     512-bit:    79.8%
                Scalar: 20.2%
          DP FLOPs:   0.4%
        x87 FLOPs: 0.0%
          Non-FP: 84.2%

By some reason DP FLOPs are not broken down by packed and scalar in your case.

To see why 22.3% of scalar instructions are not vectorized you can use Intel Advisor.

Thank you, Regards, Dmitry

Hi puneet,

JananiC_Intel — Fri, 17 Apr 2020 13:49:05 GMT

Hi puneet,

Was the solution provided helpful?

Thanks.

Hi,

JananiC_Intel — Fri, 24 Apr 2020 12:12:53 GMT

Hi,

We are closing this case by assuming that your issue got resolved. Please feel free to raise a new thread if you have further issues.

Thanks.