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    <title>topic Re: Meaning of Intel Advisor GOPS in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257236#M20035</link>
    <description>&lt;P&gt;Thanks. Assuming that the count is based on retired instructions, would it be possible to get a list of instructions that result in counts as both GFLOPS and INTOPS?&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;
&lt;P&gt;jgw&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 18 Feb 2021 15:47:59 GMT</pubDate>
    <dc:creator>jgwohlbier</dc:creator>
    <dc:date>2021-02-18T15:47:59Z</dc:date>
    <item>
      <title>Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1256877#M20026</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;I'm wondering specifically what is Advisor is reporting for GFLOPS and GINTOPS. Is it reporting instructions retired and account for vector instructions? I.e., would an 8-way vector fused multiply add instruction be counted as 16 operations?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks!&lt;/P&gt;
&lt;P&gt;jgw&lt;/P&gt;</description>
      <pubDate>Wed, 17 Feb 2021 17:35:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1256877#M20026</guid>
      <dc:creator>jgwohlbier</dc:creator>
      <dc:date>2021-02-17T17:35:30Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257125#M20029</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;Yes, Advisor takes into account that FMA instruction is not single operation but it's a number of operations. Specifically, for N elements we have N multiplies and N additions (for each of mul result)&lt;/P&gt;</description>
      <pubDate>Thu, 18 Feb 2021 07:53:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257125#M20029</guid>
      <dc:creator>Ruslan_M_Intel</dc:creator>
      <dc:date>2021-02-18T07:53:42Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257236#M20035</link>
      <description>&lt;P&gt;Thanks. Assuming that the count is based on retired instructions, would it be possible to get a list of instructions that result in counts as both GFLOPS and INTOPS?&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;
&lt;P&gt;jgw&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 18 Feb 2021 15:47:59 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257236#M20035</guid>
      <dc:creator>jgwohlbier</dc:creator>
      <dc:date>2021-02-18T15:47:59Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257249#M20036</link>
      <description>&lt;P&gt;I'm not sure if FMA contains any instruction which operate on both floating-point and integer data. Could you give an example?&lt;/P&gt;</description>
      <pubDate>Thu, 18 Feb 2021 16:16:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257249#M20036</guid>
      <dc:creator>Ruslan_M_Intel</dc:creator>
      <dc:date>2021-02-18T16:16:43Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257270#M20037</link>
      <description>&lt;P&gt;Sorry, that's not what I meant.&lt;/P&gt;
&lt;P&gt;I am interested in a list of instructions that result in GFLOPS counts, and a list of instructions that result in GINTOPS counts. I imagine it is all of the arithmetic instructions and vector variants of those instructions, both for floats and for ints, respectively.&lt;/P&gt;
&lt;P&gt;Thanks.&lt;/P&gt;
&lt;P&gt;jgw&lt;/P&gt;</description>
      <pubDate>Thu, 18 Feb 2021 17:14:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257270#M20037</guid>
      <dc:creator>jgwohlbier</dc:creator>
      <dc:date>2021-02-18T17:14:56Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257277#M20039</link>
      <description>&lt;P&gt;Unfortunately I don't have any list you need but if I remember correctly only IFMA stands for INTOP count. The rest ISAs (or their subsets) stand for FLOP count. So you could compile the list based on data from &lt;A href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/#" target="_self"&gt;Intel Intrinsic Guide&lt;/A&gt; resource selecting needed ISA. BTW I'm not sure if Advisor supports IFMA yet&lt;/P&gt;</description>
      <pubDate>Thu, 18 Feb 2021 17:35:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257277#M20039</guid>
      <dc:creator>Ruslan_M_Intel</dc:creator>
      <dc:date>2021-02-18T17:35:45Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257528#M20043</link>
      <description>&lt;P&gt;Hi jgw,&lt;/P&gt;
&lt;P&gt;For Advisor GINTOPS you can find instructions list at Advisor Integer Roofline article:&amp;nbsp;&amp;nbsp;&lt;A href="https://software.intel.com/content/www/us/en/develop/articles/a-brief-overview-of-integer-roofline-modeling-in-intel-advisor.html" target="_blank" rel="noopener"&gt;https://software.intel.com/content/www/us/en/develop/articles/a-brief-overview-of-integer-roofline-modeling-in-intel-advisor.html&lt;/A&gt;&amp;nbsp;, &lt;STRONG&gt;quoted&lt;/STRONG&gt;:&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;Currently, ADD, ADC, SUB, MUL, IMUL, DIV, IDIV, INC/DEC, shifts, rotates etc. are counted as INT Operations. For strict integer operation usage, which allows you to exclude the loop counter operations (INC/DEC, shift, rotate) which are not strictly calculations, set the environment variable: ADVIXE_EXPERIMENTAL=intops_strict This will lead to only counting ADD, MUL, IDIV and SUB operations.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;FLOPS and GINTOPS are implemented so that for each instruction you multiply by operand SIMD width and taking into account (for AVX-512) mask register values. Also, for FMAs and for VNNI we count them as &amp;gt; 1 op (specifically, 2 for FMA). That's actually why we position Advisor FLOPS/INTOPS collectors as "&lt;EM&gt;Precise&lt;/EM&gt; FLOPS counting" analysis.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 19 Feb 2021 10:54:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1257528#M20043</guid>
      <dc:creator>Zakhar_M_Intel1</dc:creator>
      <dc:date>2021-02-19T10:54:32Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1259136#M20071</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you for accepting the solution. We are discontinuing monitoring this thread. Please raise a new thread in case of any further issues.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Raeesa&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 25 Feb 2021 04:28:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1259136#M20071</guid>
      <dc:creator>RaeesaM_Intel</dc:creator>
      <dc:date>2021-02-25T04:28:40Z</dc:date>
    </item>
    <item>
      <title>Re: Meaning of Intel Advisor GOPS</title>
      <link>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1259608#M20084</link>
      <description>&lt;P&gt;.. And (in continuation)&lt;/P&gt;
&lt;P&gt;For the &lt;STRONG&gt;FLOP&lt;/STRONG&gt;/S tool here is a high level list of classes of instructions counted:&lt;/P&gt;
&lt;P&gt;ADD, SUB, DIV, DP, MUL, ATAN, FPREM, TAN, SIN, COS, SQRT, SUB, RCP, RSQRT, EXP, VSCALE, MAX, MIN, ABS, IMUL, IDIV, FIDIVR, CMP, VREDUCE, VRND&lt;/P&gt;</description>
      <pubDate>Fri, 26 Feb 2021 07:39:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Meaning-of-Intel-Advisor-GOPS/m-p/1259608#M20084</guid>
      <dc:creator>Zakhar_M_Intel1</dc:creator>
      <dc:date>2021-02-26T07:39:33Z</dc:date>
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