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    <title>topic vtune error in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1416785#M22574</link>
    <description>&lt;P&gt;Pin: pin-3.22-98547-7a303a835&lt;BR /&gt;Copyright 2002-2020 Intel Corporation.&lt;BR /&gt;E: [tid:13968] SYSCALL_INSPECTOR: NTDLL module is rebased&lt;BR /&gt;A: C:\tmp_proj\pinjen\workspace\pypl-pin-nightly\GitPin\Source\pin\base_w\ipc_server_windows.cpp: LEVEL_BASE::StartServer: 1283: assertion failed: res == TRUE&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;i5 12450h&lt;/P&gt;
&lt;P&gt;windows 11 insider preview&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;and&lt;/P&gt;
&lt;P&gt;microarchitecture exploration shows weird result&lt;/P&gt;
&lt;P&gt;in task manager it use P-core,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;but vtune P-core summary all zero&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;vtune: Collection stopped.&lt;BR /&gt;vtune: Using result path `C:\Windows\System32\r001ue'&lt;BR /&gt;vtune: Executing actions 20 % Resolving information for `storqosflt.sys'&lt;BR /&gt;vtune: Warning: Finalization may slow down when loading files from the symbol server specified with the _NT_SYMBOL_PATH environment variable.&lt;BR /&gt;vtune: Executing actions 21 % Resolving information for `wdfilter.sys'&lt;BR /&gt;vtune: Warning: Cannot locate debugging information for file `c:\windows\system32\drivers\netwtw10.sys'.&lt;BR /&gt;vtune: Executing actions 22 % Resolving information for `wdfilter.sys'&lt;BR /&gt;vtune: Warning: Cannot locate debugging information for file `c:\windows\system32\drivers\wd\wdfilter.sys'.&lt;BR /&gt;vtune: Executing actions 75 % Generating a report Elapsed Time: 205.423s&lt;BR /&gt;Clockticks: 179,187,840,000&lt;BR /&gt;P-Core: 0&lt;BR /&gt;E-Core: 179,187,840,000&lt;BR /&gt;Instructions Retired: 421,282,368,000&lt;BR /&gt;P-Core: 0&lt;BR /&gt;E-Core: 421,282,368,000&lt;BR /&gt;CPI Rate: 0.425&lt;BR /&gt;P-Core: 0.000&lt;BR /&gt;E-Core: 0.425&lt;BR /&gt;MUX Reliability: 0.998&lt;BR /&gt;P-Core&lt;BR /&gt;Retiring: 0.0% of Pipeline Slots&lt;BR /&gt;Light Operations: 0.0% of Pipeline Slots&lt;BR /&gt;FP Arithmetic: 0.0% of uOps&lt;BR /&gt;FP x87: 0.0% of uOps&lt;BR /&gt;FP Scalar: 0.0% of uOps&lt;BR /&gt;FP Vector: 0.0% of uOps&lt;BR /&gt;Memory Operations: 0.0% of Pipeline Slots&lt;BR /&gt;Fused Instructions: 0.0% of Pipeline Slots&lt;BR /&gt;Non Fused Branches: 0.0% of Pipeline Slots&lt;BR /&gt;Nop Instructions: 0.0% of Pipeline Slots&lt;BR /&gt;Other: 0.0% of Pipeline Slots&lt;BR /&gt;Heavy Operations: 0.0% of Pipeline Slots&lt;BR /&gt;Microcode Sequencer: 0.0% of Pipeline Slots&lt;BR /&gt;Assists: 0.0% of Pipeline Slots&lt;BR /&gt;CISC: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Latency: 0.0% of Pipeline Slots&lt;BR /&gt;ICache Misses: 0.0% of Clockticks&lt;BR /&gt;ITLB Overhead: 0.0% of Clockticks&lt;BR /&gt;Branch Resteers: 0.0% of Clockticks&lt;BR /&gt;Mispredicts Resteers: 0.0% of Clockticks&lt;BR /&gt;Clears Resteers: 0.0% of Clockticks&lt;BR /&gt;Unknown Branches: 0.0% of Clockticks&lt;BR /&gt;DSB Switches: 0.0% of Clockticks&lt;BR /&gt;Length Changing Prefixes: 0.0% of Clockticks&lt;BR /&gt;MS Switches: 0.0% of Clockticks&lt;BR /&gt;Front-End Bandwidth: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth MITE: 0.0% of Pipeline Slots&lt;BR /&gt;Decoder-0 Alone: 0.0% of Clockticks&lt;BR /&gt;Front-End Bandwidth DSB: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth LSD: 0.0% of Pipeline Slots&lt;BR /&gt;(Info) DSB Coverage: 0.0%&lt;BR /&gt;(Info) LSD Coverage: 0.0%&lt;BR /&gt;(Info) DSB Misses Cost: 0.0% of Pipeline Slots&lt;BR /&gt;Bad Speculation: 100.0% of Pipeline Slots&lt;BR /&gt;| A significant proportion of pipeline slots containing useful work are&lt;BR /&gt;| being cancelled. This can be caused by mispredicting branches or by&lt;BR /&gt;| machine clears. Note that this metric value may be highlighted due to&lt;BR /&gt;| Branch Resteers issue.&lt;BR /&gt;|&lt;BR /&gt;Branch Mispredict: 0.0% of Pipeline Slots&lt;BR /&gt;Machine Clears: 100.0% of Pipeline Slots&lt;BR /&gt;| Issue: A significant portion of execution time is spent handling&lt;BR /&gt;| machine clears.&lt;BR /&gt;|&lt;BR /&gt;| Tips: See the "Memory Disambiguation" section in the Intel 64 and&lt;BR /&gt;| IA-32 Architectures Optimization Reference Manual.&lt;BR /&gt;|&lt;BR /&gt;Back-End Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Memory Bound: 0.0% of Pipeline Slots&lt;BR /&gt;L1 Bound: 0.0% of Clockticks&lt;BR /&gt;DTLB Overhead: 0.0% of Clockticks&lt;BR /&gt;Load STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Load STLB Miss: 0.0% of Clockticks&lt;BR /&gt;Loads Blocked by Store Forwarding: 0.0% of Clockticks&lt;BR /&gt;Lock Latency: 0.0% of Clockticks&lt;BR /&gt;Split Loads: 0.0% of Clockticks&lt;BR /&gt;FB Full: 0.0% of Clockticks&lt;BR /&gt;L2 Bound: 0.0% of Clockticks&lt;BR /&gt;L3 Bound: 0.0% of Clockticks&lt;BR /&gt;L3 Latency&lt;BR /&gt;SQ Full: 0.0% of Clockticks&lt;BR /&gt;DRAM Bound: 0.0% of Clockticks&lt;BR /&gt;Memory Bandwidth: 0.0% of Clockticks&lt;BR /&gt;Memory Latency: 0.0% of Clockticks&lt;BR /&gt;Store Bound: 0.0% of Clockticks&lt;BR /&gt;Store Latency: 0.0% of Clockticks&lt;BR /&gt;Split Stores: 0.0% of Clockticks&lt;BR /&gt;DTLB Store Overhead: 0.0% of Clockticks&lt;BR /&gt;Store STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Store STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Core Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Divider: 0.0% of Clockticks&lt;BR /&gt;Port Utilization: 0.0% of Clockticks&lt;BR /&gt;Cycles of 0 Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;Serializing Operations: 0.0% of Clockticks&lt;BR /&gt;Slow Pause: 0.0% of Clockticks&lt;BR /&gt;Memory Fence: 0.0% of Clockticks&lt;BR /&gt;Mixing Vectors: 0.0% of Clockticks&lt;BR /&gt;Cycles of 1 Port Utilized: 0.0% of Clockticks&lt;BR /&gt;Cycles of 2 Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;Cycles of 3+ Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;ALU Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;Port 0: 0.0% of Clockticks&lt;BR /&gt;Port 1: 0.0% of Clockticks&lt;BR /&gt;Port 6: 0.0% of Clockticks&lt;BR /&gt;Load Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;Store Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;E-Core&lt;BR /&gt;Retiring: 53.0% of Pipeline Slots&lt;BR /&gt;General Retirement: 51.4% of Pipeline Slots&lt;BR /&gt;FP Arithmetic: 0.1% of Pipeline Slots&lt;BR /&gt;Other: 51.3% of Pipeline Slots&lt;BR /&gt;Microcode Sequencer: 1.7% of Pipeline Slots&lt;BR /&gt;Front-End Bound: 14.1% of Pipeline Slots&lt;BR /&gt;Front-End Latency: 100.0% of Pipeline Slots&lt;BR /&gt;ICache Misses: 0.6% of Pipeline Slots&lt;BR /&gt;ITLB Overhead: 0.1% of Pipeline Slots&lt;BR /&gt;BACLEARS: 0.4% of Pipeline Slots&lt;BR /&gt;Branch Resteers: 100.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth: 56.0% of Pipeline Slots&lt;BR /&gt;Cisc: 2.6% of Pipeline Slots&lt;BR /&gt;Decode: 8.4% of Pipeline Slots&lt;BR /&gt;Pre-Decode Wrong: 0.1% of Pipeline Slots&lt;BR /&gt;Front-End Other: 44.9% of Pipeline Slots&lt;BR /&gt;Bad Speculation: 73.9% of Pipeline Slots&lt;BR /&gt;| A significant proportion of pipeline slots containing useful work are&lt;BR /&gt;| being cancelled. This can be caused by mispredicting branches or by&lt;BR /&gt;| machine clears. Note that this metric value may be highlighted due to&lt;BR /&gt;| Branch Resteers issue.&lt;BR /&gt;|&lt;BR /&gt;Branch Mispredict: 4.7% of Pipeline Slots&lt;BR /&gt;Machine Clears: 0.6% of Pipeline Slots&lt;BR /&gt;Machine Clear: 0.0% of Pipeline Slots&lt;BR /&gt;MO Machine Clear Overhead: 0.6% of Pipeline Slots&lt;BR /&gt;Back-End Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| A significant portion of pipeline slots are remaining empty. When&lt;BR /&gt;| operations take too long in the back-end, they introduce bubbles in&lt;BR /&gt;| the pipeline that ultimately cause fewer pipeline slots containing&lt;BR /&gt;| useful work to be retired per cycle than the machine is capable to&lt;BR /&gt;| support. This opportunity cost results in slower execution. Long-&lt;BR /&gt;| latency operations like divides and memory operations can cause this,&lt;BR /&gt;| as can too many operations being directed to a single execution port&lt;BR /&gt;| (for example, more multiply operations arriving in the back-end per&lt;BR /&gt;| cycle than the execution unit can support).&lt;BR /&gt;|&lt;BR /&gt;Resource Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| Resource Bound&lt;BR /&gt;|&lt;BR /&gt;Memory Scheduler: 2.9% of Pipeline Slots&lt;BR /&gt;Non-memory Scheduler: 41.9% of Pipeline Slots&lt;BR /&gt;| A significant percentage of issue slots were not consumed by&lt;BR /&gt;| the backend due to IEC and FPC RAT stalls. This can be caused&lt;BR /&gt;| by the FIQ and IEC reservation station stall (integer, FP and&lt;BR /&gt;| SIMD scheduler not able to accept another uop).&lt;BR /&gt;|&lt;BR /&gt;Register: 1.5% of Pipeline Slots&lt;BR /&gt;Full Re-order Buffer (ROB): 12.7% of Pipeline Slots&lt;BR /&gt;| A significant percentage of issue slots were not consumed by&lt;BR /&gt;| the backend due to ROB full.&lt;BR /&gt;|&lt;BR /&gt;Allocation Restriction: 1.6% of Pipeline Slots&lt;BR /&gt;Serializing Operations: 2.4% of Pipeline Slots&lt;BR /&gt;Alternative Back-End Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| A significant portion of pipeline slots are remaining empty. When&lt;BR /&gt;| operations take too long in the back-end, they introduce bubbles in&lt;BR /&gt;| the pipeline that ultimately cause fewer pipeline slots containing&lt;BR /&gt;| useful work to be retired per cycle than the machine is capable to&lt;BR /&gt;| support. This opportunity cost results in slower execution. Long-&lt;BR /&gt;| latency operations like divides and memory operations can cause this,&lt;BR /&gt;| as can too many operations being directed to a single execution port&lt;BR /&gt;| (for example, more multiply operations arriving in the back-end per&lt;BR /&gt;| cycle than the execution unit can support).&lt;BR /&gt;|&lt;BR /&gt;Core Bound: 0.0%&lt;BR /&gt;Memory Bound: 42.5%&lt;BR /&gt;| The metric value is high. This can indicate that the significant&lt;BR /&gt;| fraction of execution pipeline slots could be stalled due to&lt;BR /&gt;| demand memory load and stores. Use Memory Access analysis to have&lt;BR /&gt;| the metric breakdown by memory hierarchy, memory bandwidth&lt;BR /&gt;| information, correlation by memory objects.&lt;BR /&gt;|&lt;BR /&gt;L2 Bound: 2.3%&lt;BR /&gt;L3 Bound: 1.6%&lt;BR /&gt;DRAM Bound: 38.6%&lt;BR /&gt;| This metric shows how often CPU was stalled on the main&lt;BR /&gt;| memory (DRAM). Caching typically improves the latency and&lt;BR /&gt;| increases performance.&lt;BR /&gt;|&lt;BR /&gt;Average CPU Frequency: 3.249 GHz&lt;BR /&gt;Total Thread Count: 13&lt;BR /&gt;Paused Time: 0s&lt;BR /&gt;Effective Physical Core Utilization: 3.3% (0.266 out of &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;BR /&gt;| The metric value is low, which may signal a poor physical CPU cores&lt;BR /&gt;| utilization caused by:&lt;BR /&gt;| - load imbalance&lt;BR /&gt;| - threading runtime overhead&lt;BR /&gt;| - contended synchronization&lt;BR /&gt;| - thread/process underutilization&lt;BR /&gt;| - incorrect affinity that utilizes logical cores instead of physical&lt;BR /&gt;| cores&lt;BR /&gt;| Explore sub-metrics to estimate the efficiency of MPI and OpenMP parallelism&lt;BR /&gt;| or run the Locks and Waits analysis to identify parallel bottlenecks for&lt;BR /&gt;| other parallel runtimes.&lt;BR /&gt;|&lt;BR /&gt;Effective Logical Core Utilization: 2.2% (0.266 out of 12)&lt;BR /&gt;| The metric value is low, which may signal a poor logical CPU cores&lt;BR /&gt;| utilization. Consider improving physical core utilization as the first&lt;BR /&gt;| step and then look at opportunities to utilize logical cores, which in&lt;BR /&gt;| some cases can improve processor throughput and overall performance of&lt;BR /&gt;| multi-threaded applications.&lt;BR /&gt;|&lt;BR /&gt;Collection and Platform Info&lt;BR /&gt;Application Command Line: C:\Github\vvenc\bin\relwithdebinfo-static\vvencapp.exe "--preset" "slower" "-i" "akiyo_cif.y4m" "-o" "2.266" "-t" "12"&lt;BR /&gt;Operating System: Microsoft Windows 10&lt;BR /&gt;Computer Name:&amp;nbsp;&lt;BR /&gt;Result Size: 346.2 MB&lt;BR /&gt;Collection start time: 03:24:11 23/09/2022 UTC&lt;BR /&gt;Collection stop time: 03:27:36 23/09/2022 UTC&lt;BR /&gt;Collector Type: Event-based sampling driver&lt;BR /&gt;CPU&lt;BR /&gt;Name: Intel(R) microarchitecture code named Alderlake-P&lt;BR /&gt;Frequency: 2.496 GHz&lt;BR /&gt;Logical CPU Count: 12&lt;BR /&gt;Max DRAM Single-Package Bandwidth: 31.000 GB/s&lt;BR /&gt;Cache Allocation Technology&lt;BR /&gt;Level 2 capability: not detected&lt;BR /&gt;Level 3 capability: not detected&lt;/P&gt;
&lt;P&gt;If you want to skip descriptions of detected performance issues in the report,&lt;BR /&gt;enter: vtune -report summary -report-knob show-issues=false -r &amp;lt;my_result_dir&amp;gt;.&lt;BR /&gt;Alternatively, you may view the report in the csv format: vtune -report&lt;BR /&gt;&amp;lt;report_name&amp;gt; -format=csv.&lt;BR /&gt;vtune: Executing actions 100 % done&lt;/P&gt;
&lt;P&gt;C:\Windows\System32&amp;gt;cd C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe&lt;/P&gt;
&lt;P&gt;Usage: amplxe-sepreg.exe [ option ]&lt;/P&gt;
&lt;P&gt;where option is one of the following:&lt;/P&gt;
&lt;P&gt;-c | --check-dependencies&lt;BR /&gt;-i | --install-driver&lt;BR /&gt;-s | --status&lt;BR /&gt;-u [pax]| --uninstall-driver [pax]&lt;/P&gt;
&lt;P&gt;-v | --verbose may also be added to the above option for additional output&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -c&lt;BR /&gt;Checking platform...&lt;BR /&gt;Platform is genuine Intel: OK&lt;BR /&gt;Platform has SSE2: OK&lt;BR /&gt;Platform architecture: INTEL64&lt;BR /&gt;User has admin rights: OK&lt;BR /&gt;Drivers will be installed to C:\WINDOWS\System32\Drivers\&lt;BR /&gt;Checking sepdrv5 driver path...OK&lt;BR /&gt;Checking sepdrv5 service...&lt;BR /&gt;Driver status: the sepdrv5 service is running&lt;BR /&gt;Checking sepdal driver path...OK&lt;BR /&gt;Checking sepdal service...&lt;BR /&gt;Driver status: the sepdal service is running&lt;BR /&gt;Checking socperf3 driver path...OK&lt;BR /&gt;Checking socperf3 service...&lt;BR /&gt;Driver status: the socperf3 service is running&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -s&lt;BR /&gt;Checking sepdrv5 driver path...OK&lt;BR /&gt;Checking sepdrv5 service...&lt;BR /&gt;Driver status: the sepdrv5 service is running&lt;BR /&gt;Checking sepdal driver path...OK&lt;BR /&gt;Checking sepdal service...&lt;BR /&gt;Driver status: the sepdal service is running&lt;BR /&gt;Checking socperf3 driver path...OK&lt;BR /&gt;Checking socperf3 service...&lt;BR /&gt;Driver status: the socperf3 service is running&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -i&lt;BR /&gt;Warning, socperf3 driver is already installed and will be re-used... skipping&lt;BR /&gt;Installing and starting sepdrv5...&lt;BR /&gt;OK&lt;BR /&gt;Installing and starting sepdal...&lt;BR /&gt;OK&lt;BR /&gt;Installing and starting VTSS++ driver...FAILED&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;vtune-self-checker.bat&lt;BR /&gt;Intel(R) VTune(TM) Profiler Self Check Utility&lt;BR /&gt;Copyright (C) 2009 Intel Corporation. All rights reserved.&lt;BR /&gt;Build Number: 624050&lt;/P&gt;
&lt;P&gt;HW event-based analysis (counting mode) (Intel driver)&lt;BR /&gt;Example of analysis types: Performance Snapshot&lt;BR /&gt;Collection: Ok&lt;BR /&gt;Finalization: Ok...&lt;BR /&gt;Report: Ok&lt;/P&gt;</description>
    <pubDate>Fri, 23 Sep 2022 04:21:25 GMT</pubDate>
    <dc:creator>kakuyojiki</dc:creator>
    <dc:date>2022-09-23T04:21:25Z</dc:date>
    <item>
      <title>vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1416785#M22574</link>
      <description>&lt;P&gt;Pin: pin-3.22-98547-7a303a835&lt;BR /&gt;Copyright 2002-2020 Intel Corporation.&lt;BR /&gt;E: [tid:13968] SYSCALL_INSPECTOR: NTDLL module is rebased&lt;BR /&gt;A: C:\tmp_proj\pinjen\workspace\pypl-pin-nightly\GitPin\Source\pin\base_w\ipc_server_windows.cpp: LEVEL_BASE::StartServer: 1283: assertion failed: res == TRUE&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;i5 12450h&lt;/P&gt;
&lt;P&gt;windows 11 insider preview&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;and&lt;/P&gt;
&lt;P&gt;microarchitecture exploration shows weird result&lt;/P&gt;
&lt;P&gt;in task manager it use P-core,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;but vtune P-core summary all zero&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;vtune: Collection stopped.&lt;BR /&gt;vtune: Using result path `C:\Windows\System32\r001ue'&lt;BR /&gt;vtune: Executing actions 20 % Resolving information for `storqosflt.sys'&lt;BR /&gt;vtune: Warning: Finalization may slow down when loading files from the symbol server specified with the _NT_SYMBOL_PATH environment variable.&lt;BR /&gt;vtune: Executing actions 21 % Resolving information for `wdfilter.sys'&lt;BR /&gt;vtune: Warning: Cannot locate debugging information for file `c:\windows\system32\drivers\netwtw10.sys'.&lt;BR /&gt;vtune: Executing actions 22 % Resolving information for `wdfilter.sys'&lt;BR /&gt;vtune: Warning: Cannot locate debugging information for file `c:\windows\system32\drivers\wd\wdfilter.sys'.&lt;BR /&gt;vtune: Executing actions 75 % Generating a report Elapsed Time: 205.423s&lt;BR /&gt;Clockticks: 179,187,840,000&lt;BR /&gt;P-Core: 0&lt;BR /&gt;E-Core: 179,187,840,000&lt;BR /&gt;Instructions Retired: 421,282,368,000&lt;BR /&gt;P-Core: 0&lt;BR /&gt;E-Core: 421,282,368,000&lt;BR /&gt;CPI Rate: 0.425&lt;BR /&gt;P-Core: 0.000&lt;BR /&gt;E-Core: 0.425&lt;BR /&gt;MUX Reliability: 0.998&lt;BR /&gt;P-Core&lt;BR /&gt;Retiring: 0.0% of Pipeline Slots&lt;BR /&gt;Light Operations: 0.0% of Pipeline Slots&lt;BR /&gt;FP Arithmetic: 0.0% of uOps&lt;BR /&gt;FP x87: 0.0% of uOps&lt;BR /&gt;FP Scalar: 0.0% of uOps&lt;BR /&gt;FP Vector: 0.0% of uOps&lt;BR /&gt;Memory Operations: 0.0% of Pipeline Slots&lt;BR /&gt;Fused Instructions: 0.0% of Pipeline Slots&lt;BR /&gt;Non Fused Branches: 0.0% of Pipeline Slots&lt;BR /&gt;Nop Instructions: 0.0% of Pipeline Slots&lt;BR /&gt;Other: 0.0% of Pipeline Slots&lt;BR /&gt;Heavy Operations: 0.0% of Pipeline Slots&lt;BR /&gt;Microcode Sequencer: 0.0% of Pipeline Slots&lt;BR /&gt;Assists: 0.0% of Pipeline Slots&lt;BR /&gt;CISC: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Latency: 0.0% of Pipeline Slots&lt;BR /&gt;ICache Misses: 0.0% of Clockticks&lt;BR /&gt;ITLB Overhead: 0.0% of Clockticks&lt;BR /&gt;Branch Resteers: 0.0% of Clockticks&lt;BR /&gt;Mispredicts Resteers: 0.0% of Clockticks&lt;BR /&gt;Clears Resteers: 0.0% of Clockticks&lt;BR /&gt;Unknown Branches: 0.0% of Clockticks&lt;BR /&gt;DSB Switches: 0.0% of Clockticks&lt;BR /&gt;Length Changing Prefixes: 0.0% of Clockticks&lt;BR /&gt;MS Switches: 0.0% of Clockticks&lt;BR /&gt;Front-End Bandwidth: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth MITE: 0.0% of Pipeline Slots&lt;BR /&gt;Decoder-0 Alone: 0.0% of Clockticks&lt;BR /&gt;Front-End Bandwidth DSB: 0.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth LSD: 0.0% of Pipeline Slots&lt;BR /&gt;(Info) DSB Coverage: 0.0%&lt;BR /&gt;(Info) LSD Coverage: 0.0%&lt;BR /&gt;(Info) DSB Misses Cost: 0.0% of Pipeline Slots&lt;BR /&gt;Bad Speculation: 100.0% of Pipeline Slots&lt;BR /&gt;| A significant proportion of pipeline slots containing useful work are&lt;BR /&gt;| being cancelled. This can be caused by mispredicting branches or by&lt;BR /&gt;| machine clears. Note that this metric value may be highlighted due to&lt;BR /&gt;| Branch Resteers issue.&lt;BR /&gt;|&lt;BR /&gt;Branch Mispredict: 0.0% of Pipeline Slots&lt;BR /&gt;Machine Clears: 100.0% of Pipeline Slots&lt;BR /&gt;| Issue: A significant portion of execution time is spent handling&lt;BR /&gt;| machine clears.&lt;BR /&gt;|&lt;BR /&gt;| Tips: See the "Memory Disambiguation" section in the Intel 64 and&lt;BR /&gt;| IA-32 Architectures Optimization Reference Manual.&lt;BR /&gt;|&lt;BR /&gt;Back-End Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Memory Bound: 0.0% of Pipeline Slots&lt;BR /&gt;L1 Bound: 0.0% of Clockticks&lt;BR /&gt;DTLB Overhead: 0.0% of Clockticks&lt;BR /&gt;Load STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Load STLB Miss: 0.0% of Clockticks&lt;BR /&gt;Loads Blocked by Store Forwarding: 0.0% of Clockticks&lt;BR /&gt;Lock Latency: 0.0% of Clockticks&lt;BR /&gt;Split Loads: 0.0% of Clockticks&lt;BR /&gt;FB Full: 0.0% of Clockticks&lt;BR /&gt;L2 Bound: 0.0% of Clockticks&lt;BR /&gt;L3 Bound: 0.0% of Clockticks&lt;BR /&gt;L3 Latency&lt;BR /&gt;SQ Full: 0.0% of Clockticks&lt;BR /&gt;DRAM Bound: 0.0% of Clockticks&lt;BR /&gt;Memory Bandwidth: 0.0% of Clockticks&lt;BR /&gt;Memory Latency: 0.0% of Clockticks&lt;BR /&gt;Store Bound: 0.0% of Clockticks&lt;BR /&gt;Store Latency: 0.0% of Clockticks&lt;BR /&gt;Split Stores: 0.0% of Clockticks&lt;BR /&gt;DTLB Store Overhead: 0.0% of Clockticks&lt;BR /&gt;Store STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Store STLB Hit: 0.0% of Clockticks&lt;BR /&gt;Core Bound: 0.0% of Pipeline Slots&lt;BR /&gt;Divider: 0.0% of Clockticks&lt;BR /&gt;Port Utilization: 0.0% of Clockticks&lt;BR /&gt;Cycles of 0 Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;Serializing Operations: 0.0% of Clockticks&lt;BR /&gt;Slow Pause: 0.0% of Clockticks&lt;BR /&gt;Memory Fence: 0.0% of Clockticks&lt;BR /&gt;Mixing Vectors: 0.0% of Clockticks&lt;BR /&gt;Cycles of 1 Port Utilized: 0.0% of Clockticks&lt;BR /&gt;Cycles of 2 Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;Cycles of 3+ Ports Utilized: 0.0% of Clockticks&lt;BR /&gt;ALU Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;Port 0: 0.0% of Clockticks&lt;BR /&gt;Port 1: 0.0% of Clockticks&lt;BR /&gt;Port 6: 0.0% of Clockticks&lt;BR /&gt;Load Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;Store Operation Utilization: 0.0% of Clockticks&lt;BR /&gt;E-Core&lt;BR /&gt;Retiring: 53.0% of Pipeline Slots&lt;BR /&gt;General Retirement: 51.4% of Pipeline Slots&lt;BR /&gt;FP Arithmetic: 0.1% of Pipeline Slots&lt;BR /&gt;Other: 51.3% of Pipeline Slots&lt;BR /&gt;Microcode Sequencer: 1.7% of Pipeline Slots&lt;BR /&gt;Front-End Bound: 14.1% of Pipeline Slots&lt;BR /&gt;Front-End Latency: 100.0% of Pipeline Slots&lt;BR /&gt;ICache Misses: 0.6% of Pipeline Slots&lt;BR /&gt;ITLB Overhead: 0.1% of Pipeline Slots&lt;BR /&gt;BACLEARS: 0.4% of Pipeline Slots&lt;BR /&gt;Branch Resteers: 100.0% of Pipeline Slots&lt;BR /&gt;Front-End Bandwidth: 56.0% of Pipeline Slots&lt;BR /&gt;Cisc: 2.6% of Pipeline Slots&lt;BR /&gt;Decode: 8.4% of Pipeline Slots&lt;BR /&gt;Pre-Decode Wrong: 0.1% of Pipeline Slots&lt;BR /&gt;Front-End Other: 44.9% of Pipeline Slots&lt;BR /&gt;Bad Speculation: 73.9% of Pipeline Slots&lt;BR /&gt;| A significant proportion of pipeline slots containing useful work are&lt;BR /&gt;| being cancelled. This can be caused by mispredicting branches or by&lt;BR /&gt;| machine clears. Note that this metric value may be highlighted due to&lt;BR /&gt;| Branch Resteers issue.&lt;BR /&gt;|&lt;BR /&gt;Branch Mispredict: 4.7% of Pipeline Slots&lt;BR /&gt;Machine Clears: 0.6% of Pipeline Slots&lt;BR /&gt;Machine Clear: 0.0% of Pipeline Slots&lt;BR /&gt;MO Machine Clear Overhead: 0.6% of Pipeline Slots&lt;BR /&gt;Back-End Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| A significant portion of pipeline slots are remaining empty. When&lt;BR /&gt;| operations take too long in the back-end, they introduce bubbles in&lt;BR /&gt;| the pipeline that ultimately cause fewer pipeline slots containing&lt;BR /&gt;| useful work to be retired per cycle than the machine is capable to&lt;BR /&gt;| support. This opportunity cost results in slower execution. Long-&lt;BR /&gt;| latency operations like divides and memory operations can cause this,&lt;BR /&gt;| as can too many operations being directed to a single execution port&lt;BR /&gt;| (for example, more multiply operations arriving in the back-end per&lt;BR /&gt;| cycle than the execution unit can support).&lt;BR /&gt;|&lt;BR /&gt;Resource Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| Resource Bound&lt;BR /&gt;|&lt;BR /&gt;Memory Scheduler: 2.9% of Pipeline Slots&lt;BR /&gt;Non-memory Scheduler: 41.9% of Pipeline Slots&lt;BR /&gt;| A significant percentage of issue slots were not consumed by&lt;BR /&gt;| the backend due to IEC and FPC RAT stalls. This can be caused&lt;BR /&gt;| by the FIQ and IEC reservation station stall (integer, FP and&lt;BR /&gt;| SIMD scheduler not able to accept another uop).&lt;BR /&gt;|&lt;BR /&gt;Register: 1.5% of Pipeline Slots&lt;BR /&gt;Full Re-order Buffer (ROB): 12.7% of Pipeline Slots&lt;BR /&gt;| A significant percentage of issue slots were not consumed by&lt;BR /&gt;| the backend due to ROB full.&lt;BR /&gt;|&lt;BR /&gt;Allocation Restriction: 1.6% of Pipeline Slots&lt;BR /&gt;Serializing Operations: 2.4% of Pipeline Slots&lt;BR /&gt;Alternative Back-End Bound: 26.6% of Pipeline Slots&lt;BR /&gt;| A significant portion of pipeline slots are remaining empty. When&lt;BR /&gt;| operations take too long in the back-end, they introduce bubbles in&lt;BR /&gt;| the pipeline that ultimately cause fewer pipeline slots containing&lt;BR /&gt;| useful work to be retired per cycle than the machine is capable to&lt;BR /&gt;| support. This opportunity cost results in slower execution. Long-&lt;BR /&gt;| latency operations like divides and memory operations can cause this,&lt;BR /&gt;| as can too many operations being directed to a single execution port&lt;BR /&gt;| (for example, more multiply operations arriving in the back-end per&lt;BR /&gt;| cycle than the execution unit can support).&lt;BR /&gt;|&lt;BR /&gt;Core Bound: 0.0%&lt;BR /&gt;Memory Bound: 42.5%&lt;BR /&gt;| The metric value is high. This can indicate that the significant&lt;BR /&gt;| fraction of execution pipeline slots could be stalled due to&lt;BR /&gt;| demand memory load and stores. Use Memory Access analysis to have&lt;BR /&gt;| the metric breakdown by memory hierarchy, memory bandwidth&lt;BR /&gt;| information, correlation by memory objects.&lt;BR /&gt;|&lt;BR /&gt;L2 Bound: 2.3%&lt;BR /&gt;L3 Bound: 1.6%&lt;BR /&gt;DRAM Bound: 38.6%&lt;BR /&gt;| This metric shows how often CPU was stalled on the main&lt;BR /&gt;| memory (DRAM). Caching typically improves the latency and&lt;BR /&gt;| increases performance.&lt;BR /&gt;|&lt;BR /&gt;Average CPU Frequency: 3.249 GHz&lt;BR /&gt;Total Thread Count: 13&lt;BR /&gt;Paused Time: 0s&lt;BR /&gt;Effective Physical Core Utilization: 3.3% (0.266 out of &lt;LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"&gt;&lt;/LI-EMOJI&gt;&lt;BR /&gt;| The metric value is low, which may signal a poor physical CPU cores&lt;BR /&gt;| utilization caused by:&lt;BR /&gt;| - load imbalance&lt;BR /&gt;| - threading runtime overhead&lt;BR /&gt;| - contended synchronization&lt;BR /&gt;| - thread/process underutilization&lt;BR /&gt;| - incorrect affinity that utilizes logical cores instead of physical&lt;BR /&gt;| cores&lt;BR /&gt;| Explore sub-metrics to estimate the efficiency of MPI and OpenMP parallelism&lt;BR /&gt;| or run the Locks and Waits analysis to identify parallel bottlenecks for&lt;BR /&gt;| other parallel runtimes.&lt;BR /&gt;|&lt;BR /&gt;Effective Logical Core Utilization: 2.2% (0.266 out of 12)&lt;BR /&gt;| The metric value is low, which may signal a poor logical CPU cores&lt;BR /&gt;| utilization. Consider improving physical core utilization as the first&lt;BR /&gt;| step and then look at opportunities to utilize logical cores, which in&lt;BR /&gt;| some cases can improve processor throughput and overall performance of&lt;BR /&gt;| multi-threaded applications.&lt;BR /&gt;|&lt;BR /&gt;Collection and Platform Info&lt;BR /&gt;Application Command Line: C:\Github\vvenc\bin\relwithdebinfo-static\vvencapp.exe "--preset" "slower" "-i" "akiyo_cif.y4m" "-o" "2.266" "-t" "12"&lt;BR /&gt;Operating System: Microsoft Windows 10&lt;BR /&gt;Computer Name:&amp;nbsp;&lt;BR /&gt;Result Size: 346.2 MB&lt;BR /&gt;Collection start time: 03:24:11 23/09/2022 UTC&lt;BR /&gt;Collection stop time: 03:27:36 23/09/2022 UTC&lt;BR /&gt;Collector Type: Event-based sampling driver&lt;BR /&gt;CPU&lt;BR /&gt;Name: Intel(R) microarchitecture code named Alderlake-P&lt;BR /&gt;Frequency: 2.496 GHz&lt;BR /&gt;Logical CPU Count: 12&lt;BR /&gt;Max DRAM Single-Package Bandwidth: 31.000 GB/s&lt;BR /&gt;Cache Allocation Technology&lt;BR /&gt;Level 2 capability: not detected&lt;BR /&gt;Level 3 capability: not detected&lt;/P&gt;
&lt;P&gt;If you want to skip descriptions of detected performance issues in the report,&lt;BR /&gt;enter: vtune -report summary -report-knob show-issues=false -r &amp;lt;my_result_dir&amp;gt;.&lt;BR /&gt;Alternatively, you may view the report in the csv format: vtune -report&lt;BR /&gt;&amp;lt;report_name&amp;gt; -format=csv.&lt;BR /&gt;vtune: Executing actions 100 % done&lt;/P&gt;
&lt;P&gt;C:\Windows\System32&amp;gt;cd C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe&lt;/P&gt;
&lt;P&gt;Usage: amplxe-sepreg.exe [ option ]&lt;/P&gt;
&lt;P&gt;where option is one of the following:&lt;/P&gt;
&lt;P&gt;-c | --check-dependencies&lt;BR /&gt;-i | --install-driver&lt;BR /&gt;-s | --status&lt;BR /&gt;-u [pax]| --uninstall-driver [pax]&lt;/P&gt;
&lt;P&gt;-v | --verbose may also be added to the above option for additional output&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -c&lt;BR /&gt;Checking platform...&lt;BR /&gt;Platform is genuine Intel: OK&lt;BR /&gt;Platform has SSE2: OK&lt;BR /&gt;Platform architecture: INTEL64&lt;BR /&gt;User has admin rights: OK&lt;BR /&gt;Drivers will be installed to C:\WINDOWS\System32\Drivers\&lt;BR /&gt;Checking sepdrv5 driver path...OK&lt;BR /&gt;Checking sepdrv5 service...&lt;BR /&gt;Driver status: the sepdrv5 service is running&lt;BR /&gt;Checking sepdal driver path...OK&lt;BR /&gt;Checking sepdal service...&lt;BR /&gt;Driver status: the sepdal service is running&lt;BR /&gt;Checking socperf3 driver path...OK&lt;BR /&gt;Checking socperf3 service...&lt;BR /&gt;Driver status: the socperf3 service is running&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -s&lt;BR /&gt;Checking sepdrv5 driver path...OK&lt;BR /&gt;Checking sepdrv5 service...&lt;BR /&gt;Driver status: the sepdrv5 service is running&lt;BR /&gt;Checking sepdal driver path...OK&lt;BR /&gt;Checking sepdal service...&lt;BR /&gt;Driver status: the sepdal service is running&lt;BR /&gt;Checking socperf3 driver path...OK&lt;BR /&gt;Checking socperf3 service...&lt;BR /&gt;Driver status: the socperf3 service is running&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;amplxe-sepreg.exe -i&lt;BR /&gt;Warning, socperf3 driver is already installed and will be re-used... skipping&lt;BR /&gt;Installing and starting sepdrv5...&lt;BR /&gt;OK&lt;BR /&gt;Installing and starting sepdal...&lt;BR /&gt;OK&lt;BR /&gt;Installing and starting VTSS++ driver...FAILED&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;vtune-self-checker.bat&lt;BR /&gt;Intel(R) VTune(TM) Profiler Self Check Utility&lt;BR /&gt;Copyright (C) 2009 Intel Corporation. All rights reserved.&lt;BR /&gt;Build Number: 624050&lt;/P&gt;
&lt;P&gt;HW event-based analysis (counting mode) (Intel driver)&lt;BR /&gt;Example of analysis types: Performance Snapshot&lt;BR /&gt;Collection: Ok&lt;BR /&gt;Finalization: Ok...&lt;BR /&gt;Report: Ok&lt;/P&gt;</description>
      <pubDate>Fri, 23 Sep 2022 04:21:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1416785#M22574</guid>
      <dc:creator>kakuyojiki</dc:creator>
      <dc:date>2022-09-23T04:21:25Z</dc:date>
    </item>
    <item>
      <title>Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417293#M22577</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thank you for posting in Intel Communities.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Please attach complete self checker logs.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Shyam Sundar&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 26 Sep 2022 10:57:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417293#M22577</guid>
      <dc:creator>ShyamS_Intel</dc:creator>
      <dc:date>2022-09-26T10:57:17Z</dc:date>
    </item>
    <item>
      <title>Re: Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417336#M22578</link>
      <description>&lt;P&gt;its stuck&lt;/P&gt;
&lt;P&gt;Microsoft Windows [Version 10.0.25206.1000]&lt;BR /&gt;(c) Microsoft Corporation. All rights reserved.&lt;/P&gt;
&lt;P&gt;C:\Windows\System32&amp;gt;cd "C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64"&lt;/P&gt;
&lt;P&gt;C:\Program Files (x86)\Intel\oneAPI\vtune\2022.3.0\bin64&amp;gt;vtune-self-checker.bat&lt;BR /&gt;Intel(R) VTune(TM) Profiler Self Check Utility&lt;BR /&gt;Copyright (C) 2009 Intel Corporation. All rights reserved.&lt;BR /&gt;Build Number: 624050&lt;/P&gt;
&lt;P&gt;HW event-based analysis (counting mode) (Intel driver)&lt;BR /&gt;Example of analysis types: Performance Snapshot&lt;BR /&gt;Collection: Ok&lt;BR /&gt;Finalization: Ok...&lt;BR /&gt;Report: Ok&lt;/P&gt;
&lt;P&gt;Instrumentation based analysis check...&lt;/P&gt;</description>
      <pubDate>Mon, 26 Sep 2022 14:32:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417336#M22578</guid>
      <dc:creator>kakuyojiki</dc:creator>
      <dc:date>2022-09-26T14:32:57Z</dc:date>
    </item>
    <item>
      <title>Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417629#M22590</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Could you please provide sample reproducer and commands which you tried, so that we can try it from our end&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Shyam Sundar&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 27 Sep 2022 10:51:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1417629#M22590</guid>
      <dc:creator>ShyamS_Intel</dc:creator>
      <dc:date>2022-09-27T10:51:21Z</dc:date>
    </item>
    <item>
      <title>Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419650#M22603</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Could you please provide us an update.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Shyam Sundar&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 05 Oct 2022 09:20:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419650#M22603</guid>
      <dc:creator>ShyamS_Intel</dc:creator>
      <dc:date>2022-10-05T09:20:33Z</dc:date>
    </item>
    <item>
      <title>Re: Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419927#M22604</link>
      <description>&lt;P&gt;for now im not use vtune at all&lt;/P&gt;</description>
      <pubDate>Thu, 06 Oct 2022 07:32:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419927#M22604</guid>
      <dc:creator>kakuyojiki</dc:creator>
      <dc:date>2022-10-06T07:32:21Z</dc:date>
    </item>
    <item>
      <title>Re: vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419952#M22606</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Sorry for the inconvenience caused. To assist you better, can you try running the VTune matrix multiplication sample as per the below steps in CLI:&lt;/P&gt;
&lt;P&gt;vtune -collect &amp;lt;-action&amp;gt; &amp;lt;target&amp;gt; &lt;/P&gt;
&lt;P&gt;Please refer documentation if needed: &lt;A href="https://www.intel.com/content/www/us/en/develop/documentation/vtune-help/top/command-line-interface.html" target="_blank" rel="noopener"&gt;https://www.intel.com/content/www/us/en/develop/documentation/vtune-help/top/command-line-interface.html &lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Since, you mentioned that you are not using Intel VTune Profiler now. Do let us know if we can stop monitoring this thread.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Shyam Sundar&lt;/P&gt;</description>
      <pubDate>Thu, 06 Oct 2022 11:34:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1419952#M22606</guid>
      <dc:creator>ShyamS_Intel</dc:creator>
      <dc:date>2022-10-06T11:34:23Z</dc:date>
    </item>
    <item>
      <title>Re:vtune error</title>
      <link>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1421376#M22613</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;I assume that your issue is resolved. If you need any additional information, please post a new question as this thread will no longer be monitored by Intel.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Shyam Sundar&lt;/P&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 12 Oct 2022 14:32:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/vtune-error/m-p/1421376#M22613</guid>
      <dc:creator>ShyamS_Intel</dc:creator>
      <dc:date>2022-10-12T14:32:32Z</dc:date>
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