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    <title>topic compare two FIFO implementation in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/compare-two-FIFO-implementation/m-p/855026#M3151</link>
    <description>see the single-producer/single consumer FIFO code below,seems code1 is compact,and only have 1 if-else branch.&lt;BR /&gt;&lt;BR /&gt;time: the former cost about avg. 160ns per insert (by clock_gettime) latter cost about 20 ns per insert(surprised me! ).&lt;BR /&gt;the CPI result:former is about 30,latter is about 8.&lt;BR /&gt;&lt;BR /&gt;I don't check other events&lt;BR /&gt;&lt;BR /&gt;the reason might be the code1 has an expensive insruct "div",but how to prove it?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;code1:&lt;BR /&gt;&lt;BR /&gt;bool insert( const T &amp;amp;rtItem )&lt;BR /&gt;{ &lt;BR /&gt;uint32_t ww = (uint32_t) atomic_read( &amp;amp;w );&lt;BR /&gt;uint32_t rr = (uint32_t) atomic_read( &amp;amp;r );&lt;BR /&gt;&lt;BR /&gt;if (predict_true(ww - rr != size))&lt;BR /&gt;{&lt;BR /&gt;f[ ww % size ] = rtItem;&lt;BR /&gt;atomic_inc( &amp;amp;w ); &lt;BR /&gt;return true;&lt;BR /&gt;}&lt;BR /&gt;return false;&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/////////////////////&lt;BR /&gt;code2:&lt;BR /&gt;bool insert( const T &amp;amp;rtItem )&lt;BR /&gt;{&lt;BR /&gt;uint32_t nw;&lt;BR /&gt;bool tRet = false;&lt;BR /&gt;uint32_t ww = (uint32_t) atomic_read( &amp;amp;w );&lt;BR /&gt;uint32_t rr = (uint32_t) atomic_read( &amp;amp;r );&lt;BR /&gt;&lt;BR /&gt;if ( predict_true( ( ww + 1 ) &amp;lt; size ) )&lt;BR /&gt;nw = ww + 1;&lt;BR /&gt;else&lt;BR /&gt;nw = 0;&lt;BR /&gt;&lt;BR /&gt;if ( predict_true( nw != rr ) )&lt;BR /&gt;{&lt;BR /&gt;f[ ww ] = rtItem;&lt;BR /&gt;atomic_set( &amp;amp;w, nw );&lt;BR /&gt;tRet = true;&lt;BR /&gt;}&lt;BR /&gt;return tRet;&lt;BR /&gt;}</description>
    <pubDate>Wed, 23 Dec 2009 09:15:15 GMT</pubDate>
    <dc:creator>softarts</dc:creator>
    <dc:date>2009-12-23T09:15:15Z</dc:date>
    <item>
      <title>compare two FIFO implementation</title>
      <link>https://community.intel.com/t5/Analyzers/compare-two-FIFO-implementation/m-p/855026#M3151</link>
      <description>see the single-producer/single consumer FIFO code below,seems code1 is compact,and only have 1 if-else branch.&lt;BR /&gt;&lt;BR /&gt;time: the former cost about avg. 160ns per insert (by clock_gettime) latter cost about 20 ns per insert(surprised me! ).&lt;BR /&gt;the CPI result:former is about 30,latter is about 8.&lt;BR /&gt;&lt;BR /&gt;I don't check other events&lt;BR /&gt;&lt;BR /&gt;the reason might be the code1 has an expensive insruct "div",but how to prove it?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;code1:&lt;BR /&gt;&lt;BR /&gt;bool insert( const T &amp;amp;rtItem )&lt;BR /&gt;{ &lt;BR /&gt;uint32_t ww = (uint32_t) atomic_read( &amp;amp;w );&lt;BR /&gt;uint32_t rr = (uint32_t) atomic_read( &amp;amp;r );&lt;BR /&gt;&lt;BR /&gt;if (predict_true(ww - rr != size))&lt;BR /&gt;{&lt;BR /&gt;f[ ww % size ] = rtItem;&lt;BR /&gt;atomic_inc( &amp;amp;w ); &lt;BR /&gt;return true;&lt;BR /&gt;}&lt;BR /&gt;return false;&lt;BR /&gt;}&lt;BR /&gt;&lt;BR /&gt;/////////////////////&lt;BR /&gt;code2:&lt;BR /&gt;bool insert( const T &amp;amp;rtItem )&lt;BR /&gt;{&lt;BR /&gt;uint32_t nw;&lt;BR /&gt;bool tRet = false;&lt;BR /&gt;uint32_t ww = (uint32_t) atomic_read( &amp;amp;w );&lt;BR /&gt;uint32_t rr = (uint32_t) atomic_read( &amp;amp;r );&lt;BR /&gt;&lt;BR /&gt;if ( predict_true( ( ww + 1 ) &amp;lt; size ) )&lt;BR /&gt;nw = ww + 1;&lt;BR /&gt;else&lt;BR /&gt;nw = 0;&lt;BR /&gt;&lt;BR /&gt;if ( predict_true( nw != rr ) )&lt;BR /&gt;{&lt;BR /&gt;f[ ww ] = rtItem;&lt;BR /&gt;atomic_set( &amp;amp;w, nw );&lt;BR /&gt;tRet = true;&lt;BR /&gt;}&lt;BR /&gt;return tRet;&lt;BR /&gt;}</description>
      <pubDate>Wed, 23 Dec 2009 09:15:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/compare-two-FIFO-implementation/m-p/855026#M3151</guid>
      <dc:creator>softarts</dc:creator>
      <dc:date>2009-12-23T09:15:15Z</dc:date>
    </item>
    <item>
      <title>Re: compare two FIFO implementation</title>
      <link>https://community.intel.com/t5/Analyzers/compare-two-FIFO-implementation/m-p/855027#M3152</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/327239"&gt;softarts&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;the reason might be the code1 has an expensive insruct "div",but how to prove it?&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;SPAN style="font-family: verdana, sans-serif;"&gt;Look a the cycle count event distribution over the code (disassembly view would be more useful). You can find out which instruction or group of instructions cost the most clock ticks. &lt;/SPAN&gt;</description>
      <pubDate>Wed, 23 Dec 2009 14:25:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/compare-two-FIFO-implementation/m-p/855027#M3152</guid>
      <dc:creator>Vladimir_T_Intel</dc:creator>
      <dc:date>2009-12-23T14:25:15Z</dc:date>
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