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    <title>topic Re: Question on Main Memory DRAM Address Translation in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/Question-on-Main-Memory-DRAM-Address-Translation/m-p/869412#M3764</link>
    <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/328639"&gt;zhangyihere&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;Hi, all!&lt;BR /&gt;&lt;BR /&gt;I want to do some test and I have to figure out which address will be mapped onto which memory bank? I am using processor Core 2 and the chipset is 82Q965. I have read the datasheet of 82Q965, chapter 10.2 System Memory Controller. Therein I could find the address translation in a chip, but I can't findhow doesaddress betranslated between chips in a rank? Where could I find the answer?&lt;BR /&gt;&lt;BR /&gt;Please give me some help or any literatures I could refer to.&lt;BR /&gt;&lt;BR /&gt;Many thanks!&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;P class="MsoPlainText"&gt;I'm not sure this is the right forum for such question as non of the software tools would provide you with such measurement.&lt;/P&gt;</description>
    <pubDate>Wed, 09 Dec 2009 12:59:23 GMT</pubDate>
    <dc:creator>Vladimir_T_Intel</dc:creator>
    <dc:date>2009-12-09T12:59:23Z</dc:date>
    <item>
      <title>Question on Main Memory DRAM Address Translation</title>
      <link>https://community.intel.com/t5/Analyzers/Question-on-Main-Memory-DRAM-Address-Translation/m-p/869411#M3763</link>
      <description>Hi, all!&lt;BR /&gt;&lt;BR /&gt;I want to do some test and I have to figure out which address will be mapped onto which memory bank? I am using processor Core 2 and the chipset is 82Q965. I have read the datasheet of 82Q965, chapter 10.2 System Memory Controller. Therein I could find the address translation in a chip, but I can't findhow doesaddress betranslated between chips in a rank? Where could I find the answer?&lt;BR /&gt;&lt;BR /&gt;Please give me some help or any literatures I could refer to.&lt;BR /&gt;&lt;BR /&gt;Many thanks!&lt;BR /&gt;</description>
      <pubDate>Fri, 04 Dec 2009 13:13:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Question-on-Main-Memory-DRAM-Address-Translation/m-p/869411#M3763</guid>
      <dc:creator>zhangyihere</dc:creator>
      <dc:date>2009-12-04T13:13:42Z</dc:date>
    </item>
    <item>
      <title>Re: Question on Main Memory DRAM Address Translation</title>
      <link>https://community.intel.com/t5/Analyzers/Question-on-Main-Memory-DRAM-Address-Translation/m-p/869412#M3764</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/328639"&gt;zhangyihere&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;Hi, all!&lt;BR /&gt;&lt;BR /&gt;I want to do some test and I have to figure out which address will be mapped onto which memory bank? I am using processor Core 2 and the chipset is 82Q965. I have read the datasheet of 82Q965, chapter 10.2 System Memory Controller. Therein I could find the address translation in a chip, but I can't findhow doesaddress betranslated between chips in a rank? Where could I find the answer?&lt;BR /&gt;&lt;BR /&gt;Please give me some help or any literatures I could refer to.&lt;BR /&gt;&lt;BR /&gt;Many thanks!&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;P class="MsoPlainText"&gt;I'm not sure this is the right forum for such question as non of the software tools would provide you with such measurement.&lt;/P&gt;</description>
      <pubDate>Wed, 09 Dec 2009 12:59:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/Question-on-Main-Memory-DRAM-Address-Translation/m-p/869412#M3764</guid>
      <dc:creator>Vladimir_T_Intel</dc:creator>
      <dc:date>2009-12-09T12:59:23Z</dc:date>
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