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    <title>topic Re: How to decrease very poor CPI (above 7)? in Analyzers</title>
    <link>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952289#M8136</link>
    <description>I will guess that the reason for bad cache behavior in Z direction is a stride too large for hardware prefetch to work (assuming you use a platform with hardware prefetch, such as P4).&lt;BR /&gt;If software prefetching is to be useful, it may have to be much further ahead, using non-temporal hints, if you have a CPU where that makes a difference.  You have to consider how many CPU cycles are required to resolve a miss, and how many loop iterations correspond to that.&lt;BR /&gt;Since you are posting in the VTune forum, we might ask for more detail on what VTune says about the influence of L1, L2, and DTLB misses.&lt;BR /&gt;If you can organize your Z filtering so that several X values are filtered in the same inner loop, you may be able to cut down the number of misses significantly.  This could be a useful form of cache blocking.&lt;BR /&gt;In data base applications on HyperThreaded CPUs, the standard technique for mitigating TLB misses is to thread the application, so that one thread can progress while the other is stalled on TLB miss.  If you think this is not a clean way to operate, I will not argue against you.</description>
    <pubDate>Mon, 09 Jan 2006 22:24:48 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2006-01-09T22:24:48Z</dc:date>
    <item>
      <title>How to decrease very poor CPI (above 7)?</title>
      <link>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952288#M8135</link>
      <description>I am doing 3D gauss filtering (filter size 5) using SSE. Filtering in X or Y direction gives CPI about 1.2, but filtering in the Z direction gives CPI above 7. I supposed that the reason was due to cache misses and bigger addressing stride between filtered values when filtering in Z direction. So I interleaved the calculation with prefetching but it did not help. Can prefetching really help in this case? If yes, how far should be prefetched (is it suffiecient to prefetch one or two loop iterations ahead)?&lt;BR /&gt;Please, tell me how can I decrease this terrible result.</description>
      <pubDate>Mon, 09 Jan 2006 20:42:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952288#M8135</guid>
      <dc:creator>vasko_anton</dc:creator>
      <dc:date>2006-01-09T20:42:03Z</dc:date>
    </item>
    <item>
      <title>Re: How to decrease very poor CPI (above 7)?</title>
      <link>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952289#M8136</link>
      <description>I will guess that the reason for bad cache behavior in Z direction is a stride too large for hardware prefetch to work (assuming you use a platform with hardware prefetch, such as P4).&lt;BR /&gt;If software prefetching is to be useful, it may have to be much further ahead, using non-temporal hints, if you have a CPU where that makes a difference.  You have to consider how many CPU cycles are required to resolve a miss, and how many loop iterations correspond to that.&lt;BR /&gt;Since you are posting in the VTune forum, we might ask for more detail on what VTune says about the influence of L1, L2, and DTLB misses.&lt;BR /&gt;If you can organize your Z filtering so that several X values are filtered in the same inner loop, you may be able to cut down the number of misses significantly.  This could be a useful form of cache blocking.&lt;BR /&gt;In data base applications on HyperThreaded CPUs, the standard technique for mitigating TLB misses is to thread the application, so that one thread can progress while the other is stalled on TLB miss.  If you think this is not a clean way to operate, I will not argue against you.</description>
      <pubDate>Mon, 09 Jan 2006 22:24:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952289#M8136</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2006-01-09T22:24:48Z</dc:date>
    </item>
    <item>
      <title>Re: How to decrease very poor CPI (above 7)?</title>
      <link>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952290#M8137</link>
      <description>The code (snipet) responsible for poor CPI and cache misses:&lt;BR /&gt;&lt;BR /&gt;; edx=stride&lt;BR /&gt;; eax=3*edx&lt;BR /&gt;; xmm0-xmm2 are coefficients&lt;BR /&gt;align 16&lt;BR /&gt;.Label&lt;BR /&gt;	movaps	xmm3,[esi]&lt;BR /&gt;	movaps	xmm4,[esi + edx]&lt;BR /&gt;	movaps	xmm5,[esi +2* edx]&lt;BR /&gt;	movaps	xmm6,[esi + eax]&lt;BR /&gt;	movaps	xmm7,[esi +4* edx]&lt;BR /&gt;	&lt;BR /&gt;	addps	xmm4,xmm6	; gaussian is symmetric &lt;BR /&gt;	addps	xmm3,xmm6	; &lt;BR /&gt;	&lt;BR /&gt;	mulps	xmm5,xmm2&lt;BR /&gt;	mulps	xmm4,xmm1&lt;BR /&gt;	mulps	xmm3,xmm0&lt;BR /&gt;	&lt;BR /&gt;	prefetchnta [esi]&lt;BR /&gt;	prefetchnta [esi + edx+16]&lt;BR /&gt;	prefetchnta [esi +2* edx+16]&lt;BR /&gt;	prefetchnta [esi + eax+16]&lt;BR /&gt;	prefetchnta [esi +4* edx+16]&lt;BR /&gt;	&lt;BR /&gt;	add	edi,16&lt;BR /&gt;	add	esi,16			&lt;BR /&gt;	&lt;BR /&gt;	addps	xmm5,xmm4&lt;BR /&gt;	addps	xmm5,xmm3&lt;BR /&gt;&lt;BR /&gt;	sub	ecx,16&lt;BR /&gt;	movaps	[edi-16],xmm5&lt;BR /&gt;jnz	.Label&lt;BR /&gt;&lt;BR /&gt;VTune reports about 57% L2 cache read misses and 32% DTLB Walks(TI). In comparison to the filtering in X or Y direction is it very large. I tried to change the constant 16 in prefetching but it did not help.</description>
      <pubDate>Mon, 09 Jan 2006 23:36:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Analyzers/How-to-decrease-very-poor-CPI-above-7/m-p/952290#M8137</guid>
      <dc:creator>vasko_anton</dc:creator>
      <dc:date>2006-01-09T23:36:29Z</dc:date>
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