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    <title>topic Re: Xeon D-1700 PCIe Gen4 Compliance test in Embedded Server</title>
    <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1575671#M1053</link>
    <description>&lt;P&gt;&lt;SPAN&gt;BIOS Setting :&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Socket Configuration =&amp;gt; IIO Configuration =&amp;gt; Socket0 Configuration =&amp;gt; Port 1A =&amp;gt; Compliance Mode =&amp;gt; Yes,&amp;nbsp;at the mode, the system can't change the test preset, which one is the test mode (Gen4 preset P0-P10)?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In this mode, we could pass PCIe Gen4 compliance test.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_0-1709011038858.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51936i2909DB685B7B6261/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_0-1709011038858.png" alt="TaylorTY_Lin_0-1709011038858.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The BIOS team reported that PCIe Gen4 was automatically set to P7, which complies with the PCIe definition. However, using a Keysight oscilloscope, after comparison, it should be P4, as shown below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The below picture is&amp;nbsp;Compliance Mode =&amp;gt; Yes, the system can't change the test preset, the Preshoot and De-Emphasis is the same as P4.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_1-1709011038862.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51937iBD2E66BBD174A4BA/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_1-1709011038862.png" alt="TaylorTY_Lin_1-1709011038862.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_2-1709011038876.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51938iBCA2D02E8F7A8F0F/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_2-1709011038876.png" alt="TaylorTY_Lin_2-1709011038876.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;By the way, we tested the default mode of P7 and the result was failure, so we need to check which default value on PCIe Gen4?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_3-1709011038881.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51940i67B05223775A0094/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_3-1709011038881.png" alt="TaylorTY_Lin_3-1709011038881.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 27 Feb 2024 05:19:16 GMT</pubDate>
    <dc:creator>TaylorTY_Lin</dc:creator>
    <dc:date>2024-02-27T05:19:16Z</dc:date>
    <item>
      <title>Xeon D-1700 PCIe Gen4 Compliance test</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1575381#M1052</link>
      <description>&lt;P&gt;I am testing PCIe Gen4 using Xeon D-1746 processor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_4-1708944726425.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51910i9200EB802AEE1183/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_4-1708944726425.png" alt="TaylorTY_Lin_4-1708944726425.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;"Adaptive" means that Compliance Mode can automatically select PCIe Gen4 P0~P10?&lt;/P&gt;&lt;P&gt;Socket Configuration =&amp;gt; IIO Configuration =&amp;gt; Socket0 Configuration =&amp;gt; Port 1A =&amp;gt; Compliance Mode =&amp;gt; Yes&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Taylor&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 26 Feb 2024 11:02:53 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1575381#M1052</guid>
      <dc:creator>TaylorTY_Lin</dc:creator>
      <dc:date>2024-02-26T11:02:53Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D-1700 PCIe Gen4 Compliance test</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1575671#M1053</link>
      <description>&lt;P&gt;&lt;SPAN&gt;BIOS Setting :&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Socket Configuration =&amp;gt; IIO Configuration =&amp;gt; Socket0 Configuration =&amp;gt; Port 1A =&amp;gt; Compliance Mode =&amp;gt; Yes,&amp;nbsp;at the mode, the system can't change the test preset, which one is the test mode (Gen4 preset P0-P10)?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In this mode, we could pass PCIe Gen4 compliance test.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_0-1709011038858.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51936i2909DB685B7B6261/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_0-1709011038858.png" alt="TaylorTY_Lin_0-1709011038858.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The BIOS team reported that PCIe Gen4 was automatically set to P7, which complies with the PCIe definition. However, using a Keysight oscilloscope, after comparison, it should be P4, as shown below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The below picture is&amp;nbsp;Compliance Mode =&amp;gt; Yes, the system can't change the test preset, the Preshoot and De-Emphasis is the same as P4.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_1-1709011038862.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51937iBD2E66BBD174A4BA/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_1-1709011038862.png" alt="TaylorTY_Lin_1-1709011038862.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_2-1709011038876.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51938iBCA2D02E8F7A8F0F/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_2-1709011038876.png" alt="TaylorTY_Lin_2-1709011038876.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;By the way, we tested the default mode of P7 and the result was failure, so we need to check which default value on PCIe Gen4?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_3-1709011038881.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/51940i67B05223775A0094/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_3-1709011038881.png" alt="TaylorTY_Lin_3-1709011038881.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 27 Feb 2024 05:19:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1575671#M1053</guid>
      <dc:creator>TaylorTY_Lin</dc:creator>
      <dc:date>2024-02-27T05:19:16Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D-1700 PCIe Gen4 Compliance test</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1577176#M1054</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/284268"&gt;@TaylorTY_Lin&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN&gt;You can try checking the PCIe margin using the IO Margin Tool from the document #630560.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN&gt;From the document #626646 -&amp;nbsp;Ice Lake D LCC SoC Product Family Sightings Report, there are some sightings regarding PCIe Compliance Tests.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;SPAN class="sub_section_element_selectors"&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977?emcs_t=S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExTMk1CQTVSRlpOQUtOfDE1NjgxNTR8U1VCU0NSSVBUSU9OU3xoSw" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 02 Mar 2024 04:37:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1577176#M1054</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2024-03-02T04:37:24Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D-1700 PCIe Gen4 Compliance test</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1578040#M1055</link>
      <description>&lt;P&gt;Hi Diego&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. We want to use the SIV method to authenticate PCIe/SATA,&lt;/P&gt;&lt;P&gt;The IO Margin tool is more like a compatibility test. Please correct me if there is any wrong.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Ref. #763555.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_0-1709693199870.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/52269iBADADEBE33CA4692/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_0-1709693199870.png" alt="TaylorTY_Lin_0-1709693199870.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. By the way, we don't have&amp;nbsp;Intel® In-Target Probe - Extended Debug Port (ITP-XDP),&amp;nbsp;&lt;/P&gt;&lt;P&gt;So I have tried to install IOMT, but that can't support On-target mode, I'm stuck, neither SIV nor SMV can test SATA, and PCIe Gen4 as above.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_1-1709693867549.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/52270iB8BD31A3A171DE05/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_1-1709693867549.png" alt="TaylorTY_Lin_1-1709693867549.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I can't select On Target mode in the Windows 10 operating system.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_3-1709694767080.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/52272iBCB5F21F046DF52D/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_3-1709694767080.png" alt="TaylorTY_Lin_3-1709694767080.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Reference #630559&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_2-1709694693745.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/52271iE90CE0AA547E0595/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_2-1709694693745.png" alt="TaylorTY_Lin_2-1709694693745.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="TaylorTY_Lin_4-1709694838087.png" style="width: 400px;"&gt;&lt;img src="https://community.intel.com/t5/image/serverpage/image-id/52273i9EE0479175977CDA/image-size/medium/is-moderation-mode/true?v=v2&amp;amp;px=400&amp;amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="TaylorTY_Lin_4-1709694838087.png" alt="TaylorTY_Lin_4-1709694838087.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Taylor&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 06 Mar 2024 03:23:13 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-1700-PCIe-Gen4-Compliance-test/m-p/1578040#M1055</guid>
      <dc:creator>TaylorTY_Lin</dc:creator>
      <dc:date>2024-03-06T03:23:13Z</dc:date>
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