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    <title>topic Re: Kaseyville ASD TCK connection in Embedded Server</title>
    <link>https://community.intel.com/t5/Embedded-Server/Kaseyville-ASD-TCK-connection/m-p/1748842#M1256</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/158520"&gt;@IanBanbrook&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
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&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Jaime L.&lt;BR /&gt;Intel Customer Support Engineer&lt;/P&gt;</description>
    <pubDate>Fri, 22 May 2026 20:16:44 GMT</pubDate>
    <dc:creator>Jaime_Lizarme</dc:creator>
    <dc:date>2026-05-22T20:16:44Z</dc:date>
    <item>
      <title>Kaseyville ASD TCK connection</title>
      <link>https://community.intel.com/t5/Embedded-Server/Kaseyville-ASD-TCK-connection/m-p/1748254#M1255</link>
      <description>&lt;P&gt;Am I missing something?&lt;/P&gt;&lt;P&gt;The BMC drives TCK at LVC3V3.&amp;nbsp; On the Kaseyville board it is isolated using a FET switch 74CB3Q3305D U3H2. and connected to the MIPI60 XDP connector and XEON TCK pin which is in the PVCCVNN_MAIN 1v0 domain.&lt;/P&gt;&lt;P&gt;The Kaseyville ref schematic has 49R9 series resistor from the BMC and a 49R9 pull down post switch.&amp;nbsp; This voltage divider gives 1.65V to the XEON TCK pin when driven by the BMC&lt;/P&gt;&lt;P&gt;Is this correct??&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 18 May 2026 09:22:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Kaseyville-ASD-TCK-connection/m-p/1748254#M1255</guid>
      <dc:creator>IanBanbrook</dc:creator>
      <dc:date>2026-05-18T09:22:07Z</dc:date>
    </item>
    <item>
      <title>Re: Kaseyville ASD TCK connection</title>
      <link>https://community.intel.com/t5/Embedded-Server/Kaseyville-ASD-TCK-connection/m-p/1748842#M1256</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/158520"&gt;@IanBanbrook&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
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&lt;P class="subsectionelementselectors" style="background: white; margin: 0in 0in 6.0pt 0in;"&gt;&lt;SPAN&gt;We sent an email to the address associated with this account with information that may help you.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Jaime L.&lt;BR /&gt;Intel Customer Support Engineer&lt;/P&gt;</description>
      <pubDate>Fri, 22 May 2026 20:16:44 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Kaseyville-ASD-TCK-connection/m-p/1748842#M1256</guid>
      <dc:creator>Jaime_Lizarme</dc:creator>
      <dc:date>2026-05-22T20:16:44Z</dc:date>
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