topic Re: Enable/Disable features like APS rocketing, Scalability and PP0 budget in Embedded Server

Enable/Disable features like APS rocketing, Scalability and PP0 budget

AChak12 — Thu, 18 Jul 2019 19:13:17 GMT

I have researched regarding enabling/disabling the above features, but I am unable to find these features . Can anyone guide me , how to enable/disable these features for Broadwell Processor?

Regards,

Re: Enable/Disable features like APS rocketing, Scalability and PP0 budget

CarlosAM_INTEL — Fri, 19 Jul 2019 02:03:02 GMT

Hello, @AChak12:

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please give the part number and SKU of each processor associated to this forum?

We are waiting for your answer.

Best regards,

@Mæcenas_INTEL.

Re: Enable/Disable features like APS rocketing, Scalability and PP0 budget

AChak12 — Mon, 22 Jul 2019 19:19:38 GMT

Hi @Maecenas_INTEL ,

It is for Intel Xeon D1559. We are developing coreboot based bootloader and we are looking on how to enable/disable these features.

Thank You.

Regards,

Re: Enable/Disable features like APS rocketing, Scalability and PP0 budget

CarlosAM_INTEL — Wed, 24 Jul 2019 01:31:06 GMT

Hello, @AChak12:

Thanks for your clarification.

The Coreboot consultations should be addressed as a reference to the channels listed at the following web site:

https://doc.coreboot.org/community/forums.html

Please keep in mind that this suggestion has been provided to you on our communication of the June 25th, 2019 in the following forum:

https://forums.intel.com/s/question/0D50P00004MvTtISAV/can-coreboot-be-built-for-intel-xeon-d1600

Also, this recommendation has been given the past July 4th , 2019 in the following thread:

https://forums.intel.com/s/question/0D50P00004NiTt1SAF/does-the-broadwellde-fspm-support-dcu-prefetcher-and-enhanced-error-containment-code-for-coreboot

Best regards,

@Mæcenas_INTEL.