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    <title>topic Re: Xeon D Power Sequence Issue in Embedded Server</title>
    <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1428191#M927</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I am currently experiencing a very similar situation on a custom PCB&amp;nbsp; with the D-1559. Could you please let me know what suggestions were made to help Carlos_A above?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Email : &amp;lt;EMAIL REMOVED&amp;gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Stephen Ash&lt;/P&gt;</description>
    <pubDate>Mon, 07 Nov 2022 18:19:09 GMT</pubDate>
    <dc:creator>StephenAsh</dc:creator>
    <dc:date>2022-11-07T18:19:09Z</dc:date>
    <item>
      <title>Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241623#M156</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are trying to bringup a new PCB, based on the Power sequence described in BDW_DE_SoC_EDS_vol3._544042_R2_1.pdf.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt; Judging by the SOC outputs, sequence is proceeding correctly nearly till the end (we see SOC de-asserting SLP_S4_N and SLP_S3_N, asserts DRAM_PWR_OK, activates clocks, ands read from SPI bus).&lt;P&gt;&amp;nbsp;&lt;/P&gt; However for some reason PROCPWRGD_PCH and PLTRST_N never go inactive.&lt;P&gt;&amp;nbsp;&lt;/P&gt; We checked several critical outputs from CPU (such as CATERR_N, FIVR_FAULT). but all seem to be ok.&lt;P&gt;&amp;nbsp;&lt;/P&gt; Can anyone advise how to root cause the reason why PROCPWRGD_PCH is not deasserted by the SOC? e.g. which signals to check?&lt;P&gt;&amp;nbsp;&lt;/P&gt; &lt;P&gt;&amp;nbsp;&lt;/P&gt; Thanks,&lt;P&gt;Izak Nashelsky&lt;/P&gt;</description>
      <pubDate>Thu, 19 Jul 2018 11:40:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241623#M156</guid>
      <dc:creator>GBott1</dc:creator>
      <dc:date>2018-07-19T11:40:40Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241624#M157</link>
      <description>&lt;P&gt;Hello, bgil:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In order to be on the same page, could you please give us the part numbers and SKUs of the processors related to this thread?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;By the way, could you please tell us if the affected project has been designed by you or a third-party company? In case that it is a third-party unit, could you please give us all the information related to it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Waiting for your answer to these questions.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Carlos_A.&lt;/P&gt;</description>
      <pubDate>Thu, 19 Jul 2018 15:18:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241624#M157</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2018-07-19T15:18:22Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241625#M158</link>
      <description>&lt;P&gt;Dear Carlos&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Please see blow my answers:&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;B&gt;SKU's&lt;/B&gt;: &lt;/P&gt;&lt;P&gt;Intel® Xeon® Processor D-1539/D-1559&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;B&gt;P/N:&lt;/B&gt;&lt;/P&gt;&lt;P&gt;&lt;B&gt;GG8067402569000 SR2DH (&lt;/B&gt;D-1539)&lt;/P&gt;&lt;P&gt;&lt;B&gt;GG8067402570801 SR2M5 (&lt;/B&gt;D-1559)&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Thanks for support..&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;B&gt;Maxim Alter&lt;/B&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;B&gt;Hardware Engineer&lt;/B&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Tel:&lt;/P&gt;&lt;P&gt;+972(9) 960-0620&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Cell:&lt;/P&gt;&lt;P&gt;+972(54) 541-2339&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Fax:&lt;/P&gt;&lt;P&gt;+972(9) 954-4315&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;E-mail:  mailto:&lt;A href="mailto:malter@rugged.com"&gt;malter@rugged.com&lt;/A&gt; &lt;A href="mailto:malter@rugged.com"&gt;malter@rugged.com&lt;/A&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Company website:   &lt;A href="http://www.rugged.com"&gt;www.rugged.com&lt;/A&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;B&gt; &lt;/B&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 19 Jul 2018 15:59:48 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241625#M158</guid>
      <dc:creator>MAlte</dc:creator>
      <dc:date>2018-07-19T15:59:48Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241626#M159</link>
      <description>&lt;P&gt;Hello, MaximAlter :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We really appreciate the provided information.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, we need the answer to the following questions:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you please tell us if the affected project has been designed by you or a third-party company? In case that it is a third-party unit, could you please give us all the information related to it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Waiting for the requested information.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Carlos_A.&lt;/P&gt;</description>
      <pubDate>Thu, 19 Jul 2018 16:41:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241626#M159</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2018-07-19T16:41:57Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241627#M160</link>
      <description>&lt;P&gt;Hello Carlos&lt;/P&gt;&lt;P&gt;Sorry for delay..&lt;/P&gt;&lt;P&gt;Our Project is C877 SBC I/O 3U VPX based on Xeon D-1500 that designed and manufactured by us (Aitech Systems).&lt;/P&gt;&lt;P&gt;There is NO third-party company envolved in this project.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Maxim Alter&lt;/P&gt;</description>
      <pubDate>Wed, 25 Jul 2018 07:33:07 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241627#M160</guid>
      <dc:creator>MAlte</dc:creator>
      <dc:date>2018-07-25T07:33:07Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241628#M161</link>
      <description>&lt;P&gt;Hello, MaximAlter :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In order to help you, we will contact you via email.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Carlos_A.&lt;/P&gt;</description>
      <pubDate>Wed, 25 Jul 2018 15:04:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/241628#M161</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2018-07-25T15:04:42Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1428191#M927</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I am currently experiencing a very similar situation on a custom PCB&amp;nbsp; with the D-1559. Could you please let me know what suggestions were made to help Carlos_A above?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Email : &amp;lt;EMAIL REMOVED&amp;gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Stephen Ash&lt;/P&gt;</description>
      <pubDate>Mon, 07 Nov 2022 18:19:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1428191#M927</guid>
      <dc:creator>StephenAsh</dc:creator>
      <dc:date>2022-11-07T18:19:09Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1428315#M928</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/241009"&gt;@StephenAsh&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;We sent an email to the address associated with this account with information that may help you.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
      <pubDate>Tue, 08 Nov 2022 02:00:29 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1428315#M928</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2022-11-08T02:00:29Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1441248#M936</link>
      <description>&lt;P&gt;Hello Carlos,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have the same problem. Could you please give us the document that consist solution?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Yunus.&lt;/P&gt;</description>
      <pubDate>Fri, 23 Dec 2022 15:13:11 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1441248#M936</guid>
      <dc:creator>YunusD</dc:creator>
      <dc:date>2022-12-23T15:13:11Z</dc:date>
    </item>
    <item>
      <title>Re: Xeon D Power Sequence Issue</title>
      <link>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1441416#M939</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/121419"&gt;@YunusD&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;We sent an email to the address related to this account with information that may help you.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 24 Dec 2022 00:59:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Server/Xeon-D-Power-Sequence-Issue/m-p/1441416#M939</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2022-12-24T00:59:15Z</dc:date>
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