<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic FSP with debug info in Embedded Intel Atom® Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/FSP-with-debug-info/m-p/719117#M3932</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I got the following output after compiling coreboot with a debug FSP for baytrail:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;============= PEIM FSP v1.0 (VLYVIEW0 v0.0.3.5) =============&lt;/P&gt;&lt;P&gt;Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE&lt;/P&gt;&lt;P&gt;Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3&lt;/P&gt;&lt;P&gt;Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A&lt;/P&gt;&lt;P&gt;The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0&lt;/P&gt;&lt;P&gt;Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39&lt;/P&gt;&lt;P&gt;Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38&lt;/P&gt;&lt;P&gt;Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6&lt;/P&gt;&lt;P&gt;Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480&lt;/P&gt;&lt;P&gt;Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39&lt;/P&gt;&lt;P&gt;Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FE4&lt;/P&gt;&lt;P&gt;The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;PcdMrcInitTsegSize = 8&lt;/P&gt;&lt;P&gt;PcdMrcInitMmioSize = 800&lt;/P&gt;&lt;P&gt;PcdMrcInitSPDAddr1 = A0&lt;/P&gt;&lt;P&gt;PcdMrcInitSPDAddr2 = A2&lt;/P&gt;&lt;P&gt;Setting BootMode to 0&lt;/P&gt;&lt;P&gt;Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56&lt;/P&gt;&lt;P&gt;Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE&lt;/P&gt;&lt;P&gt;About to call MrcInit();&lt;/P&gt;&lt;P&gt;BayleyBay Platform Type&lt;/P&gt;&lt;P&gt;AutoSelfRefreshEnable =&amp;nbsp;0x2&lt;/P&gt;&lt;P&gt;RID = 0x11.&lt;/P&gt;&lt;P&gt;Reg_EFF_DualCH_EN = 0x100301C0.&lt;/P&gt;&lt;P&gt;CurrentMrcData.BootMode = 4&lt;/P&gt;&lt;P&gt;C0.D0: SPD not present.&lt;/P&gt;&lt;P&gt;C1.D0: SPD not present.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What should I do with this information ?&lt;/P&gt;&lt;P&gt;Should I use it in Intel's BCT to modify some default FSP values ?&lt;/P&gt;&lt;P&gt;or should I use it to modify the current devicetree.cb ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a detailed documentation explains what is the meaning of each line in the messages I got ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;Zvika &lt;/P&gt;</description>
    <pubDate>Sun, 10 Feb 2019 04:50:16 GMT</pubDate>
    <dc:creator>ZVere</dc:creator>
    <dc:date>2019-02-10T04:50:16Z</dc:date>
    <item>
      <title>FSP with debug info</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/FSP-with-debug-info/m-p/719117#M3932</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I got the following output after compiling coreboot with a debug FSP for baytrail:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;============= PEIM FSP v1.0 (VLYVIEW0 v0.0.3.5) =============&lt;/P&gt;&lt;P&gt;Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE&lt;/P&gt;&lt;P&gt;Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3&lt;/P&gt;&lt;P&gt;Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A&lt;/P&gt;&lt;P&gt;The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0&lt;/P&gt;&lt;P&gt;Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39&lt;/P&gt;&lt;P&gt;Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38&lt;/P&gt;&lt;P&gt;Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6&lt;/P&gt;&lt;P&gt;Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480&lt;/P&gt;&lt;P&gt;Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39&lt;/P&gt;&lt;P&gt;Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FE4&lt;/P&gt;&lt;P&gt;The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;PcdMrcInitTsegSize = 8&lt;/P&gt;&lt;P&gt;PcdMrcInitMmioSize = 800&lt;/P&gt;&lt;P&gt;PcdMrcInitSPDAddr1 = A0&lt;/P&gt;&lt;P&gt;PcdMrcInitSPDAddr2 = A2&lt;/P&gt;&lt;P&gt;Setting BootMode to 0&lt;/P&gt;&lt;P&gt;Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56&lt;/P&gt;&lt;P&gt;Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE&lt;/P&gt;&lt;P&gt;About to call MrcInit();&lt;/P&gt;&lt;P&gt;BayleyBay Platform Type&lt;/P&gt;&lt;P&gt;AutoSelfRefreshEnable =&amp;nbsp;0x2&lt;/P&gt;&lt;P&gt;RID = 0x11.&lt;/P&gt;&lt;P&gt;Reg_EFF_DualCH_EN = 0x100301C0.&lt;/P&gt;&lt;P&gt;CurrentMrcData.BootMode = 4&lt;/P&gt;&lt;P&gt;C0.D0: SPD not present.&lt;/P&gt;&lt;P&gt;C1.D0: SPD not present.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;What should I do with this information ?&lt;/P&gt;&lt;P&gt;Should I use it in Intel's BCT to modify some default FSP values ?&lt;/P&gt;&lt;P&gt;or should I use it to modify the current devicetree.cb ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there a detailed documentation explains what is the meaning of each line in the messages I got ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;Zvika &lt;/P&gt;</description>
      <pubDate>Sun, 10 Feb 2019 04:50:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/FSP-with-debug-info/m-p/719117#M3932</guid>
      <dc:creator>ZVere</dc:creator>
      <dc:date>2019-02-10T04:50:16Z</dc:date>
    </item>
    <item>
      <title>Re: FSP with debug info</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/FSP-with-debug-info/m-p/719118#M3933</link>
      <description>&lt;P&gt;Hello, &lt;A href="https://community.intel.com/sfdc-users/ZVere"&gt;@ZVere&lt;/A&gt;​:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We suggest you&amp;nbsp;refer to&amp;nbsp;the suggestions and information stated in the Intel(R) Firmware Support Package [FSP] for Intel(R) Atom(TM) Processor E3800 Product Family: Integration Guide document # 331165 that may answer your questions.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This document can be found at the following website:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/guides/atom-e3800-fsp-integration-guide.pdf" target="_self" alt="https://www.intel.com/content/dam/www/public/us/en/documents/guides/atom-e3800-fsp-integration-guide.pdf"&gt;&lt;/A&gt;&lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/guides/atom-e3800-fsp-integration-guide.pdf"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/guides/atom-e3800-fsp-integration-guide.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We hope that this information is useful to you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.intel.com/sfdc-users/Mæcenas_INTEL"&gt;@Mæcenas_INTEL&lt;/A&gt;​.&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 12 Feb 2019 22:52:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/FSP-with-debug-info/m-p/719118#M3933</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2019-02-12T22:52:06Z</dc:date>
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  </channel>
</rss>

