topic Re: Swizzling for Intel MRD in Embedded Intel Atom® Processors

Swizzling for Intel MRD

ChipsetWr — Tue, 24 Nov 2020 08:37:34 GMT

Is there example somewhere of MemoryInit settings for #572383 "Apollo Lake Platform MRD Refresh LPDDR4 Design Schematics Rev 2.0"? I am looking for swizzling settings (ChN_Bit_Swizzling).

Thank you

Re: Swizzling for Intel MRD

CarlosAM_INTEL — Tue, 24 Nov 2020 13:46:23 GMT

Hello, @ChipsetWr:

Thank you for contacting Intel Embedded Community.

You should review with the assistance of your Intel BIOS Vendor (IBV) the information that may answer your request on pages 82, 83, and 89 of the Intel Pentium and Celeron Processor N- and J- Series Formerly Apollo Lake Intel Architecture Firmware Specification Volume 1 of 2 BIOS Specification document # 559810. You can find this document when you are logged into your Resource and Design Center (RDC) privileged account on the following website:

https://cdrdv2.intel.com/v1/dl/getContent/559810

You should fill out the form stated on the following website when you have problems with the provided website or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

Re: Swizzling for Intel MRD

ChipsetWr — Wed, 25 Nov 2020 11:47:09 GMT

Thank you, @CarlosAM_INTEL , but I need exact values for that Intel MRD schematic. Maybe there is some coreboot sources of BIOS or something?

Re: Swizzling for Intel MRD

CarlosAM_INTEL — Wed, 25 Nov 2020 23:01:25 GMT

Hello, @ChipsetWr:

Thanks for your reply.

You should contact your IBV to help with your last request, as we have suggested in our previous message.

Best regards,

@CarlosAM_INTEL.

Re: Swizzling for Intel MRD

ChipsetWr — Thu, 10 Dec 2020 08:37:11 GMT

For those of you still searching for an answer here are correct memory settings for #572383 "Apollo Lake Platform MRD Refresh LPDDR4 Design Schematics Rev 2.0":

ChannelHashMask :0x36
SliceHashMask :0x9
ChannelsSlicesEnabled :0x0
ScramblerSupport :0x1
InterleavedMode :0x2
MinRefRate2xEnabled :0x0
DualRankSupportEnabled :0x1
Profile :0xB
SpdAddress[0] :0x0
SpdAddress[1] :0x0
SystemMemorySizeLimit :0x0
LowMemMaxVal :0x0
HighMemMaxVal :0x0
DisableFastBoot :0x0
RmtMode :0x0
RmtCheckRun :0x3
RmtMarginCheckScaleHighThreshold:0xC8
MsgLevelMask :0x0
MemoryDown :0x1
Channel0:
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x2
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0
Swizzling:
0 7 5 6 3 1 2 4 F A 8 B E C D 9 1D 1F 19 18 1C 1B 1A 1E 15 12 13 16 17 11 10 14
Channel1:
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x2
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0
Swizzling:
6 7 2 3 4 1 0 5 9 B C A D E F 8 12 16 17 14 11 10 13 15 1E 1F 1C 1A 1B 19 18 1D
Channel2:
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x2
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0
Swizzling:
E A B D F 9 8 C 5 3 1 2 0 7 6 4 1B 1F 1E 1D 1A 19 18 1C 15 12 11 14 16 17 13 10
Channel3:
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x2
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0
Swizzling:
5 7 0 1 2 3 4 6 D C B A 9 F 8 E 1D 18 1C 1E 19 1B 1A 1F 16 10 13 15 12 17 14 11