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    <title>topic Re: CommandClockTraining fails in Embedded Intel Atom® Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313626#M4444</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/121595"&gt;@jamesadupre&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thanks for your reply.&lt;/P&gt;
&lt;P&gt;Based on your previous communication, could you please clarify if the reported situation is related to BIOS or Coreboot?&lt;/P&gt;
&lt;P&gt;We are waiting for your answer.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
    <pubDate>Fri, 10 Sep 2021 14:03:04 GMT</pubDate>
    <dc:creator>CarlosAM_INTEL</dc:creator>
    <dc:date>2021-09-10T14:03:04Z</dc:date>
    <item>
      <title>CommandClockTraining fails</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313411#M4441</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I have a custom board design that uses the C3958. During boot time, it consistently fails the "CommandClockTraining" algorithm of the memory initialization. Can someone please explain what this algorithm is doing and why it is failing? The output of the UART is below. I'm not looking for a root cause diagnosis, I'd just like to understand what this algorithm is doing and why it might not pass. For example, is this algorithm sweeping the clock output from minimum phase delay to maximum phase delays while sampling the command signals on each clock edge to determine the phase delay which produces the optimal eye?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;James&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;START_CommandClockTraining&lt;BR /&gt;Setting CMD GRP = 340 at 3N&lt;BR /&gt;Setting CMD GRP = 340 at 3N&lt;BR /&gt;Setting CMD GRP = 324 at 3N&lt;BR /&gt;Setting CMD GRP = 308 at 3N&lt;BR /&gt;Setting CMD GRP = 292 at 3N&lt;BR /&gt;Setting CMD GRP = 276 at 3N&lt;BR /&gt;Setting CMD GRP = 260 at 3N&lt;BR /&gt;Setting CMD GRP = 244 at 3N&lt;BR /&gt;Setting CMD GRP = 228 at 3N&lt;BR /&gt;Setting CMD GRP = 212 at 3N&lt;BR /&gt;Setting CMD GRP = 196 at 3N&lt;BR /&gt;Setting CMD GRP = 180 at 3N&lt;BR /&gt;Setting CMD GRP = 356 at 3N&lt;BR /&gt;Setting CMD GRP = 372 at 3N&lt;BR /&gt;Setting CMD GRP = 388 at 3N&lt;BR /&gt;Setting CMD GRP = 404 at 3N&lt;BR /&gt;Setting CMD GRP = 420 at 3N&lt;BR /&gt;Setting CMD GRP = 436 at 3N&lt;BR /&gt;Setting CMD GRP = 452 at 3N&lt;BR /&gt;Setting CMD GRP = 468 at 3N&lt;BR /&gt;Setting CMD GRP = 340 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 484 at 3N&lt;BR /&gt;Setting CMD GRP = 340 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 500 at 3N&lt;BR /&gt;Setting CMD GRP = 340 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**Result L: -160 H:112 New Value = 316&lt;BR /&gt;Setting CMD GRP = 316 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 300 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 284 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 268 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 252 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 236 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 220 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 204 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 188 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 172 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 156 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 332 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 348 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 364 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 380 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 396 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 412 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 428 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 444 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 460 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 476 at 1N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Margin not found at 1N&lt;BR /&gt;Not Found any Margin at 1N. Trying 2N&lt;BR /&gt;Setting CMD GRP = 316 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 300 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 284 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 268 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 252 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 236 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 220 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 204 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 188 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 172 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 156 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 332 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 348 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 364 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 380 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 396 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 412 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 428 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 444 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 460 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Setting CMD GRP = 476 at 2N&lt;BR /&gt;Setting CMD GRP = 316 at 3N&lt;BR /&gt;**ReInitialize&lt;BR /&gt;Margin not found at 2N&lt;BR /&gt;elapsedTime: 2701886(us)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 09 Sep 2021 19:21:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313411#M4441</guid>
      <dc:creator>jamesadupre</dc:creator>
      <dc:date>2021-09-09T19:21:01Z</dc:date>
    </item>
    <item>
      <title>Re: CommandClockTraining fails</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313444#M4443</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/121595"&gt;@jamesadupre&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P&gt;We sent an email to the address associated with this account with information that may help.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 09 Sep 2021 21:04:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313444#M4443</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2021-09-09T21:04:27Z</dc:date>
    </item>
    <item>
      <title>Re: CommandClockTraining fails</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313626#M4444</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/121595"&gt;@jamesadupre&lt;/a&gt;:&lt;/P&gt;
&lt;P&gt;Thanks for your reply.&lt;/P&gt;
&lt;P&gt;Based on your previous communication, could you please clarify if the reported situation is related to BIOS or Coreboot?&lt;/P&gt;
&lt;P&gt;We are waiting for your answer.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/114"&gt;@CarlosAM_INTEL&lt;/a&gt;.&lt;/P&gt;</description>
      <pubDate>Fri, 10 Sep 2021 14:03:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313626#M4444</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2021-09-10T14:03:04Z</dc:date>
    </item>
    <item>
      <title>Re: CommandClockTraining fails</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313744#M4445</link>
      <description>&lt;P&gt;It is with the BIOS. The file I programmed into the SPI Flash (which is the boot source) is&amp;nbsp;HVLRCRB.86B.WR.64.2021.17.4.01.1422.HCV16D37.bin and the BIOS ID is&amp;nbsp;HAVLCRB1.X64.0016.D37.2104221422. For reference, I have attached a log file with the output of UART0 from the start of boot to the end when it fails the CommandClockTraining algorith.&lt;/P&gt;</description>
      <pubDate>Fri, 10 Sep 2021 22:53:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1313744#M4445</guid>
      <dc:creator>jamesadupre</dc:creator>
      <dc:date>2021-09-10T22:53:08Z</dc:date>
    </item>
    <item>
      <title>Re: CommandClockTraining fails</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1314553#M4448</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello,&amp;nbsp;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/121595" target="_blank"&gt;@jamesadupre&lt;/A&gt;:&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thanks for your replies.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;We sent another email to the address associated with this account with information that may help.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/114" target="_blank"&gt;@CarlosAM_INTEL&lt;/A&gt;.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Sep 2021 20:11:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/CommandClockTraining-fails/m-p/1314553#M4448</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2021-09-14T20:11:08Z</dc:date>
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