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    <title>topic Re: Help implementing PCU SPI in Atom E3800 in Embedded Intel Atom® Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1483148#M5029</link>
    <description>&lt;P&gt;Hello Diego,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for the links.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;According to the Coreboot post, it seems the PCU SPI controller cannot be seen in the OS. I will continue to do research on this topic and post here if I find anything.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 04 May 2023 18:24:17 GMT</pubDate>
    <dc:creator>AtomHelp</dc:creator>
    <dc:date>2023-05-04T18:24:17Z</dc:date>
    <item>
      <title>Help implementing PCU SPI in Atom E3800</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1482339#M5018</link>
      <description>&lt;P&gt;Hello all,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Has anyone had any success implementing the SPI controller in the PCU in an Atom E3800 series processor?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I am trying to use the PCU SPI to configure a flash device, but I am having no luck in accessing the controller. Any reads to the SPI base address B/D/F located at 0/31/0 + 0x54 offset results in a read value of &lt;STRONG&gt;0xFED01002&lt;/STRONG&gt;.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Does anyone have any information on this? I did some research on this resulting value and upon looking at some Chipsec dumps, it seems to mean something, but I cannot figure out what exactly.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In any case, I just can't access my flash device using the SPI controller. When I attempt to read the hardware sequencing status register (HSFSTS) at offset 0x4, it returns a &lt;STRONG&gt;0x2&lt;/STRONG&gt;, indicating the FCERR bit is set. The datasheet says this is set by hardware if there's a "protection policy" configured, but it never clarifies what these "protection policies" are.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I am using an RTOS (not Linux or Windows), so I can't run any utilities.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;There's very little information about this part online so I'm hoping to get answers here. Thank you for any tips or suggestions.&lt;/P&gt;</description>
      <pubDate>Tue, 02 May 2023 16:18:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1482339#M5018</guid>
      <dc:creator>AtomHelp</dc:creator>
      <dc:date>2023-05-02T16:18:27Z</dc:date>
    </item>
    <item>
      <title>Re: Help implementing PCU SPI in Atom E3800</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1482896#M5028</link>
      <description>&lt;P class="sub_section_element_selectors"&gt;Hello&amp;nbsp;&lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/291909"&gt;@AtomHelp&lt;/a&gt;,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;We are not supporting Bay Trail family anymore.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://www.intel.com/content/www/us/en/support/articles/000022396/processors.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/support/articles/000022396/processors.html&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;I'm not sure if what you are trying to do can be done according to this.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://www.mail-archive.com/coreboot@coreboot.org/msg49652.html" target="_blank"&gt;https://www.mail-archive.com/coreboot@coreboot.org/msg49652.html&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Also, I'm sharing the link for Bay Trail documents. You may check them to see what is available.&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A href="https://www.intel.com/content/www/us/en/products/platforms/details/bay-trail/docs.html" target="_blank"&gt;https://www.intel.com/content/www/us/en/products/platforms/details/bay-trail/docs.html&lt;/A&gt;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 03 May 2023 23:38:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1482896#M5028</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-05-03T23:38:50Z</dc:date>
    </item>
    <item>
      <title>Re: Help implementing PCU SPI in Atom E3800</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1483148#M5029</link>
      <description>&lt;P&gt;Hello Diego,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for the links.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;According to the Coreboot post, it seems the PCU SPI controller cannot be seen in the OS. I will continue to do research on this topic and post here if I find anything.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 04 May 2023 18:24:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1483148#M5029</guid>
      <dc:creator>AtomHelp</dc:creator>
      <dc:date>2023-05-04T18:24:17Z</dc:date>
    </item>
    <item>
      <title>Re: Help implementing PCU SPI in Atom E3800</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1483222#M5031</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.intel.com/t5/user/viewprofilepage/user-id/291909"&gt;@AtomHelp&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Yes, that's why I'm not sure if it can be done but if you find anything else, it may be very interesting to know.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;Best regards,&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="sub_section_element_selectors"&gt;&lt;A class="sub_section_element_selectors" href="https://community.intel.com/t5/user/viewprofilepage/user-id/266977" target="_blank" rel="noopener"&gt;@Diego_INTEL&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 04 May 2023 22:06:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Atom-Processors/Help-implementing-PCU-SPI-in-Atom-E3800/m-p/1483222#M5031</guid>
      <dc:creator>Diego_INTEL</dc:creator>
      <dc:date>2023-05-04T22:06:18Z</dc:date>
    </item>
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