topic Amston Lake IBECC in Embedded Intel Atom® Processors

Amston Lake IBECC

武橋詰 — Wed, 26 Nov 2025 08:06:57 GMT

Is it possible to inject ECC errors in order to check the IBECC mechanism?

(We use DDR5 Unbuffered Non ECC SO-DIMM)

Re: Amston Lake IBECC

Jaime_Lizarme — Wed, 26 Nov 2025 20:18:59 GMT

Thank you for contacting the Intel Embedded Community.

It is not possible to inject ECC errors on DDR5 Unbuffered Non-ECC SO-DIMM modules on an Amston Lake board to test the IBECC mechanism, because the memory modules do not support ECC and the ECC error injection infrastructure requires ECC-capable DIMMs.

Best regards,

Jaime L.

Re: Amston Lake IBECC

武橋詰 — Thu, 27 Nov 2025 01:45:01 GMT

Thank you for your reply.

We use Atom x7000RE series.
We think IBECC is ECC function with Non-ECC SO-DIMM.
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750907_AlderLakeN_AmstonLake_IBECC_TA_Rev1.2.pdf

page 7: 2.0 In-Band Error Correction Code

The In-Band Error Correction Code (IBECC) module improves accuracy and reliability by providing error check and correct protection to all or specific regions of the physical memory space. The IBECC can be enabled for memory technologies that do not support the out-of-band ECC, where the cost of adding an additional device to each channel for ECC data storage is prohibitive. The IBECC will allow up to eight different address regions to be protected. An ECC space will also be reserved to store the ECC values for all protected regions and there will be some performance impact due to additional bandwidth required. The platform has IBECC enabled for all memory technologies (LPDDR5, DDR5 and DDR4).
Out of Band ECC is not supported on this platform.

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Also, we found on the same doc. about Error Injection.

page17: 5.0 IBECC Error Injection

Regards,

Takeshi Hashizume