topic Re: E3815 GTT memory allocation in Embedded Intel Atom® Processors

E3815 GTT memory allocation

AMamo1 — Tue, 15 Nov 2016 09:34:41 GMT

Hello!

I'm trying to figure out the order of initialization of the E3815 graphics. I cannot understand whether to allocate memory for Graphics Translation Table. The documentation (# IHD-OS-VLV-Vol5-04.14, page 19) says: "The base address (MM offset) of the GTT and the PPGTT are programmed via the PGTBL_CTL and PGTBL_CTL2 MI registers, respectively." But I can not find the description of the register PGTBL_CTL in the E3800 Datasheet. Also, I looked at the Linux driver (i915) source code and it seems like it doesn't allocate memory for GTT. Hence the question: Do I have to allocate memory for GTT, and if so, how to do it correctly?

Re: E3815 GTT memory allocation

CarlosAM_INTEL — Tue, 15 Nov 2016 16:27:37 GMT

Hello AlexMamonov ,

Thank you for contacting the Intel Embedded Community.

The information that may help you is stated in the https://01.org/sites/default/files/documentation/intel_os_gfx_prm_vol2_-_cmd_ref_registers_0.pdf Intel® Open Source HD Graphics Programmers' Reference Manual (PRM) Volume 2, Part 3: Command Reference - Registers For the 2014 Intel Atom™ Processors, Celeron™ Processors, and Pentium™ Processors based on the "BayTrail" Platform (ValleyView graphics) document # IHD-OS-VLV-Vol2pt3-04.14.

It is important to let you know that the Intel Open Source Graphics Programmer's Reference Manual (PRM) For The 2014 Intel® Atom™ Processors, Celeron™ Processors, and Pentium™ Processors based on the Bay Trail Platform can be found at the https://01.org/linuxgraphics/documentation/driver-documentation-prms/2014-intel-processors-based-bay-trail-platform 2014 Intel Processors based on the Bay Trail Platform website.

We hope that this information may help you.

Best Regards,

Carlos_A.

Re: E3815 GTT memory allocation

AMamo1 — Thu, 17 Nov 2016 06:54:56 GMT

Hello, Carlos.

I looked through document that you mentioned, but I didnt find anything on PGTBL_CTL register or on allocating memory for GTT. Please, could you elaborate in what part of the document should I seek?

Thanks in advance, Alex.

Re: E3815 GTT memory allocation

CarlosAM_INTEL — Thu, 17 Nov 2016 20:14:48 GMT

Hello, AlexMamonov :

Thanks for your reply.

We suggest you address your consultations to the https://01.org/linuxgraphics/forum/graphics-power-users Intel(R) Graphics for Linux* Forum or its https://lists.freedesktop.org/mailman/listinfo/intel-gfx Mailing list.

We hope that this information may help you.

Best regards,

Carlos_A.

Re: E3815 GTT memory allocation

OTS — Sat, 04 Nov 2023 01:07:03 GMT

I know that this question was asked long ago. However, I was looking for the same information and found this topic, which is still unanswered. So I thought I might drop what I could figure out so far for those who come here somewhen in the future.

First: I could not find the PGTBL_CTL register in the Valleyview documentation for the E3815, either, even though it is supposed to exist. I did not check the E3815 datasheet, but I believe you that there is nothing there either.

This register existed in older graphics circuits (see attachment).

But I don't think that it was ever used. On an Gen3 compatible graphics circuit (Pineview) I could read the value 0x00000001 which was written by the BIOS I guess. On a Gen7LC compatible graphics circuit (Valleyview in an E3815) I could not read a value as if there was no register at the offset 0x2020. I did not test which graphics circuit was the first to drop this register.

The GTT base address (bits 31:12 and 7:4) can be retrieved from a PCI configuration register.

The size of the GTT (bits 3:1) can be ignored. The graphics circuit does not need to know the size of the GTT. The GTT has no fixed size. It's a loose collection of entries.

When byte 0 to 4,095 of the video memory is accessed then GTT[0] is accessed and needs to exist.
When byte 4,096 to 8,191 is accessed then GTT[1] is accessed and needs to exist.
When byte 8,192 to 12,287 is accessed then GTT[2] is accessed and needs to exist.

So when no byte from 4,096 to 8,191 is ever accessed then GTT[1] does not need to exist and the space can be used for other data. So the size of GTT is not fixed and doesn't need to be stored anywhere.

The page table enable bit (bit 0) is the only one that needed to be set to 1 I guess. When this register still existed it was an extra superfluously on switch for the driver to babysit. Everyone probably just set it to 1 once and then never thouched it again.

So my guess is that this register was dropped somewhen between Gen3 and Gen7LC but the reference to it was copied and pasted into the Valleyview documentation from an older documentation.

Maybe this information helps someone. Helpful information is hard to find for us driver developers. But I am also still learning and often enough: guessing.

Re: E3815 GTT memory allocation

CarlosAM_INTEL — Fri, 01 Dec 2023 23:59:50 GMT

Hello, @OTS :

Thank you for contacting Intel Embedded Community.

The Intel Atom® Processor E3815 is a Bay Trail processor.

The active support for the BayTrail family has ended. But you can check this link for the documentation:

https://www.intel.com/content/www/us/en/products/platforms/details/bay-trail/docs.html

Best regards,

@CarlosAM_INTEL.