topic Re: TCVIL for 80L186EC16 Timing Issue in Embedded Intel® Core™ Processors

TCVIL for 80L186EC16 Timing Issue

EDolf — Mon, 13 Feb 2017 20:46:50 GMT

hello All have a question:

The parameter in question is

TCVIL, see the attached spec pages

On the tester I can see the CAS2:0

data drive in manner that looks very similar to what is displayed in the

waveform on page 46. The data comes out on the AD15-AD13 pins at roughly

the same time as the start of the first INTA low pulse, and the data stays on

the outputs until just after the end of the second INTA low pulse, at which

time the pins float. I measure both TILIH and TIHIL and both are very

close to the specified 2T and 4T respectively. The problem with the TCVIL

parameter can be seen by looking at the timing diagram. TCVIL should be

roughly equal to TILIH + TIHIL which equals 6T. But the value Intel

entered under the parameter is 8T. This doesn't make sense. I

suspect the 8T is an error and should be 6T, or that the timing diagram should

show TCVIL running through the end of the second low pulse.

We believe the limit should

be from 8T to 6T based on measurement and we suspect the datasheet is an error,

is this assumption correct!

If any one of you could help answer this issue with the timing

parameters that would be terrific!

Gene

Re: TCVIL for 80L186EC16 Timing Issue

CarlosAM_INTEL — Tue, 14 Feb 2017 16:05:26 GMT

Hello, GeneDolfi:

Thank you for contacting Intel Embedded Community.

It is important to let you know that Intel guarantees the proper functionality of their devices if your implementations fulfill with all the recommendations stated in their documentations. Any situation out of the information stated in the documentation should be tested and validated on your own.

By the way, please review the attached document.

We hope that this information may help you.

Best regards,

Carlos_A.

Re: TCVIL for 80L186EC16 Timing Issue

EDolf — Tue, 14 Feb 2017 16:22:17 GMT

Carlos_A guess I misunderstood help, yes I know Intel is not supporting this device, but would have thought with such a large user group someone would have come across this issue and either Intel published some up-date to the data sheet way back when or based on other user having a similar question there was clarification for this timing parameters, your advise to test on your own to the data sheet is what I have done, i.e. that why the question was asked in the first place. Based on your recommendation I guess if the physical part is providing this result, I would have to assume that the Intel data sheet is in error.

Thanks

Gene