topic Re: Unreliable DIMM B operation in Haswell based design in Embedded Intel® Core™ Processors

Unreliable DIMM B operation in Haswell based design

PWilc1 — Thu, 02 Mar 2017 02:39:21 GMT

Dear Embedded Community,

We have a Haswell based processor design. It has two DIMMs,

one connected to each of the two DDR controllers. The "A"

DIMM appears to work. The "B" DIMM gets occasional errors

and the processor will often crash during booting Linux or

some time afterwards.

We are seeing some differences between the "A" and "B" DIMM

signals. We have been triggering on ODT. We believe that when

ODT is high, this should mean that the processor is driving DQS

and data towards the DIMM.

In the attached traces, the pink signal is ODT and the yellow and

blue signals are DQSxP/N.

In the attached trace for DIMM A DQS7, APR2i_A_DQS7_ODT.tif,

during ODT we get what we would expect: ODT asserted, followed

by eight clock edges then ODT deasserted.

But in the attached trace for B DQS2, APR2i_B_DQS2_ODT.tif,

during ODT we get an initial bad clock transition. Followed

by some O.K. clocks, then clock seven seems to be just plain

missing. I particularly don't understand the missing clock.

The DIMM "B" trace lengths follow the requirements in the

Haswell Desktop and Denlow-WS Platform Design Guide, 486711

Is there any explanation that you can give us for the very

odd behaviour of the clocks on the "B" DIMM?

We can send the Allegro .brd layout file if this would be useful.

Does Intel offer a layout examination service? This would be very

helpful. We have had the schematics looked at by Intel in the past.

Thanks, Paul.

Re: Unreliable DIMM B operation in Haswell based design

CarlosAM_INTEL — Thu, 02 Mar 2017 15:57:48 GMT

Hello, PVWB:

Thank you for contacting Intel Embedded Community.

You can request a layout review following the suggestions stated at the https://edc.intel.com/Tools/Design-Review/Default.aspx?language=en Design Review Services website, also filling out the https://edc.intel.com/Tools/Design-Review/Apply/?t=l Layout Review Service Request Form.

By the way, could you please tell us the part number of the processor related to the affected design?

We hope that this information may help you.

Best regards,

Carlos_A .

Re: Unreliable DIMM B operation in Haswell based design

PWilc1 — Thu, 02 Mar 2017 19:20:19 GMT

Dear Carlos,

I will try the layout review services. Thank you for the pointer to this.

We are use the E3-1268Lv3 processor.

Thanks, Paul.

Re: Unreliable DIMM B operation in Haswell based design

CarlosAM_INTEL — Thu, 02 Mar 2017 20:44:27 GMT

Hello, PVWB:

We really appreciate your update.

We are glad to hear that your design will be verified by Intel. By the way, based on your previous communication, could you please verify if the problem can be reproduced using any of the memories listed at the http://www.intel.com/content/dam/www/public/us/en/documents/platform-memory/ddr3-1600-udimm-ecc-haswell-validation-results.pdf validated memories for the Intel(R) Xeon(R) Processor E3-1200 v3 Processors (codename Haswell) and let us know the results?

Waiting for your reply.

Best regards,

Carlos_A.