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    <title>topic PLEVT SATA margin test in Embedded Intel® Core™ Processors</title>
    <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/PLEVT-SATA-margin-test/m-p/250420#M2387</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our DQA member tries to SATA margin test on Denventon platform&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;they used # 526691(Intel Physical Layer Electrical Validation Tool Ver 1.12.7)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But the Tool can't capture SATA data that like below picture.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;we are sure our BIOS program HSIO 16,17 and 18 to SATA. Therefore, we can run the SATA device well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you have any suggest?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
    <pubDate>Fri, 10 Aug 2018 06:15:16 GMT</pubDate>
    <dc:creator>FTsai1</dc:creator>
    <dc:date>2018-08-10T06:15:16Z</dc:date>
    <item>
      <title>PLEVT SATA margin test</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/PLEVT-SATA-margin-test/m-p/250420#M2387</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Our DQA member tries to SATA margin test on Denventon platform&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;they used # 526691(Intel Physical Layer Electrical Validation Tool Ver 1.12.7)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But the Tool can't capture SATA data that like below picture.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;we are sure our BIOS program HSIO 16,17 and 18 to SATA. Therefore, we can run the SATA device well.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could you have any suggest?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Fri, 10 Aug 2018 06:15:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/PLEVT-SATA-margin-test/m-p/250420#M2387</guid>
      <dc:creator>FTsai1</dc:creator>
      <dc:date>2018-08-10T06:15:16Z</dc:date>
    </item>
    <item>
      <title>Re: PLEVT SATA margin test</title>
      <link>https://community.intel.com/t5/Embedded-Intel-Core-Processors/PLEVT-SATA-margin-test/m-p/250421#M2388</link>
      <description>&lt;P&gt;Hello, Frankey:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for contacting Intel Embedded Community.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In order to be on the same page, could you please confirm that you have followed the procedure stated in section 2.3.1, on pages 6 and 7 of the Intel(R) Physical Layer Electrical Validation Tool [Intel(R) PLEVT] User Guide document #  562291? This guide has the same document number that the tool cited in your previous message because they can be found in the same file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please let us know the information that should answer this question.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Carlos_A.&lt;/P&gt;</description>
      <pubDate>Fri, 10 Aug 2018 22:39:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Embedded-Intel-Core-Processors/PLEVT-SATA-margin-test/m-p/250421#M2388</guid>
      <dc:creator>CarlosAM_INTEL</dc:creator>
      <dc:date>2018-08-10T22:39:23Z</dc:date>
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