https://community.intel.com/t5/Embedded-Intel-Core-Processors/CML-PDG-doc-610244-question/m-p/686916#M3359 <P>Hello, <A href="https://community.intel.com/sfdc-users/RSun">@RSun</A>​:</P><P>&nbsp;</P><P>Thank you for contacting Intel Embedded Community.</P><P>&nbsp;</P><P>We have contacted via email to help you.</P><P>&nbsp;</P><P>Best regards,</P><P><A href="https://community.intel.com/sfdc-users/Mæcenas_INTEL">@Mæcenas_INTEL</A>​.</P> Thu, 23 Apr 2020 01:46:10 GMT CarlosAM_INTEL 2020-04-23T01:46:10Z https://community.intel.com/t5/Embedded-Intel-Core-Processors/CML-PDG-doc-610244-question/m-p/686915#M3358 <P><span class="lia-inline-image-display-wrapper" image-alt="LEX.jpg"><img src="https://community.intel.com/t5/image/serverpage/image-id/2459i6E84FB58A3553823/image-size/large?v=v2&amp;px=999&amp;whitelist-exif-data=Orientation%2CResolution%2COriginalDefaultFinalSize%2CCopyright" role="button" title="LEX.jpg" alt="LEX.jpg" /></span></P><P>Please refer attch picture from CML PDG.</P><P>​If our design not using DSW and G3 flash sharing, still have 6 days limit?</P> Wed, 22 Apr 2020 17:31:54 GMT https://community.intel.com/t5/Embedded-Intel-Core-Processors/CML-PDG-doc-610244-question/m-p/686915#M3358 RSun 2020-04-22T17:31:54Z https://community.intel.com/t5/Embedded-Intel-Core-Processors/CML-PDG-doc-610244-question/m-p/686916#M3359 <P>Hello, <A href="https://community.intel.com/sfdc-users/RSun">@RSun</A>​:</P><P>&nbsp;</P><P>Thank you for contacting Intel Embedded Community.</P><P>&nbsp;</P><P>We have contacted via email to help you.</P><P>&nbsp;</P><P>Best regards,</P><P><A href="https://community.intel.com/sfdc-users/Mæcenas_INTEL">@Mæcenas_INTEL</A>​.</P> Thu, 23 Apr 2020 01:46:10 GMT https://community.intel.com/t5/Embedded-Intel-Core-Processors/CML-PDG-doc-610244-question/m-p/686916#M3359 CarlosAM_INTEL 2020-04-23T01:46:10Z