Coffee lake Memory Throttling Implementation

NeousysD — Mon, 26 Oct 2020 10:45:39 GMT

Can I implement Memory throttling ( EXTTS# mode ) in Coffee Lake?

It has been connect PCH GPP_0 with SPD EVENT_n. (When DIMM temperature over cirtical temperature , SPD EVENT_n will active Low)

But the result was the same with the EVENT_n deassert condition when I used the memory performance test.

Thanks!

Re: Coffee lake Memory Throttling Implementation

CarlosAM_INTEL — Mon, 26 Oct 2020 23:20:04 GMT

Hello, @NeousysD:

Thank you for contacting Intel Embedded Community.

You should review the information stated in Table 6-13, on page 129 of the 8th and 9th Generation Intel® Core™ Processor Families and Intel® Xeon E Processor Family Coffee Lake and Coffee Lake Refresh External Design Specification Volume 1 of 2 document # 570805, and in sections 7.66 and 7.74, on pages 229 and 236 of the 8th and 9th Generation Intel® Core™ Processor Families and Intel® Xeon E Processor Family Coffee Lake and Coffee Lake Refresh External Design Specification Volume 2 of 2 document # 570806, which may answer your questions. You can find these documents when you are logged into your Resource and Design Center (RDC) privileged account on the following websites:

https://cdrdv2.intel.com/v1/dl/getContent/570805

https://cdrdv2.intel.com/v1/dl/getContent/570806

You should fill out the form stated on the following website when you have problems with the provided websites or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

topic Re: Coffee lake Memory Throttling Implementation in Embedded Intel® Core™ Processors

Coffee lake Memory Throttling Implementation

Re: Coffee lake Memory Throttling Implementation