topic Re: SSTL-15 in Embedded Intel® Core™ Processors

SSTL-15

idata — Mon, 21 Sep 2015 13:43:37 GMT

Hello everyone,

I get a problem about SSTL-15 interface circuit.As it's established by JEDEC,I search for this standard in JEDEC.But what I get are SSTL-2 and SSTL-18.They are working for DDR1 and DDR2.There is no SSTL-15 in JEDEC.So I need your help !

Best regards

Lich_Wang

Re: SSTL-15

CarlosAM_INTEL — Mon, 21 Sep 2015 15:36:42 GMT

Hello Fupeng_Wang,

Thank you for contacting Intel Embedded Community.

Based on the following yellow highlighted information as http://www.freescale.com/files/training_pdf/VFTF09_AN111.pdf?lang_cd=en a reference:

The http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-ddr2-ecc-so-dimm-paper.pdf Considerations for designing an Embedded IA System with DDR3 ECC SO-DIMMs and http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/x1000-ddr3-dual-rank-memory-down-schematic-paper.pdf DDR3 Dual Rank Memory Down Schematic Guide White Paper have the information that may help you.

Please let us know if this information is useful to you.

Best Regards,

Carlos A.

Re: SSTL-15

idata — Tue, 22 Sep 2015 01:00:43 GMT

Dear Carlos,

Thanks for your reply.The article you give me teach us how to use DDR3.But I'm afraid it is not the answer I want.SSTL-15 is a kind of voltage level.It has its special I/O circuit.I just want to analyse the circuit.I don't know if this is in your working range.Thanks!

Best regards

Lich_Wang

Re: SSTL-15

CarlosAM_INTEL — Tue, 22 Sep 2015 14:16:26 GMT

Hello Fupeng_Wang,

Thanks for your reply.

In order to help you with your documentation request of the mentioned standard developer, as a reference please address your request by filling out their https://www.jedec.org/contact?category=JEDEC%20Standards%20and%20Documents form.

Please let us know if this information is useful to you.

Best Regards,

Carlos_A

Re: SSTL-15

idata — Wed, 23 Sep 2015 01:08:10 GMT

Dear Carlos,

Thanks for your reply.Maybe this is not in your working range.I have found the SSTL-15 in JEDEC.But the newest one I found is SSTL-18 which is used in DDR2.I think Intel may own the standard because the SSTL circuit is integrated in processor.

Best regards

Lich_Wang

Re: SSTL-15

CarlosAM_INTEL — Wed, 23 Sep 2015 20:27:10 GMT

Hello Fupeng_Wang,

Thanks for your reply.

Could you please clarify us what is the processor or document that has the cited integrated circuit?

Thanks in advance for your cooperation.

Best Regards,

Carlos_A.

Re: SSTL-15

idata — Thu, 24 Sep 2015 00:55:05 GMT

Dear Carlos,

Thanks for your reply.We all know the processor contact memory by using memory controller.Intel use the North Bridge to contain the memory controller long before.In recent years,new platforms have integrated the memory controller into the processor because the North Bridge is integrated in processor too.So,the SSTL-15 interface circuit is in processor mentioned above.Thanks!

Best regards

Lich_Wang

Re: SSTL-15

CarlosAM_INTEL — Thu, 24 Sep 2015 14:07:48 GMT

Hello Fupeng_Wang,

Thanks for your reply.

Please review the information as a reference that may help you:

http://www.aragio.com/io-library-solutions/memoryinterfaces/# memory15 Memory Interfaces: DDR3 – SSTL_15

Summary

The SSTL_15 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since the SSTL_15 normally operates with its own isolated power domain (1.5V), a "rail-splitter" support cell (SPP_RS_005_15V) is included to allow the designer to easily break the lines that should not connect to the rest of the padring, while allowing VDD and VSS to be continuous within the padring.

Features

Full DDR3 capability – 800MHz (1600 Mbps)
Low Power driving standard DDR3 memories
1.8V FETs
Full complement of cells to build padring (20)
Full ODT Capability:
- Either fixed 6-Bit programmation (program from core)
- Or, dynamic 6-Bit PVT calibration (external reference resistor)

Diagram (driver)

Diagram (clock driver)

Recommended Operating Conditions

ParameterDescriptionMinNomMaxUnitsVVDDCore supply voltage0.91.0 to 1.11.115VVDVDDI/O supply voltage1.4251.51.575VVVREFReference voltage0...

Re: SSTL-15

idata — Fri, 25 Sep 2015 00:46:35 GMT

Dear Carlos,

Thanks for your reply.Although the article is not standard,I think it give me inspirations at least.Thanks for your enthusiastic help.

Best ragards

LIch_Wang

Re: SSTL-15

CarlosAM_INTEL — Fri, 25 Sep 2015 12:20:03 GMT

Hello Fupeng_Wang,

Thanks for your update.

We are glad to hear that the information that we have found may help you.

Please do not hesitate to let us know if you have more questions.

Best Regards,

Carlos_A